lecture 8 - cpe 690 introduction to vlsi design

8/13/2019 Lecture 8 - CpE 690 Introduction to VLSI Design

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CpE 690: Digital System DesignFall 2013

Lecture 8Transient Response and Delay

1

Bryan AcklandDepartment of Electrical and Computer Engineering

Stevens Institute of TechnologyHoboken, NJ 07030

Adapted from Lecture Notes, David Mahoney Harris CMOS VLSI Design


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Activity

1) If the width of a transistor increases, the current willincrease decrease not change

2) If the length of a transistor increases, the current willincrease decrease not change

3) If the supply voltage of a chip increases, the maximum

transistor current willincrease decrease not change

4) If the width of a transistor increases, its gate capacitance willincrease decrease not change

5) If the length of a transistor increases, its gate capacitance willincrease decrease not change

6) If the supply voltage of a chip increases, the gate capacitanceof each transistor will

increase decrease not change


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DC analysis tells us V out if Vin is constant

Transient analysis tells us V out (t) in response to a

change in V in

Requires solving differential equations Input is usually considered to be a step or ramp

From GND to V DD or vice versa

Transient Response

GND

VDD

Vin Vout

delay


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tpdr : rising propagation delay maximum time from input

crossing V DD/2 to risingoutput crossing V DD/2

tpdf : falling propagation delay maximum time from input

crossing VDD

/2 to fallingoutput crossing V DD/2

tpd : average propagation delay t pd = (t pdr + t pdf )/2

t r : rise time from output crossing 0.2

VDD to 0.8 V DD

t f : fall time from output crossing 0.8

VDD to 0.2 V DD

Delay Definitions


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tcdf : falling contamination delay minimum time from input

crossing V DD/2 to fallingoutput crossing V DD/2

tcdr : rising contamination delay minimum time from input

crossing V DD/2 to risingoutput crossing V DD/2

tcd : avg. contamination delay

t pd = (t cdr + t cdf )/2

Delay Definitions (cont.)

tcdf

tpdf


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Delay in CMOS Circuits

Switching CMOS gate generates output current inresponse to changing input voltages

All nodes have some finite capacitance (to ground) gate capacitance parasitic source/drain (diode) capacitance parasitic wiring capacitance

Transient waveforms found by solving:

C node (dV node /dt) = I k,nodefor each node in circuit

k

Cnode

Vnode I1,node

I2,node

I3,node


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Inverter Step Response

Find step response of inverter driving C load

V in(t ) = u (t - t 0)V DD

V out (t < t 0) = V DD

d V out (t ) dt = - I dsn (t ) C load

Vin(t) Vout (t)C load

Idsn (t)

I dsn (t )=

0 for t < t 0

( /2 )(V DD V t )2 for V out > V DD V t

(V DD V t V out (t) /2) V out (t) for Vout < V DD - V t

t0

Vin(t)

Vout (t)


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Simulated Inverter Delay

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write!

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

tpdf = 66ps t pdr = 83psVinVout


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Delay Estimation

We would like to be able to easily estimate delay For exploration of design space, dont need to be as accurate as

simulation Want a technique where its easier to ask What if?

The step response usually looks like a 1 st order RCresponse with a decaying exponential.

Can we model conducting transistor as effective resistance?

1.0

0.5

0.0

(V)

20p 40p 60p 80p0

A

ShockleySPICE

RC model


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Effective Resistance

Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis

Simplification: treat transistor as resistor Replace I ds (Vds , Vgs ) with effective resistance R Ids = Vds /R or 0 depending on gate voltage

R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict gate delay


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RC Delay Model

Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C

Capacitance (gate & diffusion) proportional to width

Resistance inversely proportional to width


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RC Values

Capacitance C = C g = C s = C d = 2 fF/ m of gate width in 0.6 m Gradually decline to 1 fF/ m in nanometer techs.

Resistance R 5-10 K m in 0.6 m process Improves with shorter channel lengths

Unit transistors May refer to minimum contacted device (4/2 ) Or maybe W=1 m device (doesnt matter as long as you are consistent)

AMI

0.6 m

TSMC

250nm

TSMC

180nm

IBM

130nm

IBM

65nm

R n (k . m) 9.2 4.0 2.7 2.5 1.3

R n (k .4 ) 7.7 8.0 7.5 9.6 10

R p (k . m) 19.9 8.9 6.5 6.4 2.9

R p (k .4 ) 16.6 17.8 18.1 24.7 22.3


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RC Values

Estimate the delay of a fanout-of-1 inverter

6RC


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Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to

achieve effective rise and fall resistances equal to a unitinverter (R).

2 2 2

3

3

3


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3-input NAND Capacitors

Annotate the 3-input NAND gate with gate and diffusion

capacitance.

2 2 2

3

3

3

2 2 2

3

3

33C

3C

3C

3C

2C

2C

2C

2C

2C

2C

3C

3C

3C

2C 2C 2C


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9C

3C

3C3

3

3

222

5C

5C

5C

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3-input NAND Capacitors

Annotate the 3-input NAND gate with gate and diffusion

capacitance.


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9C

3C

3C3

3

3

222

5C

5C

5C

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Rise & Fall Delay

What are worst-case rise and fall delays?

How can we estimate delay of these networks?


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with multiple RC components

Second order response is too complicated defeats whole purpose of simplifying to an RC network

Can approximate to: =

1 +

2= R

1C

1 + (R

1+R

2).C

2

= RC

= 11 + 1 1 + 1 + 2 . 2 + 2 1 1 2 2


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Elmore Delay

ON transistors modeled as resistors

Pullup or pulldown network represented as an RC tree root of tree is voltage source (often V DD or GND) leaves are capacitors at end of branches

Elmore delay to any target (node j) in the branch:

where: i represents all the nodes in the branch

C i is the capacitance at node i Rsij is the resistance of the shared path from the source to and

from the source to the target

Elmore delay is conservative

over-estimates the delay

= .


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Shared Path

delay to node N is:R1C1 + (R 1+R 2).C 2 + + (R 1+R 2++R n).C N

delay to node 2 is:R1C1 + (R 1+R 2).C 2 + (R 1+R 2).(C 3+C 4++C N)

R1 R 2 R 3 R N

C1 C 2 C 3 C N


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Example: Elmore Delay

Calculate delay from source to all nodes in circuit:

A B C D

E

F

G

H 2R

2R

3R

3R

3R R R

R

C C

C

2CC

2C C

3C

source


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3-input NAND: pull-down delay

Estimate worst-case rising and falling delay of 3-input NAND

driving h identical gates.

h copies

= 3 + 3C + + 9 + 5 ( + + ) = 12 + 5

Worst case pull-down delay occurs when ABC goes from (110) to (111)

A

B

C


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3-input NAND: pull-up delay

Estimate worst-case rising and falling delay of 3-input NAND

driving h identical gates.

h copies

= 9 + 5 C (R) + 3C R + 3C R = 15 + 5

Worst case pull-up delay occurs when ABC goes from (111) to (110)

A

B

C


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Delay Components

Delay has two parts

Parasitic delay 15 or 12 RC Independent of load

Effort delay 5h RC Proportional to load capacitance

= 15 + 5 = 12 + 5


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Contamination Delay

Best-case (contamination) delay can be substantially less

than propagation delay:

if top nMOS is last to turn on:

= 9 + 5

if all pMOS turn on simultaneously:

= 3 +

= 12 + 5 = 15 + 5 compare to:

i.e. ABC goes from (011) to (111) i.e. ABC goes from (111) to (000)


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Diffusion Capacitance

We assumed contacted diffusion on every s / d.

but shared on series nMOS chain Good layout minimizes diffusion area Good NAND3 layout shares one diffusion contact

Reduces output capacitance by 2C

Merged un-contacted diffusion also helps

1.5C 1.5C

1.5C

1.5C


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Layout Comparison

Which layout is better?

AVDD

GND

B

Y

AVDD

GND

B

Y


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Example: Gate delays

For the gate =

+ .

a) Draw the schematic

b) Size the transistors to give pullup and pulldown strength equal to unitsize inverter

c) Annotate with effective R of each transistor and C of each node

d) Calculate worst case rising & falling propagation delay while driving h similar gates (via input B)

e) Calculate best case rising & falling contamination delay while driving hsimilar gates (via input B)

lecture 8 - cpe 690 introduction to vlsi design

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