digital integrated circuits - Študentski.net · 2019. 3. 20. · © digital integrated circuits2nd...

Sequential Circuits

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

November 2002

Sequential Circuits

Sequential LogicSequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

Current State

Inputs

Sequential Circuits

Naming ConventionsNaming Conventions

In our text: a latch is level sensitive a register is edge-triggered

There are many different naming conventions For instance, many books call edge-

triggered elements flip-flops This leads to confusion however

Sequential Circuits

Latch versus RegisterLatch versus Register Latch

stores data when clock is low

Register

stores data when clock rises

Clk Clk

Sequential Circuits

LatchesLatches

Po sitive Latch

Outs tab le

Outfollows In

Neg ative Latch

Outs tab le

Outfollows In

Sequential Circuits

Latch-Based DesignLatch-Based Design

• N latch is transparentwhen φ = 0

• P latch is transparent when φ = 1

NLatch

PLatch

Sequential Circuits

Timing DefinitionsTiming Definitions

tc 2 q

tholdtsu

Q DATASTABLE

DATASTABLE

Register

Sequential Circuits

Characterizing TimingCharacterizing Timing

tC 2 Q

tD 2 Q

Register Latch

Sequential Circuits

Maximum Clock FrequencyMaximum Clock Frequency

tp,comb

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delay

tclkQ + tp,comb + tsetup = T

Sequential Circuits

Positive Feedback: Bi-StabilityPositive Feedback: Bi-StabilityV i1 Vo2

Vo2 = V i 1

Vo1 = V i 2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1

Sequential Circuits

Meta-StabilityMeta-Stability

Gain should be larger than 1 in the transition region

V i1 5 Vo2

Sequential Circuits

Writing into a Static LatchWriting into a Static Latch

Converting into a MUXForcing the state(can implement as NMOSonly)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

Sequential Circuits

Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=

Sequential Circuits

Mux-Based LatchMux-Based Latch

Sequential Circuits

Mux-Based LatchMux-Based Latch

NMOS only Nonoverlapping clocks

Sequential Circuits

Master-Slave (Edge-Triggered) Master-Slave (Edge-Triggered) RegisterRegister

Master

Two opposite latches trigger on edgeAlso called masterslave latch pair

Sequential Circuits

Master-Slave RegisterMaster-Slave Register

I3 T4I5

Multiplexerbased latch pair

Sequential Circuits

Clk-Q DelayClk-Q Delay

tc 2 q(lh)

0.5 1 1.5 2 2.50time, nsec

tc 2 q(hl)

Sequential Circuits

Setup TimeSetup Time

I2 2 T2

0.2 0.4time (nsec)

(a) Tsetup5 0.21 nsec

0.6 0.8 10

I2 2 T2

2 0.5V

0.2 0.4time (nsec)

(b) Tsetup5 0.20 nsec

0.6 0.8 10

Sequential Circuits

Reduced Clock Load Reduced Clock Load Master-Slave RegisterMaster-Slave Register

D QT1 I1

Sequential Circuits

Avoiding Clock OverlapAvoiding Clock OverlapCLK

(a) Schematic diagram

(b) Overlapping clock pairs

Sequential Circuits

Overpowering the Feedback Loop ─Overpowering the Feedback Loop ─Cross-Coupled PairsCross-Coupled Pairs

Forbidden State

011 0RQ

NORbased setreset

Sequential Circuits

Cross-Coupled NANDCross-Coupled NAND

M8 CLK

Crosscoupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell

Sequential Circuits

Sizing IssuesSizing Issues

Output voltage dependence on transistor width

Transient response

4.03.53.0W/L5 and 6

2.52.00.0

time (ns)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

W = 1 mµ

W = 0.9 mµW = 0.8 mµ

W = 0.7 mµW = 0.6 mµ

W = 0.5 m

Sequential Circuits

Storage MechanismsStorage Mechanisms

Dynamic (chargebased)

Static

Sequential Circuits

Making a Dynamic Latch Pseudo-StaticMaking a Dynamic Latch Pseudo-Static

Sequential Circuits

More Precise Setup TimeMore Precise Setup Time

tD 2 C

tC 2 Q1.05tC 2 Q

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Setup/Hold Time IllustrationsSetup/Hold Time Illustrations

Circuit before clock arrival (Setup1 case)

Inv2TG1

Timet=0

ClockDataTSetup-1

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Inv2TG1

Timet=0

ClockDataTSetup-1

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Timet=0

ClockDataTSetup-1

Inv2TG1

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Inv2TG1

Timet=0

ClockDataTSetup-1

Sequential Circuits

Timet=0

ClockDataTSetup-1

Inv2TG1

Clk-Q Delay

TSetup-1

TClk-Q

Sequential Circuits

Hold1 case

Inv2TG1

Timet=0

DataClockTHold-1

Clk-Q Delay

THold-1

TClk-Q

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Timet=0

DataClockTHold-1

Hold1 case

Inv2TG1

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Inv2TG1

Timet=0

DataClockTHold-1

Hold1 case

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Inv2TG1

Timet=0

THold-1

Hold1 case

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Inv2TG1

Timet=0

THold-1

Hold1 case

Sequential Circuits

Other Latches/Registers: COther Latches/Registers: C22MOSMOS

Master Stage

CLK M8

“Keepers” can be added to make circuit pseudostatic

Sequential Circuits

Insensitive to Clock-OverlapInsensitive to Clock-Overlap

(a) (0-0) overlap

(b) (1-1) overlap

Sequential Circuits

PipeliningPipeliningR

Reference Pipelined

Sequential Circuits

Other Latches/Registers: TSPCOther Latches/Registers: TSPC

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

Sequential Circuits

Including Logic in TSPCIncluding Logic in TSPC

CLKIn CLK

VDDVDD

In1 In2

AND latchExample: logic inside the latch

Sequential Circuits

TSPC RegisterTSPC Register

Sequential Circuits

Pulse-Triggered LatchesPulse-Triggered LatchesAn Alternative ApproachAn Alternative Approach

Master-Slave Latches

Pulse-Triggered Latch

L1 L2 L

Ways to design an edgetriggered sequential cell:

Sequential Circuits

Pulsed LatchesPulsed Latches

(a) register (b) glitch generation

Sequential Circuits

Pulsed LatchesPulsed LatchesHybrid Latch – Flipflop (HLFF), AMD K6 and K7 :

Sequential Circuits

Hybrid Latch-FF TimingHybrid Latch-FF Timing

0.20.0 0.4

time (ns)

0.6 0.8 1.0

CLKDCLK

Sequential Circuits

Latch-Based PipelineLatch-Based Pipeline

In Out

Compute F compute G

Sequential Circuits

Non-Bistable Sequential Circuits─Non-Bistable Sequential Circuits─Schmitt TriggerSchmitt Trigger

In Out

VoutVOH

VM– VM+

•VTC with hysteresis•Restores signal slopes

Sequential Circuits

Noise Suppression using Schmitt Noise Suppression using Schmitt TriggerTrigger

t0 + tp t

Sequential Circuits

CMOS Schmitt TriggerCMOS Schmitt Trigger

Moves switching thresholdof the first inverter

X Vout

Sequential Circuits

Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4 . The width isk* 0.5 m.m

0.00.0 0.5 1.0 1.5 2.0 2.5

k = 2k = 3

Vin (V)

0.00.0 0.5 1.0 1.5 2.0 2.5

Sequential Circuits

CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)

Sequential Circuits

Multivibrator CircuitsMultivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

Sequential Circuits

Transition-Triggered MonostableTransition-Triggered Monostable

Sequential Circuits

Monostable Trigger (RC-based)Monostable Trigger (RC-based)VDD

InOutA B

(a) Trigger circuit.

(b) Waveforms.

Sequential Circuits

Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

2.5V1 V3 V5

20.50.5

time (ns)

1.0 1.5

Sequential Circuits

Relaxation OscillatorRelaxation Oscillator

T = 2 (log3) RC

Sequential Circuits

Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

propagation delay as a functionof control voltage

Sequential Circuits

Differential Delay Element and VCODifferential Delay Element and VCO

two stage VCO

Vo 2 Vo 1

delay cell

simulated waveforms of 2-stage VCO

20.51.5

V1 V2 V3 V4

time (ns)2.5 3.5

digital integrated circuits - Študentski.net · 2019. 3. 20. · © digital integrated circuits2nd...

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