1

Digital Integrated

CircuitsA Design Perspective

Designing Combinational

Logic Circuits

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolić

November 2002.

2

Combinational vs. Sequential Logic

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

CombinationalLogicCircuit

OutInCombinational

LogicCircuit

OutIn

State

3

Static CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to eitherVDD or Vss via a low-resistive path.

The outputs of the gates assume at all times the value

of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

4

Static complementary CMOS - except during switching, output connected to either VDD or GND via a low-resistance path

high noise margins

- full rail to rail swing

- VOH and VOL are at VDD and GND, respectively

low output impedance, high input impedance

no steady state path between VDD and GND (no static power consumption)

delay a function of load capacitance and transistor resistance

comparable rise and fall times (under the appropriate transistor sizing conditions)

Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes

simpler, faster gates

increased sensitivity to noise

CMOS Circuit Styles

CSE477 L06 Static CMOS Logic.5 Irwin&Vijay, PSU, 2003

Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PUN and PDN are dual logic networks

Pull-up network (PUN) and pull-down network (PDN)

PMOS transistors only

pull-up: make a connection from VDD to F

when F(In1,In2,…InN) = 1

NMOS transistors only

pull-down: make a connection from F to

GND when F(In1,In2,…InN) = 0

6

NMOS Transistors

in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

XY

A

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors

in Series/Parallel Connection

X Y

A B

Y = X if A AND B = A + B

XY

A

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

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Threshold Drops

VDD

VDD 0PDN

0 VDD

CL

CL

PUN

VDD

0 VDD - VTn

CL

VDD

VDD

VDD |VTp|

CL

S

D S

D

VGS

S

SD

D

VGS

CSE477 L06 Static CMOS Logic.9 Irwin&Vijay, PSU, 2003

Construction of PDN

NMOS devices in series implement a NAND function

NMOS devices in parallel implement a NOR function

A

B

A • B

A B

A + B

CSE477 L06 Static CMOS Logic.10 Irwin&Vijay, PSU, 2003

Dual PUN and PDN

PUN and PDN are dual networks

DeMorgan’s theorems

A + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B]

A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]

a parallel connection of transistors in the PUN corresponds to a series connection of the PDN

Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)

Number of transistors for an N-input logic gate is 2N

11

Complementary CMOS Logic Style

12

Example Gate: NAND

13

Example Gate: NOR

14

Complex CMOS Gate

OUT = D + A • (B + C)

D

A

B C

D

A

B

C

15

Constructing a Complex Gate

C

(a) pull-down network

SN1 SN4

SN2

SN3D

FF

A

DB

C

D

F

A

B

C

(b) Deriving the pull-up networkhierarchically by identifyingsub-nets

D

A

A

B

C

VDD VDD

B

(c) complete gate

RC Delay Model

• Use equivalent circuits for MOS transistors

• Ideal switch + capacitance and ON resistance

• Unit nMOS has resistance R, capacitance C

• Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width

• Resistance inversely proportional to width

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Switch Delay Model

A

Req

A

Rp

A

Rp

A

Rn CL

A

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

NAND2 INVNOR2

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Input Pattern Effects on Delay

Delay is dependent on the pattern of inputs

Low to high transition both inputs go low

– delay is 0.69 Rp/2 CL

one input goes low– delay is 0.69 Rp CL

High to low transition both inputs go high

– delay is 0.69 2Rn CL

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

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Adding devices in series slows down the circuit, and devices must

be made wider to avoid performance penalty.

When sizing the transistors in a gate with multiple inputs, we

should pick the combination of inputs that triggers the worst case

conditions.

For the NAND gate to have the same pull-down delay (tphl) with

an inverter, the NMOS devices in the PDN stack must be made

twice as wide (2.5 times, if velocity saturation is effective).

PMOS devices can remain unchanged.

(Extra capacitance introduced by widening is ignored here, which

is not a good assumption)

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Delay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=10

A=1, B=10

A=1 0, B=1

time [ps]

Vo

lta

ge

[V

]

Input Data

Pattern

Delay

(psec)

A=B=01 67

A=1, B=01 64

A= 01, B=1 61

A=B=10 45

A=1, B=10 80

A= 10, B=1 81

NMOS = 0.5m/0.25 m

PMOS = 0.75m/0.25 m

CL = 100 fF

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Transistor Sizing

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

2

2

2 2

11

4

4

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Transistor Sizing a Complex

CMOS Gate

OUT = D + A • (B + C)

D

A

B C

D

A

B

C

1

2

2 2

4

4

8

8

6

3

6

6

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Fan-In Considerations

DCBA

D

C

B

A CL

C3

C2

C1

Distributed RC model

(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates

rapidly as a function of fan-in –

quadratically in the worst case.

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tp as a Function of Fan-In

tpL

H

t p(p

se

c)

fan-in

Gates with a

fan-in

greater than

4 should be

avoided.

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpHL

quadratic

linear

tp

tpLH

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tp as a Function of Fan-Out

2 4 6 8 10 12 14 16

tpNOR2

t p(p

se

c)

eff. fan-out

All gates

have the

same drive

current.

tpNAND2

tpINV

Slope is a

function of

“driving

strength”

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tp as a Function of Fan-In and Fan-Out

Fan-in: quadratic due to increasing

resistance and capacitance

Fan-out: each additional fan-out gate

adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

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Fast Complex Gates:

Design Technique 1

Transistor sizing

as long as fan-out capacitance dominates

Progressive sizing

InN CL

C3

C2

C1In1

In2

In3

M1

M2

M3

MNDistributed RC line

M1 > M2 > M3 > … > MN

(the fet closest to the

output is the smallest)

Can reduce delay by more than

20%; decreasing gains as

technology shrinks

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Fast Complex Gates:

Design Technique 2

Transistor ordering

C2

C1In1

In2

In3

M1

M2

M3 CL

C2

C1In3

In2

In1

M1

M2

M3 CL

critical path critical path

charged1

01charged

charged1

delay determined by time to

discharge CL, C1 and C2

delay determined by time to

discharge CL

1

1

01 charged

discharged

discharged

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Fast Complex Gates:

Design Technique 3

Alternative logic structures

F = ABCDEFGH

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Fast Complex Gates:

Design Technique 4

Isolating fan-in from fan-out using buffer

insertion

CLCL

Logical Efforttp = tp0 (1 + Cext/ Cg) = tp0 (1 + f/)

tp = tp0 (p + g f/)

tp0 is the intrinsic delay of an inverter

f is the effective fan-out (Cext/Cg) – also called the electrical effort

p is the ratio of the instrinsic (unloaded) delay of the complex gate and a

simple inverter (a function of the gate topology and layout style)

g is the logical effort of the complex gate - how much more input

capacitance a gate presents to deliver the same output current as an

inverter (how much worse it is at producing output current than an

inverter)

Normalize everything to an inverter: ginv=1, pinv= 1

P = n for n input NAND and NOR gates

Assume γ = 1.

32

Logical Effort

Inverter has the smallest logical effort and

intrinsic delay of all static CMOS gates

Logical effort of a gate presents the ratio of its

input capacitance to the inverter capacitance

when sized to deliver the same current

Logical effort increases with the gate

complexity

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Delay in a Logic Gate

Gate delay:

d = h + p

effort delay intrinsic delay

Effort delay:

h = g f

logical

effort

effective fanout =

Cout/Cin

Logical effort is a function of topology, independent of sizing

Effective fanout (electrical effort) is a function of load/gate size

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Logical EffortPMOS/NMOS ratio of 2, the input capacitance of a minimum

sized symmetrical inverter equals 3 times the gate capacitance of a

minimum sized NMOS (called Cunit)

g = 1

(3 Cunit)

g = 4/3

(4 Cunit)

g = 5/3

(5 Cunit)

B

A

A B

F

VDDVDD

A B

A

B

F

VDD

A

A

F

1

2 2 2

2

2

1 1

4

4

Inverter 2-input NAND 2-input NOR

CSE477 L11 Fast Logic.35 Irwin&Vijay, PSU, 2003

Intrinsic Delay Term, p

The more involved the structure of the complex gate, the higher the intrinsic delay compared to an inverter

Gate Type p

Inverter 1

n-input NAND n

n-input NOR n

n-way mux 2n

XOR, XNOR n 2n-1

Ignoring second order effects such as internal node capacitances

36

Logical Effort

From Sutherland, Sproull

37

Logical Effort of Gates

Fan-out (h)

No

rmaliz

ed

de

lay (

d)

t

1 2 3 4 5 6 7

pINV

tpNAND

F(Fan-in)

g =

p =

d =

g =

p =

d =

38

Logical Effort of Gates

Fan-out (h)

No

rmaliz

ed

de

lay (

d)

t

1 2 3 4 5 6 7

pINV

tpNAND

F(Fan-in)

g = 1

p = 1

d = f+1

g = 4/3

p = 2

d = (4/3)f+2

𝑑 = 𝑝 + 𝑔 ⋅ 𝑓

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Delay as a Function of Fan-Out

Intrinsic Delay

EffortDelay

1 2 3 4 5

Fanout f

1

2

3

4

5

Inver

ter:

g = 1

; p = 1

2-in

put N

AN

D: g

= 4

/3; p

= 2

Norm

aliz

ed D

elay

• The slope of the line is

the logical effort of the

gate (d = p + fg)

• The y-axis intercept is the

intrinsic delay

• Can adjust the delay by

adjusting the effective

fan-out (by sizing) or by

choosing a gate with a

different logical effort

• Gate effort: h = fg

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Multistage Networks

Total delay of a path: 𝑡𝑝 = 𝑗=1𝑁 𝑡𝑝,𝑗 = 𝑡𝑝0 𝑗=1

𝑁 𝑝𝑗 +𝑓𝑗𝑔𝑗

𝛾

Using a a similar procedure with the sizing of the inverter

chain (finding N-1 partial derivatives and equating to

zero), we find that each stage should bear the same

gate effort:

𝑓1𝑔1 = 𝑓2𝑔2 = ⋯𝑓𝑁𝑔𝑁

Here we have some definitions:

Path effective fan-out (Path electrical effort): F = Cout/Cin

Path logical effort: G = g1g2…gN

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Branching effort of a logical gate on a path:

𝑏 =𝐶𝑜𝑛−𝑝𝑎𝑡ℎ + 𝐶𝑜𝑓𝑓−𝑝𝑎𝑡ℎ𝐶𝑜𝑛−𝑝𝑎𝑡ℎ

Path branching effort: 𝐵 = 1𝑁 𝑏𝑖

The path electrical effort can now be related to the

electrical and branching efforts:

𝐹 =

1

𝑁𝑓𝑖𝑏𝑖= 𝑓𝑖𝐵

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Finally the total path effort H can be defined:

𝐻 =

1

𝑁

ℎ𝑖 =

1

𝑁

𝑔,𝑓𝑖 = 𝐺𝐹𝐵

From here on, the analysis can be carried out as in the

case of inverter chain. The gate effort that minimizes

the path delay is:

ℎ =𝑁𝐻

And the minimum delay through the path is:

𝐷 = 𝑡𝑝0

𝑗=1

𝑁

𝑝𝑗 +𝑁𝑁𝐻

𝛾

43

We assume that a unit-size gate has a driving capability equal

to a minimum-size inverter. This means that its input

capacitance is g times larger than that of the reference inverter

(Cref). With s1the sizing factor of the first gate in the chain, the

input capacitance of the chain can be written as:

𝐶𝑔1= 𝑔1𝑠1𝐶𝑟𝑒𝑓Including the branching effort, the input capacitance of gate 2

will be 𝑓1/𝑏1 times larger:

𝑔2𝑠2𝐶𝑟𝑒𝑓 =𝑓1

𝑏1𝑔1𝑠1𝐶𝑟𝑒𝑓 For gate i in the chain:

𝑠𝑖 =𝑔1𝑠1𝑔𝑖

𝑗=1

𝑖−1𝑓𝑗𝑏𝑗

46

Example: Optimize Path

Effective fanout, F =

G =

H =

h =

a =

b =

1a

b c

5

g = 1

f = ag = 5/3

f = b/a

g = 5/3

f = c/b

g = 1

f = 5/c

47

Example: Optimize Path

1a

b c

5

g = 1

f = ag = 5/3

f = b/a

g = 5/3

f = c/b

g = 1

f = 5/c

Effective fanout, F = 5

G = 1x(5/3)x(5/3)x1 = 25/9

H = GFB (no branching)=125/9 = 13.9

h = 4𝐻 =1.93

since 𝑓1𝑔1 = 𝑓2𝑔2 = 𝑓3𝑔3 = 𝑓4𝑔4 = ℎ:𝑓1 = 1.93, 𝑓2 = 1.93 × (3/5) = 1.16, 𝑓3 = 1.16, 𝑓4 = 1.93

𝑎 = 𝑠2 = 𝑓1𝑔1/𝑔2 = 1.16

𝑏 = 𝑠3 =𝑓1𝑓2𝑔1𝑔3= 1.34

𝑐 = 𝑠4 = 𝑓1𝑓2𝑓3𝑔1/𝑔4 = 2.60

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Example – 8-input AND

G=3.33 G=3.33 G=2.96

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Method of Logical Effort

Compute the path effort: F = GBH

Find the best number of stages N ~ log4F

Compute the stage effort f = F1/N

Sketch the path with this number of stages

Work either from either end, find sizes:

Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

51

Summary

Sutherland,

Sproull

Harris