eel 4783: hdl in digital system design - eecs.ucf.edueecs.ucf.edu/~mingjie/eel4783/lect.10a.pdf ·...
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EEL 4783: HDL in Digital System Design
Lecture 10: Sequential Logic in Verilog*
Prof. Mingjie Lin
*Poras T. Balsara & Dinesh K. Bhatia
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D Flip-Flop w/ Asynch Reset in Verilog
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D Flip-Flop w/ Synch Reset in Verilog
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Verilog Testbench for D Flip - flop
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Sequential Logic Design Using Verilog
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Example: Mealy Machine Implementation
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Mealy Machine in Verilog HDL
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Mealy Machine in Verilog HDL (contd...)
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Example: Moore Machine Implementation
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Moore Machine in Verilog HDL (contd...)
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Verilog Testbenches for Sequential Circuits
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Blocking (=) vs Non-Blocking (<=)
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Final issues
• Please fill out the student info sheet before leaving
• Come by my office hours (right after class)
• Any questions or concerns?
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