eel 4783: hdl in digital system design - eecs.ucf.edueecs.ucf.edu/~mingjie/eel4783/lect.10a.pdf ·...

1 EEL 4783: HDL in Digital System Design Lecture 10: Sequential Logic in Verilog* Prof. Mingjie Lin *Poras T. Balsara & Dinesh K. Bhatia

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EEL 4783: HDL in Digital System Design

Lecture 10: Sequential Logic in Verilog*

Prof. Mingjie Lin

*Poras T. Balsara & Dinesh K. Bhatia

Page 2: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

D Flip-Flop w/ Asynch Reset in Verilog

Page 3: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

D Flip-Flop w/ Synch Reset in Verilog

Page 4: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Verilog Testbench for D Flip - flop

Page 5: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Sequential Logic Design Using Verilog

Page 6: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Example: Mealy Machine Implementation

Page 7: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Mealy Machine in Verilog HDL

Page 8: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Mealy Machine in Verilog HDL (contd...)

Page 9: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Example: Moore Machine Implementation

Page 10: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Moore Machine in Verilog HDL (contd...)

Page 11: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Verilog Testbenches for Sequential Circuits

Page 12: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Blocking (=) vs Non-Blocking (<=)

Page 13: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg

Final issues

• Please fill out the student info sheet before leaving

• Come by my office hours (right after class)

• Any questions or concerns?

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