Transcript
![Page 1: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/1.jpg)
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EEL 4783: HDL in Digital System Design
Lecture 10: Sequential Logic in Verilog*
Prof. Mingjie Lin
*Poras T. Balsara & Dinesh K. Bhatia
![Page 2: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/2.jpg)
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D Flip-Flop w/ Asynch Reset in Verilog
![Page 3: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/3.jpg)
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D Flip-Flop w/ Synch Reset in Verilog
![Page 4: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/4.jpg)
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Verilog Testbench for D Flip - flop
![Page 5: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/5.jpg)
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Sequential Logic Design Using Verilog
![Page 6: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/6.jpg)
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Example: Mealy Machine Implementation
![Page 7: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/7.jpg)
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Mealy Machine in Verilog HDL
![Page 8: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/8.jpg)
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Mealy Machine in Verilog HDL (contd...)
![Page 9: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/9.jpg)
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Example: Moore Machine Implementation
![Page 10: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/10.jpg)
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Moore Machine in Verilog HDL (contd...)
![Page 11: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/11.jpg)
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Verilog Testbenches for Sequential Circuits
![Page 12: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/12.jpg)
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Blocking (=) vs Non-Blocking (<=)
![Page 13: EEL 4783: HDL in Digital System Design - eecs.ucf.edueecs.ucf.edu/~mingjie/EEL4783/lect.10a.pdf · module test fsm (reset, clk, in output reset, clk, in seq; reset, clk, in seq; reg](https://reader031.vdocument.in/reader031/viewer/2022022516/5b00e6407f8b9af1148d56a8/html5/thumbnails/13.jpg)
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Final issues
• Please fill out the student info sheet before leaving
• Come by my office hours (right after class)
• Any questions or concerns?