AbstractThe advanced power electronic packagingtechnology developed at GE CRD eliminates theneed for wire bonds, offers low inductance strip-lined power electrodes, and low parasiticimpedance. In addition, the planarity of the toplayer structure and the thermal base providedouble-sided cooling capability and improve thesize, weight, cost, and thermal and electricalperformance of the package.

IntroductionThe advanced Chip on Flex Power OverlayTechnology (POL) offers significant advantagesover the state of the art power modules availableon the market to day. Higher packaging density,lower package parasitics, higher reliability, lowerweight and size and higher efficiency are amongthe key advantages of this technology.

One of the most important features of the POL isthe elimination of bond wires. The power andcontrol circuit to device interconnections isachieved through metalized through holes. Thisapproach dramatically reduces the interconnectlength, interconnect parasitics, and increasespackaging density by allowing us to pack powerdevices more closely.

Another extremely important feature of the POLis the double-sided integral heat exchangerdesign. Thermally, the chip on flex approachcreates a planar interface that makes it possibleto remove the heat from the topside of themodule. The low thermal resistance of the topside path between the heat sink and the top layerof the power devices where most of the heatgeneration takes place offers improved thermalperformance compare to cooling through theback side of power devices. It is also nowpossible to employ double sided cooling whichcan more than double the thermal performance ofpower module. Therefore, the improved thermalperformance strongly couples with andcomplements the no wire bond approachallowing us to take full advantage of the POL

Because of these, two key features and fullystriplined power electrode design the moduleEMI will be significantly lowered and themodule efficiency will be improved. A naturaloutcome of these enhancements is the ability toswitch the advanced power devices at higherspeeds and frequencies without pushing thelimits of SOA of power devices. The reducedparasitics, particularly reduced L di/dt noise willallow us to use power devices with lowerbreakdown voltage, which improves both thecost and the electrical efficiency of modules.Ultimately the size weigh and the cost of passivefilter components will also go down.

A Cost effective fabrication approachThe CF POL technology is designed to make useof the commercially available materials,processes and equipment wherever possible. Themanufacturability, cost and reliability factorswere incorporated early in the design. Thefollowing paragraphs describe the various stepsof the fabrication technology.

Step 1. A thin layer of organic dielectric sheet isattached to a carrier frame, figure 1. The carrierframe will offer a convenient way for transport,ease of handling and dimensional stability. Thethermal, structural and electrical properties of thespecific dielectric film are compatible with thecost, reliability and the performance goals. Thelow modulus (high compliance), low CTE of thedry film dielectric improve the thermal/structuralreliability of the power module.

Step 2. The via pattern for device power andcontrol connections are made by a laser ormechanical punch. Figure 2. The stretcheddielectric membrane contains multiple powermodules. The frame improves the dimensionalstability of the membrane allowing a tighter

An Advanced Approach to Power Module Packaging

Burhan Ozmat, Charlie S. Korman, Ray Fillion

GE CRD, One Research Center, Niskayuna NY 12309

Figure1. The dry film dielectric is attached to aring shaped carrier frame

spacing for vias. Increased via density reducesthe resistive losses and current crowding.

Step 3. A partially cured polymer resin (bondlayer) is applied to dry film dielectric sheet (amembrane). The bond layer is typically a ~0.0005 inch thick layer of acrylic or epoxy resin,Figure 3. The bond layer and a protectiverelease layer may be attached to the membranebefore the formation of the via holes for thepower interconnect. Alternately, the bond layermay be applied after forming the vias.

Blanket sputtering of a layer of adhesion metaland a layer of conductive metal over the Almetalization follows the cleaning process. Theadhesion and conductive metal layers are usuallyTi and Cu, respectively, figure 5.Subsequently, an approximately 0.005 inch thickconductive Cu layer is electroplated over thesputtered Cu seed layer. The plated blanket Culayer then subtractively patterned to form thepower and the control circuit and their I/O pads.

Figure 2) Form 0.020" diameter vias on 0.050"staggered centers (a typical configuration)

Figure 5. RIE or sputter clean the excess polymer

Step 6. In step 6 the power devices will beconnected to an electrically insulating butFigure 3) A partially cured B-stage bond layer

is applied over the membrane

layer and the aluminum oxide layer, blanketmetalize with Ti and Cu, plate up with Cu andpattern

Step 4. Pick and place the power devices downon the glue layer. Cure the glue layer in avacuum oven under low pressure to achievebonding of power devices to the membrane. Notethat during the cure process some resin from thebond layer will be squeezed in to the holecovering the device metalization as a ring ofcured resin. The effect of this ring of cured resinwill depend on the ratio of the width of the ringto the diameter of the hole. The exposed cureresin needs to be cleaned before furtherprocessing, if this ratio is 0.2 or higher.

thermally conducting base plate. This base willbe fabricated by metalizing an approximately0.040 inch thick AlN plate by Cu and CuMo30infiltrated composite from both the front and theback side as shown in the Figure 6. Thestandard solderable backside metalization of thepower devices will be bonded to Cu metalizationof the power circuit formed over the AlN thermalbase.

The second layer of the power circuit will befabricated by directly active brazing one ormultiple, physically separated layers of Cusheets with different thickness to the AlNthermal plate. The over sized Cu sheets will beetched to provide a design specific pattern

consisting of three or more different thickness,and the power and control electrodes. Thethickness will include the full and a fraction ofthe original Cu sheet(s), and zero Cu thickness.The selective etch process will be carried out inmultiple steps that will provide the circuit patternand the desired thickness variations. TheFigure 4. Pick and place power devices over the

Step 5. Sputter clean the residual glue layer andthe thin aluminum oxide layer from the standardtop layer metalization (Al) of all power devices.

thickness variations will accommodate thevariation in the thickness of different types ofpower devices fabricated by different suppliers.The approach can easily accommodate thethickness variations up to 0.015 inch in astepwise fashion. The screened and reflowedsolder thickness (≈ 0.003 inch) will help to

glue layer. To achieve bonding, cure the bondlayer in a vacuum oven

accommodate the statistical variations in thethickness of power devices and the thickness ofthe etched layers both of which is usually lessthan +/- 0.001 inch.

It is important to note that the selective etchprocess is required only if double sided coolingapproach is necessary or the current density ismore than what ~.005 inch thick plated up Cucan support (~1000Amp). Otherwise, theflexible POL can accommodate differences indevice height.

Advantageously, due to the planarity, thisstructure provides a double-sided cooled moduledesign. Double-sided cooling takes advantage ofthe planarity of the top (first) layer of the powercircuit. The top layer power circuit can bemirror-imaged on an oversized copper sheet ofthe upper thermal base assembly that is activelybrazed to an Aluminum Nitrate plate, asdescribed above. Since such a coppermetalization can carry the required currentlevels, the thickness of the plated-up Cu layermay be significantly reduced.

The metalized and patterned membrane carryingthe power devices are then situated between thecopper-metalized aluminum nitride sheets andsoldered in a single or two step, fluxlesssoldering process in a reducing atmosphere

For a non-hermetic commercial power moduledesign, the copper-metalized aluminum nitridethermal plates are attached to infiltrated CuMo30composite plates. An exemplary thickness ofcopper-molybdenum plates is in the 0.050 inchto 0.100-inch range, as determined by themodule size and stiffness requirements.

SummaryA new approach to packaging high performancepower devices was presented. It was shown thatthe GE’s cost effective POL Power packagingtechnology is ideally suited for high heat fluxand high performance applications. This isprimarily due to the elimination of bond wiresand the planar geometry which offers cooling ofpower devices from top, bottom or both sides ofthe power module. It was also shown that a costeffective, scaleable high performance integralheat exchanger can maximizes the thermalperformance of POL technology thereby helpingto utilize its full potential.

Due to the excellent thermal and electricalperformance, low weight, volume, and costeffectiveness GE’s revolutionary POLtechnology sets a new standard for the future ofPackaging Power Electronics Modules.

AcknowledgementsAuthors greatly acknowledge Dr. Kirk Yerkesand Dr. John Leland of USAF for theirencouragement and recommendations during thecourse of this study. The financial support ofUSAF contract F33615-98-2-2909 is alsoappreciated.Last but not the least; the authors would like tothank Paul McConnelee and MustansirKheraluwala for their valuable support duringthe development of POL.

Active braze preforms

CuMo30composite

AlN

Cu

Figure 6. Insulating thermal base fabrication:active brazed partially and fully etched Cu andinfiltrated CuMo composite sheets on AlN baseplates

Active braze preforms

CuMo30composite

AlN

Cu

Figure 6. Insulating thermal base fabrication:active brazed partially and fully etched Cu andinfiltrated CuMo composite sheets on AlN baseplates

APPENDIX:A POL version of a commercial module:

As a part of commercialization efforts, the POLtechnology was transferred to V. Tech packaginglaboratory directed by Prof. Guo-Quan Lu. ThePOL approach is among the leading candidatesof standard technology for future powermodules by CPES consortium.As a demonstration vehicle, GE CRD built afully functional POL version of the Semikron’scommercial Semitop-2 power module (halfbridge 200 A, 600 V Mosfet version), seeFigures 1A. More recently a 200A, 1200VIGBT version of the same module was built byV-Tech packaging laboratory.

SEMIKRON SEMITOP-2 POWER MODULE

Finished COF POL Frames for Semik

Device side

Pin Attached POL

2

(1/2 Bridge 100Amp - 600V Trench Mosfet)

GT1

GB1

MB

~+ DC

- DC

WIRE BOND BASELINE

GB

GT +CTCBET~

-EB

ron’s Semitop-2 Power Module

Power Circuit side

soldered on the base

Figure 1A. A POL version of the Semitop-