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An Automated Systematic CDC Verification Methodology based on
SDC setup Ashish Hari, Sulabh Kumar Khare
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Agenda CDC Verification Challenge Traditional CDC Verification Methodology Proposed Non-iterative Methodology Decoding SDC for CDC Visualize and validate SDC Setup Conclusions
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Quality of Verification
Time to Complete
Verification
Cost Impact
CDC Verification Approach
Feature Loaded Designs
- IP Reuse - Multi Mode - Low Power
Multi-Site Development & Integration
CDC Verification Challenge
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Design Flow
• Architecture, Design &
Block development can happen across geographies
• IP Blocks are pre-verified for CDC errors by Vendor
• Verification team is usually different from the designer team
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Traditional CDC Verification Methodology
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Loop
Extra
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Limitations • Iterative Process • Extra load on CDC tool – Suboptimal Setup • Information extraction is difficult
– Designer access is limited at this stage – Information is gathered in no standard format.
• Constraints extraction manual and time consuming process – Validating the constraints is another challenge
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PROPOSED NON-ITERATIVE METHODOLOGY
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Use SDC as standard CDC setup file • Static Timing Analysis (STA) constraint information is specified
using a de-factor standard format: SDC (Synopsys Design Constraints File)
• CDC And STA are both complimentary verification problems caused by clock relations ships. CDC verifies logic across asynchronous domains. STA verifies logic under synchronous domains.
• SDC setup is generally reliable and available at various stages of design flow. Designers and verification engineers understand SDC.
• Design constraint information in SDC can be translated or directly used as CDC setup to start CDC Verification.
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CDC Verification Flow with SDC setup
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Designer Knowledge
Optimal Setup for Tool Run
SDC setup exists at all
stages
Non Iterative Methodology
Info Updated at Right Place Right Source
Accurate Results
SDC
Start CDC verification
Constraint setup from SDC file
Run CDC tool
Analyze Results
Fix CDC errors
SDC
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Extracting CDC constraints from SDC Decoding SDC for CDC
1. Inferring correct clock domains 2. Constraining primary ports in correct clock domains 3. Identifying constants 4. Identifying functional false paths
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create_clock : Specifies primary Clocks create_generated_clock : Specifies derived clocks Infer all clocks as synchronous by default. Asynchronous categorization is inferred from - set_clock_groups : Mark clocks as asynchronous set_false_path : If specified between clocks, such clocks are asynchronous
Port Domain Inference ( Port-Clock Relation) constraints – set_input_transition set_input_delay set_output_delay
Constant Port Information (Mode Signals) set_case_analysis set_logic_zero set_logic_one
Functional false paths are also specified using – set_false_path -from <tx-sig> -to <rx-sig>
Visualize and validate SDC Setup
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• SDC setup is developed primarily for timing tools • Validation of constraints is critical to qualify for CDC
verification • Debug tool for SDC setup validation:
– Visualize the SDC clocks tree – Qualify then grouping of clocks – Debug the clock grouping using a SDC command
graph
Visualize clock tree
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– Visualize the SDC clocks tree – Qualify then grouping of clocks
Debug using commands Graph
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– Debug the clock grouping using a SDC command graph
– Identify culprit commands in case of any broken assumption
Challenges
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Extracting CDC Information from SDC File is critical. SDC File can be incomplete or incorrect
Incorrect SDC file or errors in decoding it can adversely impact verification setup.
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Conclusion • Easy and Reliable Setup • Iterative nature of CDC methodologies is eliminated
by standard setup – Acceptable results are attained in first iteration itself.
• Constraints validated with visual aids before applying to CDC
• Experiments with proposed methodology highlight all these benefits on customer designs.
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Questions
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