an12284 4 result29 5 conclusion 32 rev. 1 — december 2019 application note 6 ... · 2019. 12....

1 IntroductionCoreMark, developed by EEMBC, is a simple, yet sophisticated benchmarkthat is designed specifically to test the functionality of an embedded processorcore. Running CoreMark produces a single-number score allowing users tomake quick comparisons between processors.

LPC55xx is an Arm® Cortex® -M33 based microcontroller for embeddedapplications. These devices include:

• An Arm Cortex-M33 coprocessor

• CASPER Crypto/FFT engine

• PowerQuad hardware accelerator for DSP functions

• Up to 320 KB of on-chip SRAM, up to 640 KB on-chip flash

• PRINCE module for on-the-fly flash encryption/decryption

• High-speed and full-speed USB host and device interface with crystal-less operation for full-speed, SDIO/MMC

• Five general-purpose timers, one SCTimer/PWM, one RTC/alarm timer

• One 24-bit Multi-Rate Timer (MRT)

• A Windowed Watchdog Timer (WWDT)

• Nine flexible serial communication peripherals (which can be configured as a USART, SPI, high-speed SPI, I2C, or I2Sinterface)

• Programmable Logic Unit (PLU)

• One 16-bit 1.0 Msamples/sec ADC, comparator, and temperature sensor

The Cortex-M33 offers 18.2 % performance increase in the same process technology compared to the high-embeddedperformance bars established by Cortex-M4 processors, while improving power efficiency. Cortex-M33 official CoreMark is 4.02CoreMark/MHz, Cortex-M4 official CoreMark is 3.40 CoreMark/MHz.

This application note describes how to port CoreMark code to LPC55xx, which involves setting up software and hardware includingmemory partitioning, compiler setting, and board setup. It also describes how to measure CoreMark scores on the Cortex-M33and the result including CoreMark scores and power consumption in μA/MHz. Separate CoreMark projects for different softwaredevelopment tools (Keil MDK, IAR EWARM, and MCUXpresso IDE) are also included herewith for reference.

2 Integration of CoreMark library to SDK2.0 framework

The software package associated with this application note contains SDK2.0 based project framework. It allows developers todrop in the CoreMark library sources and quickly get up and running with benchmarking the LPC55xx. To get started, go to: https://www.eembc.org/coremark, Click the Download link as shown in Fig. 1 and follow the instructions on the page.

Contents

1 Introduction..........................................1

2 Integration of CoreMark library toSDK2.0 framework............................ 1

2.1 Porting CoreMark libraryinto CoreMark framework........ 2

2.2 Optimizing the CoreMarkframework..............................18

3 Measuring CoreMark on board.........253.1 LPC55S69Xpresso board..... 253.2 Board Setup..........................253.3 Run CoreMark code..............28

4 Result..................................................29

5 Conclusion......................................... 32

6 Reference........................................... 32

7 Revision history.................................32

AN12284LPC55xx CoreMark on Cortex-M33 Porting GuideRev. 1 — December 2019 Application Note

https://www.eembc.org/coremark

https://www.eembc.org/coremark

Figure 1. EEMBC CoreMark download link webpage

After reviewing the license terms, go through the readme and documentation file. The readme provides step-by-step instructionson unpacking and building the distribution. It also helps in getting familiar with the CoreMark terminology used throughout theapplication note.

2.1 Porting CoreMark library into CoreMark framework

There are two variants of CoreMark projects for each IDE. One executes the CoreMark application from internal flash and otherexecutes the CoreMark application from internal SRAMX

The CoreMark projects are:

1. run_in_flash_xxmhz – Cortex-M33 executes CoreMark application from internal flash.

2. run_in_ramx_xxmhz – Cortex-M33 executes CoreMark application from internal RAM.

The locations of CoreMark projects are:

Keil MDK IDE :

- lpc5500_coremark_mdk\coremark.uvprojx.eww

IAR Workbench IDE:

- lpc5500_coremark_iar\coremark.eww

Each of executes settings have four frequency settings : 12 MHz, 48 MHz, 96 MHz and 150 MHz.

Depending on the toolchain, the workspace should look as shown in below figures. The CoreMark framework requires the additionof the CoreMark files from EEMBC.

2.1.1 CoreMark framework for Keil MDK / IAR EWARM / MCUXpresso IDE

The run_in_xxxx_xxmhz project must be set as active before the CoreMark files can be added.

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Integration of CoreMark library to SDK2.0 framework

LPC55xx CoreMark on Cortex-M33 Porting Guide, Rev. 1, December 2019Application Note 2 / 33

Figure 2. Keil MDK CoreMark framework

Figure 3. IAR EWARM workspace

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Figure 4. MCUXpresso project configuration select

Copy the following files from the CoreMark package downloaded from EEMBC:

- core_list_join.c

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- core_main.c

- core_matrix.c

- core_state.c

- core_util.c

- coremark.h

Figure 5. CoreMark files to copy

-For Keil MDK place these files in the project directory

lpc5500_coremark_mdk\source

-For IAR Embedded Workbench place these files in the project directory

lpc5500_coremark_iar\source

-For MCUXpresso place these files in the project directory.

lpc5500_coremark_mcux\source

The files ee_printf.c, core_portme.c and core_portme.h(under port_lpc5500 folder)need to be copied to the following folderlocations.

-For Keil IDE place the files in “lpc5500_coremark_mdk\source”

Add the files into the Keil MDK project framework to the respective groups source by double clicking on the groups.

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Figure 6. Adding files in Keil MDK

-For IAR Embedded workbench place the files in “lpc5500_coremark_iar\source”

Add the files into the IAR project framework to the respective groups source by double clicking on the groups.

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-For MCUXpresso place the files in “lpc5500_coremark_mcux\source”

Add the files into the MCUXpresso project framework to the respective groups source by click the “refresh” selection.

Figure 7. Adding files in IAR EWARM workspace

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Figure 8. Adding files in MCUXpresso project

Use the core_portme.c and core_portme.h files provided with the application note and not the one from the EEMBC CoreMarkpackage. For convenience these files have the required porting changes ready for use.

Copy these files to the source folder for all three tool chains and add the core_portme.c file in the project framework under thesource group.

Once all the files have been added, the workspace should look as shown below:

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Figure 9. Keil MDK project workspace after adding CoreMark files

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Figure 10. IAR EWARM workspace after adding CoreMark files

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Figure 11. MCUXpresso project after adding CoreMark files

A few files need to be modified to support CoreMark and are described below. In the project scatter file change the stack size as0x2000.

define symbol __size_cstack__ = 0x2000;

To support ‘printf’ statements to a PC terminal, the ‘core_portme.h’ file needs to be modified. Add the following line of code foree_printf function.

#if HAS_PRINTF#else#ifdef COREMARK_SCORE_TEST#define ee_printf printf#elseextern int ee_printf_template(const char *fmt, ...);#define ee_printf ee_printf_template#endif#endif#endif

In ‘eeprintf.c’ file, add #ifdef COREMARK_SCORE_TEST and the function ee_printf(const char *fmt,…).

#ifndef COREMARK_SCORE_TESTint ee_printf_template(const char *fmt, ...){ return 0;

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}#endif

This is added so that the printf code is optimized when running the μA/MHz test. In ‘core_portme.h’ there is a #defineCOREMARK_SCORE_TEST that dictates whether or not the application is executing the CoreMark score test.

In order to add the path to the header files used in the project, in Keil MDK under Project->Options-> C/C++(AC6) tab, click ‘Includepath’ and add the following paths that contain the header files.

Figure 12. Keil MDK compiler include paths

In IAR under Project->Options-> C/C++ Compiler, click “Preprocessor” and add the following paths that contains the header files.

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Figure 13. IAR EWARM compiler include paths

The CoreMark files have now been successfully ported into the CoreMark project framework

In MCUXpresso under “ Properties for xxxx”->C/C++ Build-> Settings->, click “Includes” and add the following paths that containsthe header files.

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Figure 14. MCUXpresso compiler include paths

The CoreMark files have now been successfully ported into the CoreMark project framework.

2.1.2 CoreMark framework to execute from Internal SRAM

The project run_in_ram_xxmhz executes the CoreMark application from 32 KB SRAMX memory region.

The files core_list_join.c, core_main.c, core_matrix.c, core_state.c and core_util.c are relocated to execute from SRAMX usingthe linker scripts.

For Keil MDK the linker script is located at:

.\lpc5500_coremark_mdk\LPC55S69_cm33_core0_ramx.scf

The linker script setting for run_in_ramx_xxmhz project is shown in Fig 15

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Figure 15. Linker script in Keil IDE

For IAR EWARM IDE to execute CoreMark in Internal SRAM, a line of code needs to be added to the files core_main.c, core_util,c,core_state.c, core_matrix.c and core_list_join.c, as Fig 18 shows, above #include in all five files.

These CoreMark files are labeled as their own IAR EWARM linker “section”. The provided .icf linker file in .\lpc5500_coremark_iar\LPC55S69_cm33_core0_ramx.icf

then places this section, which is called “critical_text” into SRAMX. To do this, add the following line of code in icf file, as shownin Fig 16.

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Figure 16. IAR EWARM allocate Code to SRAM area

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Figure 17. Linker script in IAR EWARM

Figure 18. IAR EWARM #pragma command

For MCUXpresso to execute CoreMark in Internal SRAM, just selected the linker file as “lpc5500_coremark_RUN_IN_SRAMX.ld”in “Managed Linker Script”,as shown in Fig 19..

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Figure 19. MCUXpresso allocate Code to SRAM area

2.2 Optimizing the CoreMark framework

There are many factors that affect the CoreMark and μA/MHz score that can be optimized. Some of these factors are IDEdependent optimizations, while others leverage the MCU architecture for better performance. The goal is to be able to producethe best scores from all three IDEs. It is important to understand that these IDEs are constantly changing and a different versionof a given IDE may add or remove features that may make these optimizations obsolete or ineffective. The following are the IDEversions that are applicable to this application note:

Keil MDK v5.28

IAR EWARM 8.40.2

MCUXpresso 11.0.1_2563

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2.2.1 Memory considerations

Due to the inherent architecture of SRAM and flash, CoreMark executes faster when running out of SRAM. The LPC55xx internalmemory uses a multilayer AHB matrix system that provides a separate instruction and data bus for Cortex-M33 and SRAMX bank.See Fig 20. SRAM0 to SRAM4 are on System bus. Placing the CoreMark code and data in different SRAM, banks minimizes buscontention and improves instruction and data parallelism.

It is important to minimize the flash wait states according to the MCU frequency to optimize the CoreMark score. In contrast, whenperforming the μA/MHz test, it is possible to save power by disabling the prefetch ability of flash. The LPC55xx user manualcontains more information on configuring the flash memory, such as the minimum number of wait states allowed at a given corefrequency.

The provided CoreMark framework projects include separate SRAM and flash based projects that implement various memoryoptimizations.

Figure 20. LPC55Sxx AHB matrix

In both the SRAM and flash projects, there is a COREMARK_SCORE_TEST macro defined in core_portme.h, that indicateswhether the project is configured to execute the CoreMark benchmark or the μA/MHz test. If this macro is defined, the CoreMarkscore test runs. If this macro is commented out, the μA/MHz test runs. Use this macro to switch between the two benchmarks.

2.2.2 IDE Optimization Setting

The following optimizations are compiler based and therefore IDE dependent. These optimizations apply to both the SRAM andflash based projects.

2.2.2.1 Keil optimizations

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There are two compiler optimizations that can be done to improve the CoreMark score. In Project->Options and under the C/C++(AC6) tab, the optimization level needs to be set as “-mcpu=Cortex-m33 --target=arm-arm-none-eabi -Omax -g -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -fno-common -ffp-mode=fast” in Misc Ctonrols.

Figure 21. Keil MDK CoreMark score optimization

When benchmarking the power consumption of the MCU, the optimization setting must be set to Level 0 (-O0) and “Optimizedfor time” must be unchecked.

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Figure 22. Keil MDK μA/MHz optimization

2.2.2.2 IAR Optimization

There are two compiler optimizations that can be done to improve CoreMark score. Set the optimization level to “High”, select“Speed” from the drop down menu and check the “No size constraints” checkbox

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Figure 23. IAR EWARM CoreMark score optimization

When benchmarking the power consumption of the MCU, the optimization level should be set to “None”.

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Figure 24. IAR EWARM μA/MHz optimization

2.2.2.3 MCUXpresso Optimization

There are two compiler optimizations that can be done to improve CoreMark score. Set the optimization level to “-O3” so pleaseselect “Optimize most(-O3)” from the drop down menu.

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Figure 25. MCUXpresso CoreMark score optimization

When benchmarking the power consumption of the MCU, the optimization level should be set to “None(-O0)”

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Figure 26. MCUXpresso μA/MHz optimization

3 Measuring CoreMark on board

3.1 LPC55S69Xpresso boardThe LPC55S69Xpresso board supports a VCOM serial port connection via P6. To observe debug messages from the board setthe terminal program to the appropriate COM port and use the setting ‘115200-8-N-1-none’. To make the debug messages easierto read, the new line receive setting should be set to auto.

3.2 Board SetupThe LPC55S69 Rev A1 development board is used for benchmarking

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Measuring CoreMark on board


Figure 27. LPC55S69Xpresso board

The board ships with CMSIS-DAP debug firmware programmed. Visit the following FAQ for more information on CMSIS_DAPdebug firmware: https://www.nxp.com/downloads/en/software/lpc_driver_setup.exe For debugging and terminal debugmessages, connect a USB cable to P6 USB connector. Board schematics are available on www.nxp.com.

3.2.1 μA/MHz measurement setup

To measure the LPC5500 power consumption, remove R92, install header at P13, and connect ammeter across P13 as shownin Figure 28.

The current data on EVK maybe little higher than datasheet, due to the EVK have more other components may

cost more power.

NOTE

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Figure 28. μA/MHz measurement setup

If we need measurement the MCU core current, we need rework the board by removing the R92. Then we can measure thecurrent through P13 by multimeter.

While performing the μA/MHz benchmark, use P6 USB connector to provide power to the board. After the μA/MHz benchmarkproject has been downloaded, power cycling the board by removing the USB cable, and reinsert to make sure that the debugprobe is not connected.

The baud rate setting for debug messages is 115200. It can be changed in core_potme.c file.

Line209 config.baudRate_Bps = 115200;

Similarly, by selecting different configuration projects in workspace window, the core clock frequency can be changed. Each ofthe configuration may enable below defined project configuration settings:

RUN_IN_12MHZ

RUN_IN_48MHZ

RUN_IN_96MHZ

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RUN_IN_150MHZ

3.3 Run CoreMark code

The first step to get CoreMark result is to connect the connector P6 of the board with PC. Then the PC recognizes the LPC-Link2debugger with a Simulate Serial Port as shown in Fig 29 .

If PC cannot find the serial port driver, download the LPCScrypt from below link, and install on your PC.

https://www.nxp.com/support/developer-resources/software-development-tools/lpc-developer-resources-/lpc-microcontroller-utilities/lpcscrypt-v2.0.0:LPCSCRYPT?tab=Design_Tools_Tab

Figure 29. LPC-LinkII UCom Port

Open a UART debug terminal (like Tera Term, putty, etc.), and configure as 115200, 8 data bits, no parity, 1 stop bit, refer Fig 30.

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Figure 30. UART debug terminal configuration

Once the CoreMark necessary files are added into the project (by following Chapter 2.1 instructions), compile the project anddownload to the LPC5500Xpresso board.

Click reset button, the CoreMark benchmark prints on the terminal after a few seconds, like Fig 31 in Chapter 4.

4 Result

Figure 31 shows the CoreMark benchmark result when running LPC5500 at 96 MHz core frequency in IAR. The CoreMarkbenchmark score is the number of iterations per second. The CoreMark/MHz score executing from internal flash for this run is372.786580/96 MHz = 3.883 CoreMark/MHz .

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Result


Figure 31. CoreMark result

Table 1 shows typical CoreMark score when benchmarked on Keil MDK, IAR EWARM and MCUXpresso IDE when running frominternal flash and SRAM at 96 MHz core frequency.

Table 1. LPC55S69Xpresso board CoreMark/MHz Score

IDE CoreMark/MHz Score(SRAMX) CoreMark/MHz Score(Flash)

KEIL MDK 4.021 2.333

IAR EWARM 3.887 2.435

MCUXpresso 2.843 2.016

Test under 96 MHz

NOTE

For μA/MHz, following tables show typical results when running on the LPCXpresso55S69 board with VDD = 3.3 V at roomtemperature. Fig 24 compares the three IDEs in terms of power consumption.

The current data on EVK maybe little higher than datasheet, due to the EVK have more other components may

cost more power.

NOTE

The average current in 150MHz will higher than other modes, the reason is 150Mhz will enable PLL, the PLL cost

more power.

NOTE

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Result


Table 2. Keil MDK μA/MHz score

Frequency Avg. Power

Consumption (mA,SRAM X)

μA/MHz

Score

(SRAM X)

Avg. Power

Consumption (mA,Flash)

μA/MHz

Score

(Flash)

12 MHz 1.34 111.67 1.35 112.50

48 MHz 2.68 55.84 2.72 56.67

96 MHz 3.89 40.53 3.95 41.14

150 MHz 7.24 48.27 6.30 42.00

Table 3. IAR EWARM μA/MHz score



μA/MHz

Score

(SRAM X)

Avg. Power


μA/MHz

Score

(Flash)

12 MHz 1.48 123.34 1.29 107.50

48 MHz 2.63 54.80 3.32 69.17

96 MHz 3.96 41.25 4.28 44.59

150 MHz 7.63 50.87 7.56 50.40

Table 4. MCUXpresso μA/MHz score



μA/MHz

Score

(SRAM X)

Avg. Power


μA/MHz

Score

(Flash)

12 MHz 1.33 110.84 1.19 115.84

48 MHz 2.40 50.00 2.41 50.03

96 MHz 3.64 37.92 3.58 37.30

150 MHz 7.19 47.94 6.57 43.80

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Result


Figure 32. μA/MHz IDE comparison

5 ConclusionThree types of CoreMark benchmarking on the LPC55xx are presented in this document with different IDEs (Keil, IAR,MCUXpresso):

CoreMark score, power consumption, and μA/MHz.

It also describes how to optimize the benchmark results when running the benchmark out of internal SRAM and flash.

The CoreMark results are measured on LPCXpresso55S69. The best CoreMark number is 4.021, achieved by using KEILMDK(Arm Compiler 6.12) and running CoreMark from SRAM X. The best CoreMark power consumption in μA/MHz is 37.30,achieved by running CoreMark from flash when core frequency is 96 MHz.

6 Reference1. CoreMark Benchmarking for ARM Cortex Processors, ARM

2. AN11811 LPC5411x CoreMark Cortex-M4 Porting Guide,NXP

3. UM11126_LPC55xx/LPC55Sxx User Manual ,NXP

7 Revision history

Revision history

Rev. Date Substantial changes

0 25 January, 2019 Initial reversion

1 December, 2019 Updated CoreMark scores on silicon ‘1B’ with SDK2.6.3 and added 150MHz CoreMark

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Conclusion


http://infocenter.arm.com/help/topic/com.arm.doc.dai0350a/DAI0350A_coremark_benchmarking.pdf

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Date of release: December 2019

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an12284 4 result29 5 conclusion 32 rev. 1 — december 2019 application note 6 ... · 2019. 12....

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