CONCORDIAVLSI DESIGN LAB

SPICE Levels

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular

Level 39 UCB BSIM2 model: (Commercial HSPICE model). Improves modeling of subthreshold conduction.

Level 49 UBC BSIM3 model (Commercial HSPICE level 49) corrects non physical behavior of earlier models

SPICE Parameters (Process)

SPICE Transistor (Parasitic Parameters)

SPICE Transistor Parameters

*Canadian Microelectronic Corporation

CMOSIS5 Design Kit V2.1 for Cadence Analog Artist.MODEL CMOSN mos3 type=n +PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 +VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E –04 +UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976 +NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 +ETA=3.7180E-02 +KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10 +CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11 +MJSW=0.521 PB=0.99 +XW=4.108E-07 +CAPMOD=bsim XQC=0.5 XPART=0.5 *Weff = Wdrawn - Delta_W*The suggested Delta_W is 4.1080E-07

.MODEL CMOSP mos3 type=p+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10MJSW=0.505 PB=0.99+XW=3.622E-07+CAPMOD=bsim XQC=0.5 XPART=0.5*Weff = Wdrawn –Delta_W*The suggested Delta_W is 3.220E-07

Temperature ranges: commercial : 0 to700C industrial: -40 to 850C military: -55 to 1250C

2. Interconnection Capacitance

The following parameters are obtained with 1.0 micron wide active trace with 1.0 micron spacing to both side as illustrated by the following cross section drawing:

top layer =============================== active layer ==== ++++ ==== ++++ - active trace bottom layer ===============================

The total capacitance is calculated as

C_total = C_bot_a + C_top_a + 2 * (C_bot_p + C_bot_p + C_line)

where

C_bot_a is the area capacitance to the bottom layer. C_bot_p is the perimeter capacitance to the bottom layer. C_top_a is the area capacitance to the top layer. C_top_p is the perimeter capacitance to the top layer. C_line is the one-side interline capacitance.

Poly to Substrate Over Field Oxide (No top layer)Area (bottom) 0.1043 +/- 0.0255 fF/um^2Fringing per edge (bottom) 0.0298 +/- 0.0062 fF/umLine per edge 0.0151 +/- 0.0004 fF/um

Poly to Substrate Over Field Oxide (Metal 1 on top)

Area (bottom) 0.1043 +/- 0.0255 fF/um^2

Fringing per edge (bottom) 0.0250 +/- 0.0053 fF/umArea (top) 0.0663 +/- 0.0161 fF/um^2Fringing per edge (top) 0.0177 +/- 0.0040 fF/umLine per edge 0.0050 +/- 0.0008 fF/um

Poly to Substrate Over Field Oxide (Metal 2 on top)Area (bottom) 0.1043 +/- 0.0255 fF/um^2Fringing per edge (bottom) 0.0284 +/- 0.0061 fF/umArea (top) 0.0177 +/- 0.0032 fF/um^2Fringing per edge (top) 0.0062 +/- 0.0012 fF/umLine per edge 0.0128 +/- 0.0002 fF/um

Poly to Substrate Over Field Oxide (Metal 3 on top)Area (bottom) 0.1043 +/- 0.0255 fF/um^2Fringing per edge (bottom) 0.0290 +/- 0.0062 fF/umArea (top) 0.0103 +/- 0.0018 fF/um^2Fringing per edge (top) 0.0037 +/- 0.0007 fF/um Line per edge 0.0153 +/- 0.0003 fF/um

Metal-1 to Substrate/Diffusion (no top layer)Area (bottom) 0.0411 +/- 0.0102 fF/um^2Fringing per edge (bottom) 0.0177 +/- 0.0044 fF/um Line per edge 0.0528 +/- 0.0068 fF/um

Metal-2 to Substrate/Diffusion (no top layer)Area (bottom) 0.0152 +/- 0.0029 fF/um^2Fringing per edge (bottom) 0.0072 +/- 0.0014 fF/umLine per edge 0.0624 +/- 0.0084 fF/um

Metal-2 to Substrate/Diffusion (Metal-3 on top)Area (bottom) 0.0152 +/- 0.0029 fF/um^2Fringing per edge (bottom) 0.0071 +/- 0.0014 fF/umArea (top) 0.0392 +/- 0.0092 fF/um^2Fringing per edge (top) 0.0170 +/- 0.0041 fF/um Line per edge 0.0452 +/- 0.0055 fF/um

Metal-2 to Poly (no top layer)Area (bottom) 0.0177 +/- 0.0032 fF/um^2Fringing per edge (bottom) 0.0083 +/- 0.0016 fF/um Line per edge 0.0612 +/- 0.0084 fF/um Metal-2 to Poly (Metal-3 on top)Area (bottom) 0.0177 +/- 0.0032 fF/um^2Fringing per edge (bottom) 0.0082 +/- 0.0016 fF/umArea (top) 0.0392 +/- 0.0092 fF/um^2Fringing per edge (top) 0.0170 +/- 0.0041 fF/umLine per edge 0.0440 +/- 0.0053 fF/um

Metal-2 to Metal-1 (no top layer)Area (bottom) 0.0444 +/- 0.0115 fF/um^2Fringing per edge (bottom) 0.0189 +/- 0.0049 fF/umLine per edge 0.0527 +/- 0.0069 fF/umFringing per edge (bottom) 0.0187 +/- 0.0050 fF/umArea (top) 0.0392 +/- 0.0092 fF/um^2Fringing per edge (top) 0.0169 +/- 0.0042 fF/umLine per edge 0.0356 +/- 0.0038 fF/um

Metal-2 to Metal-1 (Metal-3 on top)

Area (bottom) 0.0444 +/- 0.0115 fF/um^2Fringing per edge (bottom) 0.0187 +/- 0.0050 fF/umArea (top) 0.0392 +/- 0.0092 fF/um^2Metal-1 to Substrate/Diffusion (Metal-2 on top)Area (bottom) 0.0411 +/- 0.0102 fF/um^2Fringing per edge (bottom) 0.0175 +/- 0.0045 fF/umArea (top) 0.0392 +/- 0.0092 fF/um^2Fringing per edge (top) 0.0168 +/- 0.0041 fF/um Line per edge 0.0360 +/- 0.0040 fF/um

Metal-1 to Substrate/Diffusion (Metal-3 on top)Area (bottom) 0.0411 +/- 0.0102 fF/um^2Fringing per edge (bottom) 0.0176 +/- 0.0044 fF/umArea (top) 0.0149 +/- 0.0028 fF/um^2Fringing per edge (top) 0.0070 +/- 0.0014 fF/um Line per edge 0.0445 +/- 0.0054 fF/um

Metal-1 to Poly (no top layer)Area (bottom) 0.0663 +/- 0.0161 fF/um^2Fringing per edge (bottom) 0.0262 +/- 0.0065 fF/um Line per edge 0.0482 +/- 0.0068 fF/um

Metal-1 to Poly (Metal-2 on top)Area (bottom) 0.0663 +/- 0.0161 fF/um^2Fringing per edge (bottom) 0.0259 +/- 0.0067 fF/umArea (top) 0.0392 +/- 0.0092 fF/um^2Fringing per edge (top) 0.0167 +/- 0.0042 fF/umLine per edge 0.0316 +/- 0.0039 fF/um

Metal-1 to Poly (Metal-3 on top)Area (bottom) 0.0663 +/- 0.0161 fF/um^2Fringing per edge (bottom) 0.0261 +/- 0.0066 fF/umArea (top) 0.0149 +/- 0.0028 fF/um^2Fringing per edge (top) 0.0069 +/- 0.0014 fF/umLine per edge 0.0400 +/- 0.0053 fF/um

Resistor Values

For 0.5u process: Values are per square

N+ diffusion : 70 W / M1: 0.06/ P+ diffusion : 140 W / M2: 0.06/ Polysilicon : 12 W / M3: 0.03/ Polycide:2-3 W / P-well: 2.5K/ N-well: 1K/

Contact resistance: PolyI to MetalI 50 W Via resistance: Metal I to Metal II 1.5 W Via resistance: Metal II to metal III 1.W Contact resistance: PolyI to MetalI 50 W Via resistance: Metal I to Metal II 1.5 W Via resistance: Metal II to metal III 1.W

Silicon Parameters

The Intrinsic Silicon Thermally generated electrons and holes Carrier concentration

pi =ni ni= 3.1X1016 T3/2 e-1.21/2KT cm-3 T= temperature in K K= Boltzmann Constant = 8.63X10-5 eV/K

Silicon: ni=1.45X1010 cm-3 @ room temp GaAs : ni=2X106 cm-3 @ room temp

si =11.7 o

ox =3.97 o

o =8.85 * 10 -14 F/cm

SPICE Transistor Parameters

Parameter

NMOS PMOS Units Source

Description

VTOKPGAMMAPHILAMBDARDRSCBDCBSISPBCGSOCGDOCGBORSHCJMJCJSWMJSWJSTOXNSUBNSSNFSTPGXJLDUOVMAX

0.740E-6

1.10.60.01(40)(40)

0.73.0E-103.0E-105.0E-10

254.4E-10

0.54.0E-10

0.31.0E-55.0E-81.7E16

001

6.0E-73.5E-7

7751.0E5

-0.812E-6

0.60.60.03(100)(100)

0.62.5E-102.5E-105.0E-10

801.5E-4

0.64.0E-10

0.61.0E-55.0E-85.0E15

001

5.0E-72.5E-7

2500.7E5

V(A/V2)(V0.5)

V1/V

ohmsohms

FFAV

F/mF/mF/m

Ohms/sq.

(F/m2)-

F/m-

(A/m2)m

(1/cm3)(1/cm2)(1/cm2)

-mm

(cm2/Vs)m/s

(1)(5)(1)(3)(5)(2)(2)(2)(2)(2)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(3)(3)(3)(1)(1)(1)(1)

-zero bias threshold voltage-transconductance parameter-bulk threshold parameter-surface potential-channel-length modulation-drain ohmic resistance (w=6)-source ohmic resistance()-zero bias B-D juction cap.-zero bias B-S juction cap.-bulk junction sat.current-bulk junction potential;-G-S overlap capacitance-G-D overlap capacitance-G-bulk overlap capacitance-diffusion sheet resistance-zero bias bulk junction cap.-bulk junction grading coef.-bulk junction sidewall cap.-sidewall cap. Grading coef.-bulk jinction sat.current-oxide thickness-substrate doping-surface state density-fast surface state density-type of gate material-metallurgical junction depth-lateral diffusion-surface mobility-maximum drift velocity

SPICE Level 3 Parameters

Parameter NMOS PMOS Units Source Description

THETAKAPPAETA

0.111.00.05

0.131.00.3

1/V--

(1)(1)(1)

-mobility modulation-saturation field factor-static feedback

Page 2 of 4Other Electrical Parameters

Capacitance (pF/m2)

Edge Component (pF/m)

Source

Gate (Cox)Metal1 – FieldMetal1 – PolyMetal1 – DiffusionPoly – FieldMetal2 – FieldMetal2 – DiffusionMetal2 – PolyMetal2 – Metal1Capacitor P + - Poly(0.1%/V linearity)

6.9E-42.7E-55.0E-55.0E-56.0E-51.4E-51.6E-52.0E-52.5E-56.9E-4

0.5E-40.4E-4

0.2E-42.0E-5

0.5E-4

(1)(1)(1)(1)(1)(4)(4)(4)(4)(*)(1)

Resistance (ohms/sq.) Source

N+ DiffusionP+ DiffusionN+ PolyCapacitor P+P-wellMetal1Metal23 3 metal1 – P + Diffusion Contact3 3 metal1 – N + Diffusion Contact3 3 metal1 – N + Poly Contact

2580183004K0.0350.0301214425

(1)(1)(5)(1)(1)(4)(4)(5)(5)(5)

Maximum operating voltage: 5 volts.

Sources: (1) D. Smith of NTE, presented at CMC Workshop June 6-7, 1985. (2) Calculated by SPICE: e.g. –RSH is used to calculate RD & RS. (3) SPICE default. (4) D. Smith of NTE, April 1986. (5) Typical Measured DC result. (*) Estimate – Capacitors assumed to be equal to gate capacitance.

CONCORDIAVLSI DESIGN LAB

Hand Analysis useful parameters

Cox= 3.6 fF/ m2 Capacitance per unit area Vthn= 0.69 Vthp=-0.91 Threshold Voltage n=0.62 p= 0.49 Body effect parameter LDn=0.09 m LDp=0.07 m Lateral Diffusion Wdn=0.41 m Wd=0.36 m Width overlap K’ (Uo * Cox/2) K’n=70.6 A/V2 Transconductance. K’p=-21 A/V2

0.5u CMOS Process:Cox= 3.45 fF/um2

tox Oxide thickness for 0.35 um , tox=100Ao =90 nm.`

Rsh = Sheet resistance For 0.5u process : N+ diffusion : 70 W/ M1: 0.06W/

P+ diffusion : 140 W/ M2: 0.06 W/ Polysilicon : 12 W/ M3: 0.03 W/ Polycide: 2-3 W/ P-well: 2.5KW/

N-well: 1KW/ 0.35u CMOS Process:Cox= 3.65 fF/um2 Rsh values for 0.35u CMOS Process: Polysilicon 10 W/ Polycide 2 W/ Metal1 0.07 W/ Metal II 0.07 W/ Metal III 0.05 W/ Contact resistance: PolyI to MetalI 50 W Via resistance: Metal I to Metal II 1.5 W Via resistance: Metal II to metal III 1.5 W