awr ltcc design flow
DESCRIPTION
microwave simulationTRANSCRIPT
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LTCC Design Flow
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Outline
Current methodologies employed today
Ideal LTCC design methodology
Challenges associated with reaching an ideal design methodology Accurate modeling
Integrated solution
Library availability
Solutions to the current challenges
Steps to reaching an ideal LTCC design methodology
Demonstration of the implementation of the LTCC design methodology
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LTCC Technology
X-ray view from top
Photograph view from top
(no top layer conductor tracks)
Auto Assembly of components
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LTCC Module Applications
RF/ Wireless includes:
WLAN
Bluetooth
Mobile Communications Multi-band radios
Bluetooth Antenna Modules
Front-End Transmitter Modules
Front-End Receiver Module
Power Amplifier Modules
Duplexer Switch Component Markets
Filter Component Markets
Voltage-Controlled Oscillator (VCO)
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LTCC Modules Mobile Radio
RF Front End - A dual Band Mobile radio.
Average parts count for
Dual Band radio
LTCC
LTCC
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LTCC Modules Mobile Radio
Next generation
Lower parts count and more
advanced radio .. Tri Band! LTCC
LTCC
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Typical Design
Methodology Today
Initial simulation
in HF design tool
Layout in a
layout package EM simulation
Final Layout
Ok?
2-10 Iterations
Design Rule
Check
Fab Verification Test
GDSII Stream
Output
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Challenges with the
current Methodology
Serial process, no interactivity to quickly change and verify, inaccurate modeling
Several disconnected tools in use Simulation tools: ADS, MWO, etc
Layout: PADS, Protel, Mentor, etc
EM Simulation: HFSS, Sonnet, Emsight, etc
DRC: Calibre, Dracula, etc
Multiple cycles are required through multiple tools
Cycle times are long and numerous as a result
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LTCC Ideal Methodology
Outlined below is the generic LTCC design methodology
Thus far, most designers have not been able to realize a fully integrated process
Process
Characterization
Library
Implementation
Process
Verification
Interactive
Layout/Simulation
with Inets and ACE
Simulation
Schematic
Design
Ok? Ok?
EM Analysis
Critical Areas
Design Rule
Check Fab Verification Test
yes
no
yes
no
GDSII Stream
Output
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LTCC Modules
Outlined in the previous slide is a generic Ideal Flow
The details of the flow will vary dependent on the types of LTCC circuits being designed.
LTCC Diplexer/Filter modules
Embedded Passives
Compact size is important
Understanding the coupling between passives is important
Extensive use of EM simulation
LTCC FEM
Some embedded passives
Chips are both passive and active.
Many via interconnects
Coupling issues between interconnects and not so much the embedded passives.
Probably the most complex module, because of multiple technologies used.
LTCC Pa amp modules
LTCC is used as module package for PA chip.
Most of the passives are SMD parts.
Interconnects for SMD parts in 3d using vias.
Coupling issues only between vias and interconnect lines.
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LTCC Modules
LTCC Diplexer/Filter modules
Embedded Passives
Compact size is important
Understanding the coupling between passives is important
Extensive use of EM simulation
Mixed HighK all embedded Passives Lowk LTCC SMD and embedded Sprials
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LTCC Modules
LTCC FEM
Some embedded passives
Chips are both passive and active.
Many via interconnects
Coupling issues between interconnects and not so much the embedded passives.
Probably the most complex module, because of multiple technologies used.
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LTCC Modules
LTCC PA amp modules
LTCC is used as module package for PA chip.
Most of the passives are SMD parts.
Interconnects for SMD parts in 3d using vias.
Coupling issues only between vias and interconnect lines.
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ACETM : What is it?
Traditional High Frequency Circuit Design
All transmission lines and coupled transmission lines are modeled by a schematic element.
Creating the schematics can be cumbersome and time consuming.
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GM6CLINID=TL1W1=20 umW2=20 umW3=20 umW4=20 umW5=20 umW6=20 umOffs1=40 umOffs2=40 umOffs3=40 umOffs4=40 umOffs5=40 umOffs6=40 umCL1=1CL2=1CL3=1CL4=1CL5=1CL6=1L=40 umAcc=1
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GM5CLINID=TL2W1=20 umW2=20 umW3=20 umW4=20 umW5=20 umOffs1=40 umOffs2=40 umOffs3=40 umOffs4=40 umOffs5=40 umCL1=1CL2=1CL3=1CL4=1CL5=1L=40 umAcc=1
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GM4CLINID=TL3W1=20 umW2=20 umW3=20 umW4=20 umOffs1=40 umOffs2=40 umOffs3=40 umOffs4=40 umCL1=1CL2=1CL3=1CL4=1L=40 umAcc=1
VIAID=V1D=20 umH=100 umT=2 umRHO=1
VIAID=V2D=20 umH=100 umT=2 umRHO=1
VIAID=V3D=20 umH=100 umT=2 umRHO=1
VIAID=V4D=20 umH=100 umT=2 umRHO=1
VIAID=V5D=20 umH=100 umT=2 umRHO=1
VIAID=V6D=20 umH=100 umT=2 umRHO=1
VIAID=V7D=20 umH=100 umT=2 umRHO=1
VIAID=V8D=20 umH=100 umT=2 umRHO=1
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10GM5CLINID=TL4W1=20 umW2=20 umW3=20 umW4=20 umW5=20 umOffs1=40 umOffs2=40 umOffs3=40 umOffs4=40 umOffs5=40 umCL1=1CL2=1CL3=1CL4=1CL5=1L=40 umAcc=1
MLINID=TL5W=20 umL=40 um
MLINID=TL6W=20 umL=40 um
MBEND90X$ID=MS1M=0
MBEND90X$ID=MS2M=0
MBEND90X$ID=MS3M=0
MBEND90X$ID=MS4M=0
MLINID=TL7W=20 umL=40 um
MLINID=TL8W=20 umL=40 um
?
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ACETM : What is it?
Current Trends in High Frequency Design
Because of the complexity of these types of designs, and the push to create smaller circuits, Designers are
beginning to forego this part of the design process and
go straight to EM analysis.
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ACETM : What is it?
ACE is AWRs response to overuse of EM simulation in the design process.
ACE software reclaims parametric design for the user by creating netlist-based representations of complex interconnects
using the very same networks of parametric models designers
themselves would use if they had the time and patience to do so,
in a fraction of the time that it would take EM tools to create
equivalent S-parameters.
The speed, accuracy, and parametric nature of ACE software enable engineers to return to real design by exploring design
alternatives and changes in seconds.
Obviously, EM verification is still a necessary part of the flow, but the ACE tool enables engineers to design once again rather than analyze, even on many of the most challenging RF and MW
designs.
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ACETM : How is it done?
ACE software is based on the proven digital and analog-mixed signal (AMS) technique of
circuit extraction from physical layout where the
equivalent model is a RLCK circuit as shown
below.
CAPID=RL1C=0 F
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
CAPID=RL1C=0 F
CAPID=RL1C=0 F CAP
ID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
K
K
K
K
K
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
SRL
ID=R
L1
R=1
Ohm
L=1e
-9 H
CAPID=RL1C=0 F
CAPID=RL1C=0 F CAP
ID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
KK
KK
KK
KK
KK
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
CAPID=RL1C=0 F
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ACE: How is it done?
ACE uses the same methodology but substitutes the RLCK models with Microwave Models.
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RESID=R1R=1 Ohm
RESID=R2R=1 Ohm
RESID=R3R=1 Ohm
RESID=R4R=1 Ohm
RESID=R5R=1 Ohm
RESID=R6R=1 Ohm
RESID=R7R=1 Ohm
RESID=R8R=1 Ohm
RESID=R9R=1 Ohm
RESID=R10R=1 Ohm
RESID=R11R=1 Ohm
RESID=R12R=1 Ohm
MTRACE2ID=X1W=200 umL=2.064e4 umBType=1M=1
MTRACE2ID=X2W=200 umL=1.439e4 umBType=1M=1
EXTRACTID=EX1EM_Doc="EM Mercury"Name="Mercury"Simulator={Choose}X_Cell_Size=1 umY_Cell_Size=1 umPortType=DefaultSTACKUP="STACK3"Create_Enclosure=YesCreate_Shapes=YesExtension=600 um
PORTP=1Z=50 Ohm
PORTP=2Z=50 Ohm
PORTP=3Z=50 Ohm
PORTP=4Z=50 Ohm
PORTP=5Z=50 Ohm
PORTP=6Z=50 Ohm
PORTP=7Z=50 Ohm
PORTP=8Z=50 Ohm
PORTP=9Z=50 Ohm
PORTP=10Z=50 Ohm
PORTP=11Z=50 Ohm
PORTP=12Z=50 Ohm
PORTP=13Z=50 Ohm
PORTP=14Z=50 Ohm
PORTP=15Z=50 Ohm
PORTP=16Z=50 Ohm
ACETM: How is it done?
Uses AWR microwave models including em based models
Driven by AWR iNets
& EXTRACT flow
Reuse structures with any EM Socket solver
100x-1000x faster than EM
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ACETM: Models
Circuit models from geometric features GMCnlin EM solver built into model MLIN closed-form distributed model MTEEX X model MCROSSX X model MBENDX X model Vias sparameter via library, VIA model, or equivalent circuit
Goes from Geometry to netlist of EM-based models
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ACETM: LTCC
LTCC Diplexer and MCM modules
Embedded passive likes spirals can be modeled with ACE and Inets
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ACETM: LTCC
LTCC Diplexer and MCM modules All interconnects between layer are automatically drawn using Inets.
Simulation times are drastically reduced.
This is probably the most complex use of the ACE technology.
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On to the actual design
The initial design is done in schematic form using the library elements and ACE
Simulation and optimization is performed to meet required performance specifications
Simulation
Schematic
Design
Ok? yes
no
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Simulation Options include:
Time Domain HSPICE
Frequency Domain Harmonic Balance:
Linear
Electromagnetic 3D Planar EM
Full 3D EM
Simulation
Schematic
Design
Ok? yes
no
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Generating the LTCC layout
Ideally the LTCC layout is interactively generated with simulation of verified library models and Inets and ACE.
This provides a quick interactive design process that provides correct by construction LTCC designs
Interactive
Layout/Simulation
with parasitics
Ok? yes
no
Simulation
Schematic
Design
Ok? yes
no
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Looking at interactions
Once the initial layout is complete, each individual model in the library only represents the performance of that element in isolation
Therefore, critical areas of the design now go through an EM simulation to see the effect of element interactions
Different EM simulators are used depending upon the specific problem (MOM,FDTD, FEM, etc)
Adjustments are then made to the layout to compensate for component interactions
Interactive
Layout/Simulation
with parasitics Ok?
Critical Area
EM Analysis
yes
no
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LTCC Module Example
Build PDK
Element Models
Layer stacks
3D viewers
Inets with LPF
Circuit Design with PDK
Parasitics
Interconnection modelling use Ace and Inets
EM verification using em socket
Coupling
Leakage
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LTCC PDK
Vertical Capacitors
Element model
3D view for visualisation
Layer Stack for process
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LTCC PDK
Vertical Inductors
Element model
3D view for visualisation
Layer Stack for process
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LTCC Module Design
Start with an Ideal design.
CAPID=C1C=C1 pF
CAPID=C2C=C2 pF
INDID=L1L=L1 nH
CAPID=C3C=C3 pF
INDID=L2L=L2 nH
CAPID=C4C=C2 pF
INDID=L3L=L1 nH
CAPID=C5C=C1 pF
PORTP=1Z=50 Ohm
PORTP=2Z=50 Ohm
C1=0.8224C2=3.987L1=0.856L2=6.939C3=1.055
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LTCC Design Flow
Replace Ideal components with PDK components.
Layout view
EM view
VSPIRALNID=MI1N=2W=3 milL=17 milLN=15 milSTART_LYR=1VIA_DIA=6 milACC=1PORT
P=1Z=50 Ohm
PORTP=2Z=50 Ohm
CAPID=C1C=0.111 pF
CAPID=C2C=0.164 pF
INDID=L1L=6.45 nH
PORTP=1Z=50 Ohm
PORTP=2Z=50 Ohm
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EM Extracted Modeling
EM simulations automatically generated from Layout EM simulations can be enabled/disabled from the schematic/layout
Allows maximum flexibility in simulation of complete cicuit User can EM only the critical elements to save time Using the Circuit simulator to control EM simulations allows efficient
design
EM Extract creates parameterized EM Sim
Parameter Change auto update
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LTCC Design Flow
Replace all ideal elements with equivalent PDK elements
Inets and ACE connect components
Inets automatically connect components
with correct vias
Extract using
both EM
and ACE
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LTCC Design Flow
The EM Solver is used to guide the corrections to the circuit elements Perturbation/Optimisation techniques Space mapping/Optimisation techniques
1 2 3 4
Frequency (GHz)
Filter start values S21
-100
-80
-60
-40
-20
0
DB(|S(2,1)|)EM Block Filter with tuning
DB(|S(2,1)|)Ideal Filter
DB(|S(2,1)|)Filter with initial values
Parasitics, coupling, poor
initial element values and
interconnect effects
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EM Verification of Complete Circuit
Fine tuning may be needed at this point, but if the previous steps were done correctly it is minimal.
EM Analysis Verification
no OK? yes Fine Tune
Critical
Elements
0.1 1.1 2.1 3.1 4
Frequency (GHz)
Diplexer Ideal vs Final EM
-80
-60
-40
-20
0DB(|S(2,1)|)Diplexer_EM
DB(|S(3,1)|)Diplexer_EM
DB(|S(3,1)|)Diplexer
DB(|S(1,1)|)Diplexer
DB(|S(2,1)|)Diplexer
DB(|S(1,1)|)Diplexer_EM
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V10 Design Flow, Shape Modifiers and Data
Sets.
This design flow uses Em Based modeling in the form of save data sets. Interconnects, Sprial inductors, and Capacitors are
simulated initially using Axiem then used as a model for tuning.
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V10 Design Flow, Shape Modifiers and Data
Sets.
Shape Modifiers are used to parameterize em simulation.
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V10 Design Flow, Shape Modifiers and Data
Sets.
Swept Variables setup the parameterized model that is then used as a subcircuit in a schematic.
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V10 Design Flow, Shape Modifiers and Data
Sets.
Tuning is used to match the ideal simulation. Tune with em based modeling!!
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V10 Design Flow, Shape Modifiers and Data
Sets.
Each component is integrated then fine tuned to account for coupling issues between components. Shape modifiers, and
swept variables are used for fine tuning. Two different subckts
used to design the GSM band and DCS band.
DCS Circuit GSM Circuit
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V10 Design Flow, Shape Modifiers and Data
Sets.
Each Sub circuit now is tuned to match Ideal Performance. Fine tuning is needed as coupling between components
must be tuned out. Shape modifiers allows adjusting the
em simulation while considering as much coupling as
needed.
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V10 Design Flow, Shape Modifiers and Data
Sets.
Finally, the complete diplexer is simulated together
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V10 Design Flow, Shape Modifiers and Data
Sets.
Final verification is done by doing an em analysis of the complete diplexer combining DCS and GSM Sub Circuits. There
is a problem found in the final simulation, one of the notches in
the diplexer has changed.
Coupling effects change the notch in simulation
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V10 Design Flow, Shape Modifiers and Data
Sets.
Via wall used to isolate sub circuits and fix problem with coupling.
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V10 Design Flow, Shape Modifiers and Data
Sets.
Via wall has fixed the notch problem. Fine em tuning is then done to complete the design.
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V10 Design Flow, Shape Modifiers and Data
Sets.
Final Design including attachment to FR4 PCB, and thick metal.
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Motorola LTCC Filter
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Motorola LTCC Quad Band Receiver
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AWR LTCC
MLSCID=TL1W=30 milL=0 mil
MLSCID=TL2W=30 milL=0 mil
SSUBEr=5.7B=29.6 milT=0.0393701 milRho=1Tand=0Name=SSUB1
MSUBEr=5.7H=14.8 milT=0.1 milRho=1.2Tand=.0007ErNom=5.7Name=SUB1
MTRACEID=X1W=15 milL=30.83 milBType=3M=0
MTRACEID=X2W=15 milL=31.67 milBType=3M=0
MSTEP$ID=TL3
MTRACEID=X3W=24 milL=141 milBType=3M=0
MSTEP$ID=TL4
MTRACEID=X4W=24 milL=102.6 milBType=3M=0
MTRACEID=X5W=24 milL=39.08 milBType=3M=0
MSTEP$ID=TL5
MTRACEID=X6W=15 milL=175 milBType=3M=0
MTRACEID=X7W=24 milL=267.1 milBType=3M=0
MTRACEID=X8W=15 milL=30.83 milBType=3M=0
MTRACEID=X9W=15 milL=96.17 milBType=3M=0
MSTEP$ID=TL6
1
2
3MTEE$ID=TL7
MTRACEID=X10W=24 milL=12.34 milBType=3M=0
MTRACEID=X11W=15 milL=15.63 milBType=3M=0
CHIPCAPID=C1C=1000 pFQ=779FQ=0.03 GHzFR=0.23 GHzALPH=-1
MSTEP$ID=TL8
MTRACEID=X12W=120 milL=25 milBType=2M=0
MTRACEID=X13W=120 milL=25 milBType=2M=0
MLSCID=TL9W=30 milL=0 mil
RESID=R1R=82.5 Ohm
MLSCID=TL10W=30 milL=0 mil
MLINID=TL11W=24 milL=0 mil
MTAPERID=MT1W1=W@1 milW2=5 milL=70 mil
MTAPERID=MT2W1=W@1 milW2=5 milL=50 mil
MTRACEID=X14W=24 milL=229.3 milBType=3M=0
12
SUBCKTID=S2NET="Layout of Lo Buffer amp"
1
2
SUBCKTID=S1NET="LNA900 IC"
1
2
3
4
5
SUBCKTID=S3NET="Mixer Section"
1
2
SUBCKTID=S4NET="Filter1"
PORTP=2Z=50 Ohm
PORT1P=1Z=50 OhmPwr=-30 dBm
PORTFNSP=3Z=50 OhmFreq=0.998 GHzPStart=-15 dBmPStop=5 dBmPStep=5 dBTone=2