bandwidth enhacement by inductor + current feedback

8/13/2019 Bandwidth Enhacement by Inductor + Current Feedback

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26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 53, NO. 1, JANUARY 2006

Low-Voltage CMOS Current-Mode Preamplifier:Analysis and Design

Fei Yuan, Senior Member, IEEE

AbstractThis paper presents the analysis and design of anew low-voltage fully balanced differential CMOS current-modepreamplifier for multi-Gbps series data communications. The min-imum supply voltage of the proposed preamplifier is

.The preamplifier employs a balanced configuration to achievelarge bandwidth and to minimize the effect of bias-dependent mis-matches. Two new bandwidth enhancement techniques, namelyinductive series peaking and current feedback that are specific tolow-voltage CMOS current-mode circuits, are introduced. Theinductive series peaking technique utilizes the resonant character-istics of networks to achieve both a flat frequency responseand maximum bandwidth. Current feedback extends bandwidth,lowers input impedance, and improves dynamic range. The em-

ployment of both techniques further increases the bandwidth,reduces the value of the series peaking inductor, and improvesnoise performance of the pre-amplifier at high frequencies. Thepreamplifier has been designed using a 0.18- m 6-metal 1-poly1.8-V CMOS technology. Simulation results from Spectre withBSIM3.3 device models that account for device parasitics demon-strate that the preamplifier has a flat frequency response with 25.3dB dc current gain or equivalently 60 dB transimpedance gainwith a 50- load and bandwidth of 2.15 GHz.

Index TermsCMOS current-mode circuits, current feedback,inductive series peaking, preamplifiers.

I. INTRODUCTION

CMOS current-mode circuits have found increasing ap-plications in multi-Gbps data communication systems,

such as optical communications, low-voltage differential sig-

naling (LVDS) based point-to-point data links, and high-speed

bus systems, to name a few. The most challenging block to

design in these systems is the front-end, also known as the

preamplifier, arising from the stringent requirement on both

the noise and bandwidth. Preamplifiers are often designed

using a trans-impedance configuration to take its advantages

of relatively low noise and large bandwidth [1]. In this config-

uration, a high current gain is achieved from an intermediate

voltage amplification stage [2], [3]. Due to the existence of

high-impedance nodes, the drawbacks of voltage-mode cir-cuits, such as limited bandwidth and the need for a high supply

voltage, can not be avoided. In addition, this configuration

requires a current-to-voltage conversion stage, usually a pas-

sive resistor, which deteriorates the noise performance. It is

advantageous to amplify the current directly [4]. It is well

known that CMOS current-mode circuits have many intrinsic

Manuscript received July 28, 2004; revised March 9, 2005. This paper wasrecommended by Associate Editor I. M. Filanovsky.

The author is with the Department of Electrical and Computer Engineering,Ryerson University, Toronto, ON M5B 2K3, Canada (e-mail: [email protected]).

Digital Object Identifier 10.1109/TCSI.2005.854414

Fig. 1. Scaling of supply and threshold voltages.

advantages over voltage-mode counterparts including low

supply voltage requirement, wide bandwidth, tunable input

impedances, high slew rates, and less susceptible to power and

ground fluctuations [5], [6]. These unique characteristics make

current-mode circuits particularly attractive for multi-Gbps

data communications [7], [8]. Two critical challenges exist indesign of high-speed CMOS preamplifiers: (i) performance

degradation caused by the aggressive reduction of the supply

voltage of modern CMOS technologies and (ii) bandwidth and

slew rate requirements to support multi-Gbps data rates [9].

Thereduction in thesupply voltage of moderndigitally CMOS

technologies originated by the aggressive downscaling of MOS

devices has many prominent effects on the characteristics of

monolithic CMOS circuits including high packing density, small

device parasitics, highdevice speed, and lowpower consumption

[10]. Unlike the supply voltage, the threshold voltage of MOS

devices, however, is reduced at a rather slower pace, as shown

in Fig. 1, mainly constrained by subthreshold conduction. Asa result, reduced dynamic range, small effective gate-source

voltage , and low device output impedance [11] crit-

ically affect the performance of CMOS current-mode circuits,

particularly those that employ cascodes [5], [12].

In addition to supply voltage reduction, in design of multi-

Gbps preamplifiers, the large capacitance of the media through

which data are transmitted, such as the junction capacitance

of photo diodes in an optical communication system and the

parasitic capacitance of coaxial cables in a serial link, is often

encountered at the input of preamplifiers. The bandwidth of

preamplifiers is often set by the cutoff frequency of the net-

work formed by this capacitance and the input impedance of

1057-7122/$20.00 2006 IEEE


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YUAN: LOW-VOLTAGE CMOS CURRENT-MODE PREAMPLIFIER 27

Fig. 2. Current amplifier with inductive series peaking and its response. Circuit parameters: m, m, m, mA,

.

the preamplifiers [13]. A low input impedance is achieved tra-ditionally by increasing the width of the input transistor and its

dc biasing current, however, at the expense of chip area, power

consumption, and bandwidth. Several circuit techniques that are

based on active feedback at the input have been proposed re-

cently to reduce the input impedance of current-mode circuits

[14][16]. As demonstrated quantitatively in [17] that the effec-

tiveness of these techniques vanishes at high frequencies. The

technique introduced in [18] improves bandwidth by canceling

out the dominant pole with a compensating zero introduced by

the resistor inserted between the gates of the input and output

transistors. The added resistor, however, affects the noise per-

formance. Also, bandwidth enhancement is much smaller if the

current gain is large. CMOS preamplifiers that have large band-

width, sufficient gain, are able to operate at a low supply voltage,

and suppress power and ground noise are critically needed for

low-cost multi-Gbps data links.

In this paper, we present the analysis and design of a new

low-voltage fully balanced differential CMOS current-mode

preamplifier. The proposed preamplifier employs a balanced

two-stage configuration to suppress mismatches-induced output

offset current. In addition, we propose a new inductive series

peaking technique to increase the bandwidth of current-mode

circuits without affecting their DC characteristics. To further

increase the bandwidth, a new current feedback mechanism is

introduced. We show that this technique not only increases thebandwidth but also reduces the value of the peaking inductor.

We further show that inductive series peaking improves the

noise performance of the preamplifier at high frequencies.

The paper is organized as follows: Section II introduces an

inductive series peaking technique specific to current-mode

circuits and its effect on the bandwidth of CMOS current am-

plifiers. Section III introduces a new current-current feedback

technique for CMOS current-mode circuits and its effect on

the input impedance and bandwidth. In Section IV, the joint

effect of the inductive series peaking and current feedback is

examined. Section V investigates the input impedance of the

preamplifiers. In Section VI, the noise behavior of preamplifiersis examined. The dynamic range of the proposed preamplifiers

is investigated in Section VII. Section VIII presents a numericalstudy of the average slew rate of the preamplifiers. Low power

design issues of current-mode circuits are addressed in Sec-

tion IX. In Section X, the effect of mismatches is investigated

in detail, and a fully balanced configuration that minimizes

the bias-dependent offset output current is proposed. In Sec-

tion XI, the design of a low-voltage fully balanced differential

CMOS current-mode preamplifier with both inductive series

peaking and current feedback is presented. The layout of the

preamplifier and simulation results from SPICE are presented.

Concluding remarks are given in Section XII.

II. INDUCTIVESERIESPEAKING

When the channel length modulation and the high-order ef-

fects of MOS transistors are neglected, the basic current am-

plifier shown in Fig. 2 with has a dc current gain

and bandwidth

(1)

where and are the transconductance and gate-source

capacitance of transistor , respectively, ,

, and zero load impedance were assumed to sim-

plify analysis. The current gain and the bandwidth

are conflicting design parameters. To increase the bandwidth

without sacrificing the current gain, we notice that inductive

shunt peaking that employs a compensating inductor in parallel

with the dominant capacitor is effective in boosting the band-

width of voltage-mode circuits [19]. This technique, however,

is not particularly applicable to current-mode circuits due to

the existence of a biasing current source between the ac ground

and the dominant pole of the circuits. Because the dominant

pole of the current-mirror amplifier is at the gate of the input

and output transistors, a compensation inductor can be placed

in series with , as shown in Fig. 2. With the assumption

, the transfer function of the amplifier is given by

(2)


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Fig. 3. Left layout of square-shaped spiral inductors in a 6-metal CMOS technology. Right lumped circuit model of planar spiral inductors.

with the poles at

(3)

We examine the preceding results in detail prior to further de-

velopment:

1) The amplifier has two identical real poles if

, a pair of complex conjugate poles if

, and two distinct real poles if

. In the critically damped case where

(4)

the amplifierhasa flat frequency response with no ringing

in its step-input response. Its bandwidth is given by

(5)

If the inductance is further increased, a pair of complex

conjugate poles exist. When , a

maximallyflat frequency response known as Butterworth

response is achieved with bandwidth given by [21]

(6)

Note that in this case small ringing exists in the response

of the amplifier to a step input.

2) The added inductor does not affect the dc characteristicsof the amplifier. This is important because it not only en-

sures that the gain of the amplifier will remain unchanged,

the mismatch compensation circuitry to be introduced

shortly will also not be affected.

3) The inductor is sized based on the criterion that a max-

imum flat response and the maximum bandwidth are

achieved simultaneously. To illustrate this numerically,

the current amplifier is analyzed using Spectre with

BSIM3.3 device models that account for device para-

sitics. The response is plotted in Fig. 2 with inductor

value varied from 0 to 20 nH.

4) On-chip inductors are usually implemented in a planar

spiral configuration, as shown in Fig. 3 [20], [19], [22].Multi-layer inductors have also been proposed recently

[23]. Planar spiral inductors have the following character-

istics: (i) low quality factor arising from the ohmic loss

at high frequencies; (ii) low inductance due to the loss

of the magnetic energy caused by the planar structure;

(iii) large parasitic capacitances to the substrate; and (iv)

extremely area-greedy. Inductors larger than 100 nH is

rarely used in practice [20]. The main design parameters

of planar inductors are , , , , and the number of

turns whose definition is given in Fig. 3. Typically

is required to improve the inter-winding magnetic cou-

pling and to reduce the chip area. Also, is often kept

large to minimize the series resistance. The inductance

is calculated using the well-known Greenhouse method

[24]. A typical lumped equivalent circuit of planar spiral

inductors is shown in Fig. 3, where is the series re-

sistance, mainly governed by the loss of the skin effectof the inductor layer, is the inductance, is the

overlap capacitance between the spiral and the center-tap

under-passes. The effect of the inter-turn fringing capaci-

tance is usually small due to the nearly identical potential

of adjacent turns, is the spiral-substrate capacitance.

To minimize both the series resistance and parasitic ca-

pacitances of the inductors, the top metal layer should be

used. Also, no devices should be placed in the area di-

rectly underneath the inductor. Several ground shielding

techniques have been proposed most recently to reduce

this interaction, among which patterned ground shielding

is proven to be the most effective [22].

5) The series resistance of the inductor does not affect

the bandwidth of the circuit severely. As demonstrated in

[18], when properly valued, this resistor helps increase

the bandwidth of the amplifier. For a 10-turn planar

inductor implemented using m6 of a typical 0.18- m

6-metal 1-poly CMOS technologies, the series resistance

is usually less than 10 . Fig. 4 shows that the series re-

sistance of the peaking inductor increases the bandwidth

marginally in this case.

6) The spiral-substrate capacitance of the inductor is in

parallel with , and lowers the bandwidth of the am-

plifier, as shown in Fig. 4. Its negative effect can be com-

pensated by the resonant characteristic of the networkformed by , , and .


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Fig. 4. Left The effect of the series resistance of the peaking inductor on the bandwidth of the ampli fier ( nH, , and is varied from0 to 10

with step 2

); Rightthe effect of underpass capacitance and inductor-substrate capacitance of the inductor on the bandwidth of the amplifier( nH, , , and is varied from 0 to 100 fF with step 25 fF).

III. CURRENTFEEDBACK

It was shown in the preceding section that inductive series

peaking increases the bandwidth by times. The bandwidth

enhancement obtained from the inductive series peaking is often

insufficient to support multi-Gbps data rates. To increase the

bandwidth without employing inductors. We notice that current-

current feedback is capable of lowering the input impedance and

boosting the bandwidth [25], [27]. This mechanism, however,

usually requires the insertion of a current-sensing element,

usually a resistor, in the output current loop. The large voltage

drop across the current-sensing resistor arising from the largedc current of the output branch, however, reduces the dynamic

range of the amplifier. To sense the output current without

affecting both the dc biasing condition, we introduce a new

current feedback mechanism shown in Fig. 5. It is worth noting

that a similar approach was used in design of current-mode

integrators [28]. Neglecting parasitic capacitances, the transfer

function is given by

(7)

where and is the gate-source ca-

pacitance of . The bandwidth is given by

(8)

where was assumed. It is seen that as com-

pared with the basic amplifier, the bandwidth is increased by

the factor . The proposed current feedback has the fol-

lowing characteristics.

1) Since there are only two transistors stacked between the

power and ground rails in the feedback network and its

configuration is identical to that of the output branch, no

increase in the supply voltage is needed.

2) No high-impedance node exists in the circuit. This guar-

anteesa small time constant at every node of the amplifier.This is a typical characteristic of current-mode circuits.

Fig. 5. Current amplifier with current feedback.

3) The feedback factor can be adjusted independent of the

forward-path gain . This is critical because the band-width and the current gain of the amplifier can be con-

trolled by adjusting without affecting the dc character-

istics of the amplifier.

4) The feedback does not increase the output impedance of

the preamplifier. This is a drawback of this configura-

tion. A large output impedance is desirable because it

is equally important as a low input impedance in mini-

mizing the loading effect of current-mode circuits.

5) The feedback reduces the current gain by the same factor

. To have a sufficiently large current gain, feed-

back must not be too strong. Clearly, a compromise be-

tween the bandwidth and gain is to be made.

IV. INDUCTIVESERIESPEAKINGWITHCURRENTFEEDBACK

It is evident from the preceding analysis that the bandwidth

enhancement mechanisms of inductive series peaking and the

current feedback differ fundamentally. This suggests that both

techniques can be employed simultaneously to further improve

bandwidth. Consider the current amplifier of Fig. 6 where both

techniques are employed. The transfer function of the amplifier

is given by

(9)


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Fig. 6. Left Current amplifier with current feedback and inductive series peaking; Right frequency response of current amplifier. Circuit parameters: m, m, m, mA, . Top-left: , m; Top-right: nH, m; Bottom-left: , m, Bottom-right : nH, m.

with poles at

(10)

In the critically damped case where

(11)

we have the bandwidth

(12)

In the case of a maximallyflat response where

(13)

the bandwidth becomes

(14)

Observed is that the bandwidth in this case is times

that of the amplifier with inductor-peaking only, times that of

the amplifier with current feedback only, and times

that of the basic current amplifier. Also seen is that the value of

the series peaking inductor is reduced from

without feedback to with feedback.

Thereduction of theinductanceusingcurrent feedbackis very at-

tractive because a smaller inductor, subsequently, a smaller chip

area anda less parasiticeffect,is neededto achievethe same band-

width. To demonstrate this, the current amplifier is implemented

in a 0.18 m CMOS technology and analyzedusing Spectre with

BSIM3.3 device models. Fig. 6 shows the frequency response of

the amplifier. The bandwidth enhancement from both inductiveseries peaking and feedback is evident.

V. INPUTIMPEDANCE

As aforementioned that a low input impedance not only

reduces the loading effect, subsequently improves the accuracy

of current-mode circuits, it also plays a critical role in boosting

the bandwidth of the amplifiers. In this section, we examine

the input impedance of the proposed amplifiers. Assuming

, and neglecting , , and thesecond-order effects, one can derive the input impedance of

the amplifiers and the results are tabulated in Table I. It is seen

that the input impedance of amplifiers without inductive series

peaking has a low-pass characteristic. Current feedback reduces

the input impedance. Also seen is that the input impedance

of the amplifiers with inductive series peaking exhibits a

band-reject characteristic with the rejection frequency at the

self-resonant frequency of the amplifier

(15)

Current feedback increases the frequency of the minimal input

impedance, resulted from the reduced effective inductance. Theeffectof the peaking inductorvanishes when . Fig. 7 plots

the simulated input impedance of the amplifiers. The peaking of

the input impedance at frequencies beyond is due to the par-

asitic capacitances that were not accounted for in the preceding

derivation.

VI. NOISE

The noise of preamplifiers directly affects the overall noise

performance of receivers. In Appendix A, the power of the

input-referred noise voltage generator and that of the noise

current generators of the proposed preamplifiers are derived

and are tabulated in Table II. It is seen that the thermal noise ofthe gate series resistance and that from the channel contribute


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TABLE IINPUTIMPEDANCE OFCURRENT-MODEAMPLIFIERS

Fig. 7. Input impedance. Top-right: amplifier with current feedback;bottom-left: amplifier with inductive series peaking; bottom-right: amplifierwith both current feedback and inductive series peaking. The same device sizesas those in Fig. 6 are used.

equally to and . The amplifiers with current feedback

exhibit a higher level of noise due to: (i) reduced current gain

and (ii) additional noise from the feedback network. Inductive

series peaking does not increase the noise. It, in fact, improves

the noise performance of the amplifiers, especially when fre-

quency approaches the self-resonant frequency .

The noisefigure ( ) of the amplifiers is obtained from

(16)

where is the power of the thermal noise of

the source resistance, is Boltzmanns constant, is the resis-

tance of the source, and is temperature in degrees Kelvin. The

noisefigure of the amplifier with both series inductive peaking

and current feedback can be obtained by substituting and

of the amplifier given in Table II into (16).

To simplify analysis, we notice that the bandwidth of the am-plifier is given by . Because the frequency

of the input is upperbounded by and ,

the terms in the expression of can be simplified as follows:

(17)

As a result

(18)

The noisefigure of the amplifier is obtained from

(19)

Fig. 8 plots the noise figure of the amplifiers for the given circuit

parameters. The relatively large value is due to the chosen

circuit parameters. It is observed from the figure that current

feedback deteriorates noise performance. Also, the amplifiers

without series inductive peaking levels up at high frequencies,

mainly due to the increased coupling between the input and

output stages. Series inductive peaking does not increases noise

figure. It significantly reduces noisefigure at high frequencies.

VII. DYNAMIC RANGE

The lower bound of the input dynamic range of the ampli-

fiers is set by the power of the input-referred noise generators

whereas the upper bound is determined by the level of the har-

monic distortion at the output. Although there are many defini-

tion of the upper bound of the dynamic range of amplifiers, such

as using the amplitude of the input when 1% of total harmonic

distortion is observed at the output [34] or when the distortion

level equals to the noise level to set the maximum input am-

plitude, these methods, however, exclusively relies upon CAD

tools. In this section, we give an efficient technique that uses

the pinch-off condition to estimate the upper bound of the cur-

rent-mirror amplifier. Consider the basic amplifier with .

The pinch-off condition of the output transistor is given by, where is the maximum


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TABLE II

AND

OFCURRENT-MODEAMPLIFIERS

Fig. 8. Noisefigure. Parameters used in simulation: sheet resistance of poly , nH, , , 2 , effective gate voltage 0.3 V, m, ,

,

m, 2

V,

, , , , and .

output voltage set by the pinch-off condition of and is

the device threshold voltage. At the pinch-off of , we have

(20)

where , is the surface mobility of free

electrons, and is the gate capacitance per unit area. For ,

neglecting the effect of channel length modulation, we have

(21)

Substituting (20) into (21) yields

(22)

Equation (22) quantifies the maximum input current, i.e., the

upper bound of the dynamic range. The lower bound is set by

the input-referred noise current generator given in the preceding

section. Following a similar procedure, one can show that the

maximum input current of the amplifier with feedback is given

by

(23)

Equation (23) reveals that the current feedback improves the

dynamic range. An an example, let and

mA, we have mA without feedback and

mA when . Fig. 9 plots the output current

of the amplifier for various feedback gains with the input current

swept from 0 to 1.2 mA. The estimated upper bound of the input

current agrees reasonably well with the simulation results.

VIII. SLEWRATE

Slew-rate is a large-signalfigure-of-merit quantifying the eyeopening of the response. It is well understood that the slew rate


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Fig. 9. Dynamic range (left) and average slew rate (right).

of voltage-mode circuits is set by the ratio of the dc biasing

current to the value of compensation capacitor [27]. A number

of techniques including dynamic biasing that improves slew

rate by automatically increasing the DC basing current when

a large input is encountered, and slew-rate enhancement (SRE)

circuitry that employs additional circuitry to provide additional

charging and discharging currents in the event of a large input

[30][33], have been proposed to improve slew rate. These ap-

proaches, however, suffer from the following drawbacks.

1) Both dynamic biasing and slew rate enhancement cir-

cuitry are only sensitive to the magnitude not the rate of

change of inputs.

2) Slew rate enhancement circuit must be carefully biased

such that it is disabled under normal conditions and acti-vated only when a large input is present.

3) Due to the increased circuit complexity, these circuits can

not operate at high frequencies.

Unlike voltage-mode circuits, the maximum current for

charging and discharging the capacitor constituting the domi-

nant pole in CMOS current-mode circuits is only limited by the

maximum current set by the saturation constraint of transistors.

The average slew rate of the amplifier, defined as the time for

the output current to a step current input to change from 10% to

90% of its steady-state value is shown in Fig. 9. It is seen that

inductive series peaking improves the average slew rate.

IX. LOW-POWER DESIGN

One of the drawbacks of current-mirror amplifiers is their

high dc power consumption, arising mainly from the large dc

current of the output branch. Consider the two-stage current am-

plifier shown in Fig. 10 with . Assume a perfect device

match and neglect the effect of channel length modulation. The

output current is given by and the biasing cur-

rent of the output branch is given by . To re-

duce the dc current of the output branch, the dc current source

as shown in Fig. 10 is added. The channel current of

is given by and that of is given by

. If we impose and, then the output current is given by .

As an example, let and , T he t otal b iasing

current will be when and

when , a reduction of 81%! Power consumption can

be further reduced by varying . This technique is particularly

attractive for multistage current amplifiers. Fig. 10 plots the fre-

quency response of the circuit with and without this technique.

It is seen that the bandwidth is increased from 857 MHz without

employing this technique to 1.428 GHz with. Also observed is

that the current gain is also increased. The total current drawn

from the supply voltage is reduced from 7.48 mA without to

4.19 mA with.

X. MISMATCHES AND COMPENSATION

It is well understood that mismatches give rise to an output

offset current in current mirrors. In this section, we show that the

output offset current consists of bias-dependent and signal-de-

pendent components. We further show that the bias-dependent

output offset current is time-invariant and can be minimized

using the balanced configuration proposed in this section.

A. Output Offset Current

Consider the basic current amplifier of Fig. 2 with .

In the following analysis, we shall use , , and to

denote the total, the dc component and the ac component of the

gate voltage, respectively. Similar conventions apply to othervariables. Using the first-order model of MOS transistors and

neglecting mismatch, where is the gate oxide thickness,

we arrive at

(24)

The output offset current due to -mismatch, -mis-

match, -mismatch, and -mismatch can be derived from

(24) individually and the results are given in Appendix B. It

is seen from Table III in Appendix B that the dc-dependent

output offset currents are time-invariant whereas the ac-depen-

dent output offset currents are time-varying. Also seen is thatboth components are directly proportional to the current gain.


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Fig. 10. Power reduction technique for current-mode circuits. Circuit parameters: m for all transistors, m, m, m, m, m for . Transistor width for and is 10 m and 25 m, respectively.

TABLE IIIOUTPUTOFFSETCURRENT OFCURRENT-MODEAMPLIFIERS

The output current of the amplifier with mismatches considered

is given by

(25)

where the mismatch coefficient in the worst case is obtained

from

or in a more standard form

B. Balanced Configuration

The fact that the dc-dependent output offset current is time-in-

variant suggests that it can be minimized using the balanced con-

figuration given below. Since the mismatch coefficient of nMOS

mirrors differs from that of pMOS mirrors, the two-stage config-

uration consisting of a nMOS stage and a pMOS stage, as shown

in Fig. 11, is employed. Note that both biasing current sources

have identical paths to the output node. Because the difference

between the mismatch coefficient of nMOS current mirrors is

much smaller as compared with the difference between the mis-

match coefficients nMOS current mirrors and that of pMOS cur-

rent mirrors, it is reasonable to assume that all nMOS currentmirrors has the same mismatch coefficient and allpMOS cur-

Fig. 11. Balanced configuration.

rent mirrors have the same mismatch coefficient to simplify

analysis. Making use of (25)

(26)

where we have neglected the second-order terms

and . In a similar manner

(27)

The difference of (26) and (27) yields the output current

(28)

It is evident that the output offset current is reduced from

without the balancing network to

with the balancing network. For class A

current-mirror amplifiers, because usually holds, a

significant reduction in the output offset current is achieved.

To assess the effectiveness of this technique, the circuit of

Fig. 11 was analyzed using Spectres Monte Carlo simulation

tools. Because and are assumed to be the same for all

nMOS and pMOS current-mirror pairs, respectively, the device

dimensions are set as the follows: , ,

where and are Gaussian with the mean and standard de-viation given by m and m, respectively.


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Fig. 12. Statistical analysis of balanced network. Circuit parameters:

A,

,

m and

m. Only the dimensionmismatch of nMOS mirrors is considered. The input is a sinusoid of frequency 1 GHz and amplitude 10

A, 20 samples in Monte Carlo analysis. Leftbalancingnetwork is activated. Right balancing network is not activated.

Fig. 13. Simplified schematic of differential current-mode preamplifier.

Fig. 12 shows the output current of the circuit with 20 samples.

It is observed that without the balancing network, the output

current contains both the bias-dependent and signal-dependent

components and spreads over the range A A.

With the balancing network, the bias-dependent output offset

current is removed. As a result, the spread of the output current

is much smaller.

XI. FULLY BALANCED DIFFERENTIALCURRENT-MODE

PREAMPLIFIER

In this section, we apply the inductive series peaking, cur-

rent-current feedback, and balanced configuration to the design

a fully differential current-mode preamplifier. The schematic of

the preamplifier is shown in Fig. 13 with its parameters given

in Table IV. The dominant poles are located in the second stage

and a pair of series peaking inductors are placed in the second

stage. The preamplifier is analyzed using Spectre with BSIM3.3device model. All stages are biased carefully with biasing volt-

TABLE IVCIRCUIT PARAMETERS OFPRE-AMPLIFIER. ALLTRANSISTORSHAVE THE

SAMECHANNELLENGTH m

ages V, V, V, and

V. The frequency response of the preamplifier is

shown in Fig. 14. The dc gain of the preamplifier without se-

ries inductive peaking and current feedback is 42.4. Its band-width is 0.747 GHz. When only is used, the dc gain


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Fig. 14. Frequencyresponse of preamplifier. isvariedfrom 5 to25 nHwithstep 5 nH. The series resistance of the inductors is 5 .

drops to 18.45 and the bandwidth increases to 1.37 GHz. When

and nH are used, the preamplifier provides

a differential dc current gain of 18.45 and bandwidth 2.15 GHz.

With a 50 load, the preamplifier provides a transimpedance

gain of 60 dB .

To analyze the effect of the spread of circuit parameters, in

particular,devicemismatches,ontheresponseofthepreamplifier.

Monte Carlo analysis was carried out. Because and are

assumed to be the same for all nMOS and pMOS current mirrors

with the same input nMOS (pMOS) transistor size, respectively,

the device dimensions are set as the follows: ,

, , , ,, , , , ,

, , where , , and

are Gaussian with mean m, m, and

m, and standard deviation m,

m, m, respectively. The series peaking inductor

isalsoGaussianwithmean nHandstandard deviationof

nH. Fig. 15 plots the results of Monte Carlo simulation

with20samples.Asacomparison,therandomnessofthewidthof

all biasing transistors of the preamplifier was removed

and Monte Carlo analysis was carried out. The results are also

plottedinFig.15.Itisevidentthatthespreadoftheoutputcurrent

without the balancing network is much larger as compared with

that with the balancing network.

As pointed in [25] that the common-mode output of a differ-

ential amplifier is mainly due to the mismatches of the amplifier.

Common-mode feedback is usually required to ensure that the

common-mode output is well controlled so that transistors are

always biased properly. In out implementation, common-mode

feedback was not employed because the balanced configuration

effectivelyminimizesthe outputcurrentresultedfromdevicemis-

matches, as evident from the results of Monte Carlo analysis.

The layout of the preamplifier is shown in Fig. 16. Symmet-

rical multifinger interdigitized layout techniques were used to

layout all matched transistors. In addition, a global n-well was

used to house all pMOS devices. Multiple pull-up contacts wereused to ensure that the n-well is well connected to the power rail.

A large number of vias were used to route signals from the top

metal layer to lower metal layers to minimize the effect of con-

tact and via resistances. Two series peaking inductors are placed

outside and buses sothat theireffect on the coreis min-

imized. To minimize pad-to-substrate capacitances, only the top

two metal layers (m6 and m5) were used to construct the pads.

Four pads were used for and , respectively, to reducethe switching noise. To minimize the parasitic capacitance of

the signal interconnects, the top metal layer was used to route

both the input and output signals. Also, the interconnects neigh-

boring the signal lines are placed as far as possible to minimize

the mutual capacitances. No shielding is used for both input and

output signals as it deteriorates the bandwidth.

XII. CONCLUSION

The analysis and design of a low-voltage differential CMOS

current-mode preamplifier has been presented. The number

of transistors between the power and ground rails is only two

so that the minimum supply voltage of the preamplifier is. To increase the bandwidth, inductive series peaking

and current feedback, have been proposed. The inductive series

peaking improves the bandwidth by making use of the resonant

characteristics of networks. The added inductor does not

affect the dc characteristics of the preamplifier. It is sized

based on the criterion of maximum bandwidth with minimum

ringing. The effect of both the parasitic series resistance and

shunt capacitances of the inductor on the performance of the

preamplifier has been investigated. To further increase the band-

width, a new current feedback that is specific to low-voltage

CMOS current-mode circuits has been proposed. No series

current-sensing element is required. Because the mechanisms

of inductive series peaking and current feedback differ funda-

mentally, they can be used simultaneously to achieve further

bandwidth improvement. This has been confirmed from the

simulation results. The employment of current feedback also

effectively reduces the inductance needed for bandwidth en-

hancement. This is significant because on-chip spiral inductors

are extremely area-greedy not only because of its small induc-

tance, but also because of the large clearance between spiral

inductors and other neighboring devices set by the design rules

of CMOS fabrication processes.

Current feedback increases the noise of the amplifier, arising

from the thermal noise of the feedback network. The series

peaking inductor does not increase the noise. Instead, it im-proves the noise performance of the amplifier at high frequen-

cies. The employment of current feedback increases the upper

bound of the dynamic range.

The output offset current of current-mode circuits consists of

bias-dependent and signal-dependent components. The former

is time-invariant whereas the later is time-varying. The bias-

dependent component can be minimized effectively using the

balanced configuration.

APPENDIX I

INPUT-REFERREDNOISE OFPRE-AMPLIFIERS

Here, we derive the power of input-referred noise voltagegenerator and that of the noise current generators of the


12/14


Fig. 15. Monte Carlo analysis of preamplifier. Top left: time-domain response with balancing network; top right frequency response with balancing network;bottom left: time-domain response without balancing network; bottom right frequency response without balancing network.

Fig. 16. Layout of preamplifier.

preamplifiers. The assumption is used

for simplifying analysis. The noise equivalent circuit of the

preamplifier of Fig. 6 is shown in Fig. 17. Note that sincethe preamplifiers operate at high frequencies, the flicker noise

Fig. 17. Noise equivalent circuit of the preamplifier with current feedback and

inductive series peaking.

of MOS transistors, which has a typical corner frequency

of a few MHz [27], is neglected without introducing a large

error. Further neglecting the thermal fluctuation of diffusion

current, the power of the thermal noise of the MOS transistor

is mainly due to the thermal fluctuation of the drift current

and is given by [29], where for deep

submicron devices [26]. The thermal noise of the gate series

resistance is modeled as a noise voltage generator with its

power , where is the series resistance of

the gate computed from , and are the

width and length of the gate, respectively, and is the sheetresistance of the poly gate. is typically in the range of 57


13/14


. The thermal noise of the gate resistance can be signi ficant

as compared gate-referred noise of the thermal noise of the

channel given by . The gate series

resistance must be minimized in order to reduce its thermal

noise. This can be achieved effectively using multi-finger layout

techniques from which the gate resistance becomes ,

where is the number offingers. In this section, we neglectthe modulation effect of the thermal noise of the gate resistance

on the transconductance of the transistors simply becomes

, where is the dc gate voltage. As a result, the

thermal noise of the channel is considered to be stationary and

uncorrelated with the thermal noise of the gate series resistance.

The noise generated by other parasitics of MOS transistors,

such as source and drain bulk resistances is usually much

smaller as compared with and , and is neglected here.

Here, we derive the input-referred noise voltage generator

and noise current generator of the amplifier with the peaking

inductor and current feedback. To derive , wefirst short-cir-

cuit the input port and compute the total output noise power dueto the noise sources in the circuit

(29)

We then remove all noise sources and compute the noise power

of the output current due to only

(30)

Equating (29) and (30) yields

(31)

To derive , wefirst open-circuit the input port and compute

the output noise power due to all noise sources in the circuit

(32)

The internal noise sources are then removed. The input-referred

noise current generator is applied to the input port and the

corresponding output noise power is derived

(33)

Equating (32) and (33) yields

(34)

Fig. 18. Dimension mismatch. Left: MOS transistors with onefinger. Right:MOS transistors with two fingers.

APPENDIX II

MISMATCH-INDUCEDOUTPUTOFFSETCURRENT

In this Appendix, we analyze the output offset current of the

current amplifiers.

A. -Mismatch

-mismatch is due to the variation of fabrication process.

Consider dimension mismatch only and let .

Since large transistors are normally laid out using multifingerconfiguration to minimize both the gate series resistance and

source/drain-to-substrate capacitances, the dimension mismatch

of transistors with multifinger configuration differs from that of

transistors with single-finger configuration, as shown in Fig. 18.

In the two-finger configuration case,

whereas in the one-finger configuration .

For amplifiers with current gain of , we have

(35)

where , , and denotes

mathematical expectation operator. Equation (35) reveals that

transistors with multiple fingers have a large mismatch.Equation (24) becomes

(36)

where . It is seen that the smaller

the dimension mismatch coefficient , the smaller the mis-

match-induced output offset current.

B. -Mismatch

-mismatch is mainly due to process variation and unbal-

anced interconnects connecting the gate and source of the input

and output transistors. Consider -mismatch. Let

, . Neglecting the second-order term,

we arrive at

(37)

where . Note that since the effective

gate voltage is usually small, contributes signif-

icantly to the overall output offset current.

C. -Mismatch

-mismatch is process-induced and can be analyzed in a

similar way as -mismatch.

(38)

where . For the same reason as thatfor -mismatch, -mismatch is critical.


14/14


D. -Mismatch

In a similar manner as that of mismatch, one can show

that

(39)

where . For long channel devices,because is small, the effect of channel length modulation is

negligible. So the effect of -mismatch is small. For deep

submicron devices, , however, must be taken into account.

In practice, since , , we have

and , subsequently

and . This leads to

(40)

The dc and ac components of the output offset current are tab-

ulated in Table III.

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Fei Yuan (S96SM02) received the B.E. degreein electrical engineering from Shandong University,Jinan, China in 1985, the MASc. degree in chemicalengineering, and Ph.D. degree in electrical engi-neering from University of Waterloo, Waterloo, ON,Canada in 1995 and 1999, respectively.

During 19851989, he was a Lecturer in the De-

partment of Electrical Engineering, Changzhou Insti-tute of Technology, Jiangsu, China. In 1989, he was

a Visiting Professor at Humber College of AppliedArts and Technology, Toronto, ON, Canada. During

19891994, he worked for Paton Controls Limited, Sarnia, ON, Canada as aControls Engineer. Since July 1999, he has been with the Department of Elec-trical and Computer Engineering, Ryerson University, Toronto, ON, Canada,where he is an is currently an Associate Professor and the Associate Chairfor Undergraduate Studies and Faculty Affairs. He is the coauthor of Com-

puter Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag,2004, with A. Opal). His current research interests include design and simula-tion of mixed analogdigital circuits for Gbps data communications.

Dr. Yuan received the Ryerson Research Chair award from Ryerson Univer-sity in January 2005, the Research Excellence Award from the Faculty of Engi-neering and Applied Science of Ryerson University in 2004, the post-graduatescholarship from Natural Science and Engineering Research Council of Canada

during 19971998, and the Teaching Excellence Award from Changzhou In-stitute of Technology in 1988. He is a Registered Professional Engineer in theprovince of Ontario, Canada.

bandwidth enhacement by inductor + current feedback

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