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    Burst Clock ControllerKumar Gavanurmath

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    Agenda

    What is Burst clock.Why Burst clock.

    BCC Architecture. (Mentor)

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    BCC

    Scan Burst is an innovative new ats!eed "#$ ("esign

    %or$est) tool %rom &ogic 'ision designed s!ecically toovercome the limitations o% traditional ats!eed "#$techni*ues.

    A techni*ue to rene ats!eed launch and ca!tureclock edge !lacement +y a!!lying several ats!eed

    shi%t cycles +e%ore the launch.   $his reduces !ower droo! and may make ats!eed

    edge !lacement more accurate during ca!ture.

    ,-tension to &S.

    nce the scan chains are %ully loaded the controller

    shi%ts to the +urst !hase in which the true %unctionalclocks are a!!lied. $he scan chains are still le%t in theshi%t mode while the scan data rotates through thescan chains %or a %ew cycles. $hen a single ca!turecycle is a!!lied and the data is shi%ted out

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    Why Burst/

     $he traditional a!!roach o% testing %or !er%ormancerelated de%ects with A$0G+ased solutions has +een togenerate !atterns that target transition delay %aults.

     $hese !atterns are a!!lied using two ats!eed

    %unctional clock cycles to create a 1launch2 and1ca!ture2 se*uence. $his a!!roach is o%ten re%erred toas 1+roadside2 or 1dou+leca!ture2 timing. $histechni*ue however o%ten lacks accuracy resulting intest esca!es. 3n !articular it su4ers %rom what is

    re%erred to as 1clock stretching.2 $his !henomenon is caused +y the instantaneous drain

    on !ower rails during the launch and ca!ture cyclesthat results in an increase o% the clock !eriod an overlyand reduced delay %ault detection.

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    Cont...

    "uring the +urst !hase all %unctional clocks areena+led to !roduce a +urst o% clock cycles. $he +urstis long enough to make sure that the su!!ly has timeto sta+ili5e +e%ore the launch and ca!ture cycles.

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    Cont...

    We can control how many ats!eed shi%t cycles to +eslowed down during the +urst !hase (slowed downcycles) and the spacing between the slowed down pulses (efective slowed down requency).

    The number o at-speed burst cycles (burst length)

    that a BCC will generate is -ed at the design time. we should trade o4 these values with considerations

    %or !ower consum!tion test time and test *uality.

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    Burst Clock Controller

    • $he setu! time at the in!ut o% the clock gating cell is a %ull!eriod ($) o% theclock in!ut in the single clock case whereas it is hal% a !eriod inthe synchronous clock grou! case.

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    Cont...

    nce all scan chains are loaded they are closed intorotating segments 6 rotate at the true %unctionals!eed causing the needed ats!eed activity +e%orethe single ca!ture cycle.

     $he num+er o% clock cycles during the +urst !hase is

    called the +urst length. t deaults to ! but can bespeci"ed as small as two cycles.

    A +urst length o% 7 cycles corres!onds to %our rotatingshi%t cycles %ollowed +y a single ca!ture cycle. $heshi%t clock cycles during the Burst Mode can +e

    slowed down at run time to !recisely tune theinstantaneous !ower level around the ca!ture edge tomatch the true worst case o% instantaneous %unctional!ower.

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    "etail "iagram o% ClockController

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    Shi%t Clock Controller(#SM)

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    Burst Mode TimingDiagram

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     $he +enets o% the BurstModelogic B3S$ architecture

     $rue ats!eed testing on all clock domains with +othlogic B3S$ and A$0G !atterns.

    Com!lete short and longterm !ower management

    nly one controller !er layout region +ecause there isno need to %urther !artition %or !ower true ats!eedor clock s!eed +inning re*uirements.

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    3m!lementation o% timingarchitecture

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    8e%erence

    Embedded Test Hardware Reference

    Software Version 2014.1

    • LV Flow User’s Manual

    Software Version 2014.1

    https://www.google.co.in/patents/US7155651

    http://var/www/apps/conversion/tmp/scratch_2/Burst%20Clock%20Controller.pptxhttp://var/www/apps/conversion/tmp/scratch_2/Burst%20Clock%20Controller.pptx

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    Thank o!


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