calibre 3dstack - global semiconductor alliance...2012/04/03 · rve results n calibre 3d-ic...

Calibre 3DSTACK John Ferguson Marketing Director – DRC Applications

2 © 2010 Mentor Graphics Corp. Company Confidential www.mentor.com

Stacking Chips System View, Configurations and Interfaces

Design development on specific dies — Different design groups — “Commodity” die usage — “Template” design layer used for alignment

Multiple technology nodes Support flexible stacking configurations Easily change configurations Verify interface from one die to another

— Outside layers — Pad alignment


3DIC Physical Verification Challenge

2D PV Assumes Vertical Depth by Layer — All polygons on the same layer considered “co-planar” and can be

merged

2.5D and 3D Assemblies — Same layer at different die placements — Conflicting layer maps from separate die processes

Need a Method to Treat Each Placement Layer Uniquely

TSV Devices

BM1

M1 TSV Substrate

TSV Devices

BM1

M1 TSV Substrate

TSV Devices

BM1

M1 TSV Substrate

TSV Devices M1 Substrate


Calibre 3D-IC Verification Flow Maintain standard DRC, LVS, PEX verification processes

— Example for an advanced “SoC” – Logic/GPU verified to TSMC N28 – Memory verified to Micron 3X nm – Analog verified to TSMC N90

Introduce 3D interface verification solution — Consider: offset, rotation, scaling, etc… — Trace connectivity of interposer, 3D assembly

90nm Analog 3X nm memory

3X nm memory

3X nm memory

28nm GPU / µP

Benefits — Minimal disruption to existing verification flows

– Support flexible stacking configurations of multiple dies — Easily change configurations

– Use different process nodes together — Avoids complexity and scalability failure of

“Mega-merge” — Maximum flexibility

90nm Analog

3X nm memory

28nm GPU / µP

Die Interfaces

Chip PV

3D PV

TSMC

Micron

TSMC


Stacking Chips Pad Alignment

Verify that connections are “correct” Microball connections

— Small chip-chip coupling

Cu-Cu — May need to consider coupling

Microball and pad

Interface Layers


RVE Results

n

Calibre 3D-IC Verification Flow

Run DRC / LVS / xRC on individual chips nmDRC RVE

Results 1

Design n GDS

SPICE Netlist

Golden Foundry Deck n

Verify 3D-IC stack — Trace die-to-die or die-to-interposer connectivity — Consider: offset, rotation, scaling, etc…

Design 1 GDS

Golden Foundry Deck 1

SPICE Netlist

nmLVS

xACT 3D

3D-IC Rule Deck

Results Calibre

(for 3D-IC) Assem. 3D-IC

Design n GDS

Design 1 GDS

Verified Designs

Design n GDS

Design 1 GDS

CCI to Other


Calibre 3DSTACK: Verification Flow

Calibre 3DSTACK

Chip N

3DSTACK Rules

Assembly GDS

Chip 1 Chip 1 Chip 1 Chip 1 Chip 1

Spice N

Chip 1 Chip 1 Chip 1 Spice1 Spice1

Layout Assembly

Check

Netlist Assembly

Assembly Extracted

Netlist

Results


Physical Verification Checks

DRC Checks — Geometric overlap constraints — Center to center alignment — Grid and spacing constraints

LVS Checks — Identify mismatch connections between source and layout — Port/pin label checks — Identify layout ports not in the source

Location Checks — Ensure all expected die to die physical connections exist — Requires “source” with specific pad or bump locations (AIF)


Physical Alignment Checks: Overlap Requirements

Not highlighted as chip1 pad and chip2 pad are fully coincident (overlap = 100%)

Highlighted as overlap < the constraint (99%)


Physical Alignment Checks: Center to Center Alignment

Highlighted as center to center spacing between chip1 pad and chip2 pad is <

0.01um


Connectivity Checks: Interposer Black-Box

Verify connections by matching texts on pads (from layout) with the pin name in source netlist

- No Text Warnings

- Multi Text Warnings

- Floating Text Warnings


Connectivity Checks: Interposer White-Box

Verify connections by matching the metal layers routing (from layout) with the connection in source netlist

Highlight Nets

Open Pad


Partnering with TSMC to Continuously Expand 2.5 and 3D Offerings


Success Stories: Tezzaron


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calibre 3dstack - global semiconductor alliance...2012/04/03 · rve results n calibre 3d-ic...

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