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    Code Generation

    MACHINE - DEPENDENT CODEOPTIMIZATION

    Machine Independent Compiler Features

    MACHINE - INDEPENDENT CODEOPTIMIZATION

    Compilers

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    GENERATION OF OBJECTCODE

    Code generation phase is after the syntax phase.

    Semantic routines are called when the parser recognizes a portion of the source program according tosome rule of the grammar.

    Simple scheme of a compiler Semantic routinesgenerate object code directly.

    Some complex compilers generate an intermediateform of the program.

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    The code generation routines that isdiscussed are designed for the usewith the grammar in fig

    The list of simplified Pascal grammar is shown in fig.

    1. < prog > ::= PROGRAM < program > VAR

    begin < stmt - list > end.

    2. ::= id

    3. < dec - list > ::= < dec > | < dec - list > ;

    4. < dec > ::= < id - list > : < type >

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    5. < type > ::= integer 6. < id - list > ::= id | < id - list > , id7. ::= < stmt > ; < stmt >8. < stmt > ::= | | | 9. < assign > ::= id : = < exp >10. ::= |+| - 11. ::=||DIV 12. < factor> ::= id ; int | (< exp >)

    13. < READ> ::= READ ( < id - list >)14. < write > ::= WRITE ( < id - list >)15. < for > ::= FOR < idex - exp > Do < body >

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    Note: This grammar is used for code

    generations to emphasize the pointthat code generation techniques need not beassociated with any particular parsing method.The code generation is for the SIC/XE machine. Thecode generation routines use two data structure:

    (1) A List (2) A Stack

    Listcount: A variable Listcount is used to keep acount of the number of items currently in the list.

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    The code generation routine make use of token specifiers and are denoted byS(token) .

    Example: id S (id) ; name of the identifier

    int S (int) ; value of the integer, # 100 The code generation routines create segments of object code for the compiled program. A symbolicrepresentation is given to these codes using SICassembler language.

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    LOCCTR: It is a Location counter whichis updated to reflect the next variableaddress in the compiled program (exactly as it is in anassembler).

    Application Process to READ Statement:

    The parser tree for Readstatement can be

    generated with manydifferent parsingmethods.

    (Read)

    READ ( )

    {Value}Id

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    In an operator precedence parse, therecognition occurs when a sub-string of the input is reduced to some non-terminal.In a recursive-descent parse, the recognition occurswhen a procedure returns to its caller, indicatingsuccess.

    Thus the parser first recognizes the id VALUE asan , and then recognizes the completestatement as a < read >.

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    The symbolic representation of the objectcode to be generated for the READstatement is as shown.

    + JSUB XREAD

    WORD 1WORD VALUE

    This code consists of a call to a statement XREAD,which world be a part of a standard library associatedwith the compiler. The subroutine of any program thatwants to perform a READ operation can call XREAD.

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    The parameter list for XREAD is definedimmediately after the JSUB that calls it.The first word is the number of variablesthat will be assigned values by the READ.The following word gives the addresses of thesevariables.Routines that might be used to accomplish theabove code generation.

    < id - list > : : = idadd S (id) to listadd 1 to Listcount

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    < id - list > : : = < id - list >, idadd S (id) to listadd 1 to LC ListCount

    These two statements correspond to alternative

    structure for < id - list >, that is :: = id | < id - list >, id .

    In either case, the token specifier S(id) for a newidentifier being added to the is inserted intothe list used by the code-generation routines, andListcount is updated in incrementing.

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    < read > : : = READ (< id - list >)

    generate [ + JSUB XREAD ]record external reference to XREAD

    generate [WORD Listcount]for each item on list do begin

    remove S (ITEM) from list

    generate [WORD S (ITEM)] endList _count : = 0

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    Code-generation Process for theAssignment Statement

    Example:

    VARIANCE:=SUMSQ DIV 100 - MEAN * MEAN

    Solution

    The parser tree for this statement is shown in fig.Most of the work of parsing involves the analysisof the on the right had side of the " : = "statement.:

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    Id{SUMQ}

    DIV Int{100}

    -:=Id

    {VARIANCE}

    Id Id

    *{MEAN} {MEAN}

    Parser Tree

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    A code-generation routine is called for

    each portion of the statement isrecognized.Example: For a rule 1:: = 2 *

    a code is to be generated. The subscripts are used todistinguish between the two occurrences of .

    The code-generation routines perform all arithmeticoperations using register A.

    Before multiplication one of the operand 2 mustbe located in A-register.

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    The results after multiplication, 2 *

    will be left in register A. So we need to keep track of the result left in register A by each segment of codethat is generated.

    This is accomplished by extending the token-specifier idea to non-terminal nodes of the parse tree.

    The node specifier S( 1) would be set to rA. Thisindicates that the result of this computation is inregister A.

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    The variable REGA is used to indicate

    the highest level node of theparse tree whose value is left inregister A by the code generated sofar.

    1. < assign > :: = id := GETA (< exp >)generate [ STA S(id)]REGA : = null

    The code generation routine for consists of bringingthe value to be assigned into register A (using GETA). TheSTA instruction is generated to store the value in A register.

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    Note that REGA is then set to nullbecause the code for the statementhas been completely generated,and any intermediate results are nolonger needed.

    The following rules do not require the generation of any machine instructions since no computation or data movement is involved.

    The code generation routines for these rules simplyset the node specifier of the higher-level node toreflect the location of the corresponding value.

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    2. :: =< term >S (< exp >) : = S (< term >)if S (< exp >) = rA thenREGA : = < exp >

    3. < exp > 1 :: = < exp > 2 + < term >if S(< exp > 2) = rA then

    generate [ADD S (< term >)]else if S (< term >) = rA thengenerate [ADD S (< exp > 2)]

    else

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    beginGETA (< EXP > 2)generate [ADD S(< term >)]

    end

    S (< exp > 1) : = rAREGA : = < exp > 1

    4. < exp >1

    :: = < exp >2

    - < term >if S(< exp > 2) = rA then

    generate [SUB S (< term >)]else

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    beginGETA (< EXP > 2)generate [ SUB S(< term >)]

    endS (< exp >

    1) : = rA

    REGA : = < exp > 1

    5. < term > :: = < factor >S (< term >) : = S (< factor >)

    if S () = rA thenREGA : = < term >

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    6. 1

    :: = 2*

    if S (< term > 2) = rA thengenerate [ MUL S ()]

    else if S (< factor >) = rA then

    generate [ MUL S (< term > 2)]elsebegin

    GETA (< term > 2)generate [ MUL S(< factor >)]

    endS (< term > 1) : = rA

    REGA : = < term > 1

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    7. :: = 2

    DIV if S (< term > 2) = rA then

    generate [DIV S (< factor >)]else

    beginGETA (< term > 2)generate [ DIV S (< factor >)]

    endS (< term > 1) : = rAREGA : = < term > 1

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    8. < factor > :: = idS (< factor >) := S ( id )

    9. < factor > :: = intS (< factor >) := S ( int )

    10. < factor > :: = < exp >S (< factor >) := S (< exp >)if S (< factor >) = rA thenREGA : = < factor >

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    The GETA procedure is shownProcedure - GETA (NODE)

    beginif REGA = null then

    generate [LDA S (NODE) ]else if S (NODE) rA thenbegin

    creates a new looking variable Tempi

    generate [STA Tempi]record forward reference to TempiS (REGA) : = TempiGenerate [LDA S (NODE)]

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    end (if rA)S(NODE) : = rAREGA : = NODE

    end {GETA }

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    The code generated for the above is as follows

    LDA SUMSQDIV # 100STA TMP1LDA MEANMUL MEANSTA TMP2

    LDA TMP1SUB TMP2STA VARIABLE

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    Most of the times, the phases of a

    compiler are collected into a front-end and a back-end .The front-end comprises of those phases or at timesalso parts of the phases which depend on the source

    language and are independent of the target machine.These includelexical analysis,syntactic analysis,

    creation of symbol table,semantic analysis andgeneration of intermediate code.

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    It also includes some amount of error handling and code optimization thatgoes along with these phases.

    The back-end generally includes those phases of thecompiler which depend on the target machine.They do not depend on the source language, just theintermediate language.

    Backend includescode optimization,code generation along with error handling andsymbol-table operations.

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    Some compilers generate anexplicit intermediate representationof the source program after syntaxand semantic analysis.

    This intermediate representation of the source programcan be thought of as a program for an abstractmachine and should have two main properties viz.,

    1. It should be easy to produce

    2. It should be easy to translate into the target program

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    have to write a complier for m languages targeted for nmachines. The obvious approach would be to write m*ncompilers.

    Let us consider the situation givenin the slide above. Suppose, we

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    Compilers

    This diagram shows twocompilers convertinghigher level language to

    two different object codesfor two machines.

    It means that for alanguage it is necessary to

    have as many compilers asthe number of machines.

    HLLHigh Level language

    Object codefor M1

    Object codefor M2

    Example: C language to Intel processor and Motorola processor

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    An intermediate language avoids

    most of the problems.It allows a logical separation between machineindependent and dependent phases and facilitatesoptimization.

    All we have to do is to choose a rich intermediatelanguage that would bridge both the source programsand the target programs.

    The first three phases are called as the front end of thecompiler because they are machine independent.

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    The code generation and relatedphase is called as the back end.

    The intermediate code generation is neither consider to be the back end nor front end.

    Next slide shows three languages producing acommon intermediate code. From the intermediatecode the object code for the two M/C are obtained.

    Hence if we have Mnumber of languages and Nobject code is to be obtained, the number of front andback end that needs to be written is N+M.

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    MACHINE - DEPENDENTCODE OPTIMIZATIONThere are several different possibilities for

    performing machine-dependent code optimization .

    Assignment and use of registers

    Divide the problem into basic blocks.

    Rearrangement of machine instruction toimprove efficiency of execution

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    The intermediate form that is discussed here representsthe executable instruction of the program with asequence of quadruples.

    Each quadruples of the formOperation, OP1, OP2, result.

    WhereOperation - is some function to be performed by the

    object codeOP1 & OP2 - are the operands for the operation and

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    Result - designation when the resultingvalue is to be placed.

    Example 1: SUM : = SUM + VALUE could berepresented as

    + , SUM, Value, i1:=, i1, , SUM

    The entry i1, designates an intermediate result (SUM +

    VALUE);the second quadruple assigns the value of thisintermediate result to SUM. Assignment is treated as aseparate operation ( :=).

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    Example 2 :

    VARIANCE : = SUMSQ DIV 100 - MEAN * MEANDIV, SUMSQ, #100, i1

    *, MEAN, MEAN, i2- , i1, i2, i3

    ::=, i3, VARIABLE

    Note: Quadruples appears in the order in which thecorresponding object code instructions are to beexecuted. This greatly simplifies the task of analyzingthe code for purposes of optimization. It is also easy totranslate into machine instructions.

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    Example 3 : For the program

    shown below write the quadruples.

    PROGRAM STATS VAR

    SUM, SUMSQ, I, VALUE, MEAN, VARIANCE :INTEGER

    BEGIN SUM : = 0 ;SUMSQ : = 0 ;

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    FOR I : = 1 to 100 DO

    BEGIN READ (VALUE) ;SUM : = SUM + VALUE ;SUMSQ : = SUMSQ + VALUE * VALUE

    END;MEAN : = SUM DIV 100;VARIANCE : = SUMSQ DIV 100 - MEAN * MEAN ;WRITE (MEAN, VARIANCE)END.

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    Solution

    Line Operation OP 1 OP 2 Result Pascal Statement1. : = # 0 SUM SUM : = 0

    2. : = # 0 SUMSQ SUMSQ : = 0

    3. : = # 1 I FOR I : = 1 to 100

    4. JGT I #100 (15)

    5. CALL XREAD READ (VALUE)

    6. PARA VALUE

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    7. + SUM VALUE i1 SUM : = SUM + VALUE

    8. := i1 SUM

    9. * VALUE VALUE i2 {SUMSQ:= SUMSQ +

    10.+ SUMSQ i2 i3 VALUE * VALUE}

    11.: = i3 SUMSQ

    12.+ I #1 i4 {End of FOR loop}

    13.: = i4 I

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    14. J (4)

    15. DIV SUM #100 i5 {MEAN:= SUM DIV 100}

    16. : = i5 MEAN

    17. DIV SUMSQ #100 i6 {VARIANCE := 18. * MEAN MEAN i7 SUMSQ DIV 100

    19. - i6 i7 i8 - MEAN * MEAN}

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    21.CALL XWRITE {WRITE (MEAN, VALIANCE}

    22. PARAM MEAN

    23. PARAM VARIANCE

    20. := i8 VARIANCE

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    MACHINE - DEPENDENT CODEOPTIMIZATION

    There are several different possibilities for performingmachine-dependent code optimization .

    Assignment and use of registers:

    Registers is used as instruction operand.

    The number of registers available is limited.

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    Required to find the least used register to replace with new values when needed.

    Usually the existence of jump instructions createsdifficulty in keeping track of registers contents.

    Divide the problem into basic blocks to tackle suchproblems.

    A basic block is a sequence of quadruples with oneentry point, which is at the beginning of the block, oneexit point, which is at the end of the block, and no jumpswithin the blocks.

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    CALL operation is usually considered

    to begin a new basic block.When control passes from one block to another, allvalues currently held in registers are saved intemporary variables.For example 3, the quadruples can be divided intofive blocks. They are:

    Block -- A Quadruples 1 - 3

    Block -- B Quadruples 4

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    Block -- C Quadruples 5 - 14Block -- D Quadruples 15 - 20Block -- E Quadruples 21 - 23

    A : 1 - 3

    B : 4

    C : 5 - 14

    D : 15 - 20

    E : 21 - 23

    Fig. shows the basic blocks

    of the flow group for thequadruples.

    An arrow from one block toanother indicates that controlcan pass directly from onequadruple to another.This kind of representation is called a flow group.

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    -Rearranging quadruples beforemachine code generation:

    Example : 1) DIV SUMSQ # 100 i1

    2) * MEAN MEAN i2

    3) - i1 i2 i3

    4) : = i3 VARIANCE

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    LDA SUMSQDIV # 100STA i1LDA MEANMUL MEAN

    STA i2LDA i1SUB i2STA i3

    STA Varianceshows a typical generation of machine code from thequadruples using only a single register ie Accumulator

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    The optimizing compiler could

    rearrange the quadruples so thatthe second operand of the subtraction is computed first.This results in reducing two memory accesses.

    * MEAN MEAN i2

    DIV SUMSQ # 100 i1

    - i1 i2 i3

    := i3 VARIANCE

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    LDA MEAN

    MUL MEANSTA i1LDA SUMSQDIV # 100SUB i1STA VARIANCE

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    Characteristics and Instructions

    of Target Machine :Special loop - control instructions or addressing

    modes can be used to create more efficient objectcode.

    High-level machine instructions can performcomplicated functions such as calling procedure andmanipulating data structures in a single operation.

    If multiple functional blocks can be used, the sourcecode can be rearranged to use all the blocks or most of the blocks concurrently. This is possible if the result of one block does not depend on the result of the other.

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    Machine Independent Compiler Features

    Machine independent compilers describe themethod for handling structured variables such asarrays.

    Problems involved in compiling a block-

    structured language indicate some possible solution.

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    STRUCTURED VARIABLES

    Structured variables discussed here are arrays, records,strings and sets.

    Arrays: In Pascal array declaration

    (i)Single dimension array:

    A: ARRAY [ 1 . . 10] OF INTEGER

    If each integer variable occupies one word of memory,then we require 10 words of memory to store thisarray.

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    In general an array declaration is

    ARRAY [ i .. u ] OF INTEGER

    Memory word allocated = ( u - i + 1) words.

    (ii) Two dimension array : B:ARRAY [ 0 .. 3, 1 . . 3 ]OF INTEGER

    In this type of declaration total word memory required is0 to 3 = 4 ; 1 to 3 = 3 ; 4 x 3 = 12 word memorylocations.

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    In general:

    ARRAY [ l 1 .. u 1, l2 . . u 2.] OF INTEGERRequires ( u 1 - l1 + 1) * ( u 2 - l2 + 1) Memory words

    The data is stored in memory in two different ways.They are row-major and

    column major.

    All array elements that have the same value of the firstsubscript are stored in contiguous locations. This iscalled row-major order. It is shown in fig.

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    Register Allocation

    Assign specific CPU registers for specific values. Code Generation must maintain information on

    which registers: Are used for which purposes

    Are available for reuse

    Main objective: Maximize the utilization of the CPU registers Minimize references to memory locations

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    Possible uses for CPU registers Values used many times in a program Values that are computationallyexpensive

    Importance

    Efficiency

    Speed

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    Register Allocation AlgorithmRegister Allocation Algorithm

    Register Allocation Algorithm determines howmany registers will be needed to evaluate anexpression.

    It also determines the Sequence in which sub-expressions should be evaluated to minimizeregister use.

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    Construct a tree starting at thebottom nodes

    Assign each leaf node a weight of:

    1 if it is the left child

    0 is it is the right child

    The weight of each parent node will be computed by theweights of the 2 children as follows:

    If the 2 children have different weights, take the max.

    If the weights are the same, the parents weight is w+

    The number of CPU registers is determined bythe highest summed weight at any stage in the

    tree.

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    86/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    87/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    88/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    89/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    90/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    91/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    92/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    93/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    94/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    95/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    96/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    97/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    98/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    99/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    100/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    101/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    102/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    103/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    104/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    105/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    106/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    107/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    108/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    109/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    110/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    111/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    112/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    113/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    114/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    115/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    116/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    117/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    118/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    119/120

    N.K. Srinath [email protected] 27 RVCE

  • 8/14/2019 CCode Generation

    120/120

    Code Generation, Machine Dependent Compiler Features - Intermediate Form Of The Program,

    Machine-Dependent Code Optimization, Machine Independent Compiler Features -Structured Variables, Machine Independent Code Optimization, Storage Allocation,Block Structured Languages, Compiler Design Options - Division Into Passes,Interpreters, P-Code Compilers, Compiler-Compilers.