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Brief description about the optimization of memories

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Optimizing Power @ Design TimeMemory

Benton H. Calhoun Jan M. Rabaey

Low Power Design Essentials 2008

Chapter 7

Role of Memory in ICs Memory is very important Focus in this chapter is embedded memory Percentage of area going to memory is increasing

Low Power Design Essentials 2006

[Ref: V. De, Intel 2006]

X.2

Processor Area Becoming Memory Dominated

On chip SRAM contains 5090% of total transistor count Xeon: 48M/110M Itanium 2: 144M/220M

SRAM is a major source of chip static power dissipation

SRAM

Dominant in ultra-low power applications Substantial fraction in others

Intel Penryn(Picture courtesy of Intel) Low Power Design Essentials 2008 7.3

Chapter Outline

Memory Introduction Power in the Cell Array Power for Read Access Power for Write Access New Memory Technologies

Low Power Design Essentials 2008

7.4

Basic Memory Structures

Low Power Design Essentials 2008

[Ref: J. Rabaey, Prentice03]

7.5

SRAM Metrics

Functionality Data retention Readability Writability Soft Errors

Why is functionality a metric?

Area Power

Process variations increase with scaling Large number of cells requires analysis of tails (out to 6 or 7) Within-die VTH variation due to Random Dopant Fluctuations (RDFs)7.6

Low Power Design Essentials 2008

Where Does SRAM Power Go?

Numerous analytical SRAM power models Great variety in power breakdowns Different applications cause different components of power to dominate Hence: Depends on applications: e.g. high speed versus low power, portable

Low Power Design Essentials 2008

7.7

SRAM cell Three tasks of a cell Hold data WL=0; BLs=XM6M5 M1 QB M4

BL

WL

BL

Q M3 M2

Write WL=1; BLs driven with new data

ReadTraditional 6-Transistor (6T) SRAM cell

WL=1; BLs precharged and left floating

Low Power Design Essentials 2008

7.8

Key SRAM cell metricsKey functionality metrics Hold Static Noise Margin (SNM) Data retention voltage (DRVM6M5 M1 QB M4

BL

WL

BL

Q M3 M2

Read Static Noise Margin (SNM)

Write Write Margin

Traditional 6-Transistor (6T) SRAM cell

Metrics: Area is primary constraint Next: Power, Delay7.9

Low Power Design Essentials 2008

Static Noise Margin (SNM)BL WL VNM3 M2 M6 M5 M1 M4

BLB

SNM gives a measure of the cells stability by quantifying the DC noise required to flip the cell

Q

QB

VN

Inv 1

Inv 2

0.3VTC for Inv 2 VTC-1 for Inv 1 VTC for Inv2 with VN = SNM VTC-1 for Inv1 with VN = SNM

QB(V)

0.15

SNM SNM is length of side of the largest embedded square on the butterfly curve0 0.15 0.3[Ref: E. Seevinck, JSSC87] 7.10

0

Q (V)Low Power Design Essentials 2008

Static Noise Margin with Scaling Typical cell SNM deteriorates with scaling Variations lead to failure from insufficient SNMVariations worsen tail of SNM distributionTech and VDD scaling lower SNM

(Results obtained from simulations with Predictive Technology Models [Ref: PTM; Y. Cao 00]) Low Power Design Essentials 2008 7.11

Variability: Write MarginBL WL BLBNormalized QB 1 0.8 0.6 0.4 0.2 0 0 0.2

Write failure: Positive SNM

1 0

1

0

Dominant fight (ratioed) Cell stability prior to write:Normalized QB 1 0.8 Normalized QB 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 Normalized Q 1 1 0.8 0.6

0.4 0.6 0.8 Normalized Q

1

Successful write: Negative SNM

0.40.2 0 0 0.2 0.4 0.6 0.8 Normalized Q 1

Low Power Design Essentials 2008

7.12

Variability: Cell WritabilityVDD=0.6V0.05

Write Fails0

-0.05

SNM (V)

-0.1

-0.15 TT WW SS WS SW -20 0 20 40 60 80 100 120

-0.2

-0.25 -40

Temperature (oC)

Write margin limits VDD scaling for 6T cells to 600mV, best case. 65nm process, VDD = 0.6V Variability and large number of cells makes this worseLow Power Design Essentials 2008 7.13

Cell Array Power Leakage Power dominates while the memory holds dataBL WL BL

0

1

Importance of Gate tunneling and GIDL depends on technology and voltages applied

Sub-threshold leakage

Low Power Design Essentials 2008

7.14

Using Threshold Voltage to Reduce Leakage

1-Mb array retention current (A)

100

Tj =125 C Lg =0.1 m100 C 75 C 50 C 25 C

W (QT)=0.20 m W (QD)=0.28 m W (QL)=0.18 m

High VTH cells necessary if all else is kept the same To keep leakage in 1 MB memory within bounds, VTH must be kept in [0.4, 0.6] range

10-2

high speed (0.49) low power (0.71)

10-4 10 A 10-6 0.1 A

10-8 -0.2 0 0.2 0.4 0.6 0.8 1.0 Average extrapolated VTH (V) at 25 CExtrapolated VTH =VTH (nA/m)+0.3 V

Low Power Design Essentials 2008

[Ref: K. Itoh, ISCAS06]

7.15

Multiple Threshold VoltagesBL WL BL

BL

WL

BL

0 Dual VTH cells with low VTH access transistors provide good tradeoffs in power and delay[Ref: Hamzaoglu, et al., TVLSI02]

High VTH Low VTHLow Power Design Essentials 2008

Use high VTH devices to lower leakage for stored 0, which is much more common than a stored 1

[Ref: N. Azizi, TVLSI03]

7.16

Multiple Voltages Selective usage of multiple voltages in cell array e.g. 16 fA/cell at 25oC in 0.13 m technology

1.0V

WL=0V 1.5V

1.0V

High VTH to lower subVTH leakage Raised source, raised VDD, and lower BL reduce gate stress while maintaining SNM

0.5V

Low Power Design Essentials 2008

[Ref: K. Osada, JSSC03]

7.17

Power Breakdown During Read Accessing correct cell Decoders, WL drivers For Lower Power: hierarchical WLs pulsed decodersAddressVDD_Prech WL

Mem CellSense Amp Data

Performing read Charge and discharge large BL capacitance For Lower Power : SAs and low BL swing Hierarchical BLs Lower BL prechargeLow Power Design Essentials 2008

Lower VDD May require read assist

7.18

Hierarchical Word-line Architecture

Reduces amount of switched capacitance Saves power and lowers delay[Refs: Rabaey, Prentice03; T. Hirose, JSSC90]

Low Power Design Essentials 2008

7.19

Hierarchical Bitlines

Local BLsGlobal BLs

Divide up bitlines hierarchically Many variants possible

Reduce RC delay, also decrease CV2 power Lower BL leakage seen by accessed cellLow Power Design Essentials 2008 7.20

BL Leakage During Read Access

Leakage into nonaccessed cells Raises power and delay Affects BL differential1

0

0

Low Power Design Essentials 2008

Bit-line7.21

Bitline Leakage SolutionsVSSWL VSSWL

1Vg

0VGND

1

0

Raise VSS in cell (VGND)

Negative Wordline (NWL)

Hierarchical BLs Raise VSS in cell Negative WL voltage Longer access FETs Alternative bit-cells Active compensation Lower BL precharge voltage[Ref: A. Agarwal, JSSC03] 7.22

Low Power Design Essentials 2008

Lower Precharge Voltage

Lower BL precharge voltage decreases power and improves Read SNM Internal bit-cell node rises less Sharp limit due to accidental cell writing if access FET pulls internal 1 low

Low Power Design Essentials 2008

7.23

VDD Scaling Lower VDD (and other voltages) via classic voltage scaling Saves power Increases delay Limited by lost margin (read and write)

Recover Read SNM with read assist Lower BL precharge Boosted cell VDD [Ref: Bhavnagarwala04, Zhang06] Pulsed WL and/or Write-After-Read [Ref: Khellah06] Lower WL [Ref: Ohbayashi06]

Low Power Design Essentials 2008

7.24

Power Breakdown During Write Accessing cell Similar to Read For Lower Power: Hierarchical WLsAddressVDD_Prech WL

Mem Cell

Performing write Traditionally drive BLs full swing For Lower Power : Charge sharing Data dependencies Low swing BLs with amplificationData

Low Power Design Essentials 2008

7.25

Charge recycling to reduce write power

Share charge between BLs or pairs of BLs Saves for consecutive write operations Need to assess overheadBasic charge recycling saves 50% power in theory1 BL= 0V BLB= VDD BL= VDD/2 0 BLB= VDD/2 BL= VDD 1 BLB= 0V

old values

connect floating BLs

disconnect and drive new values

Low Power Design Essentials 2008

[Refs: K. Mai, JSSC98; G. Ming, ASICON05]

7.26

Memory Statistics 0s more common SPEC2000: 90% 0s in data SPEC2000: 85% 0s in instructions

Assumed write value using inverted data as necessary [Ref: Y. Chang, ISLPED99] New Bitcell:BL WL

BL

WZ

1R, 1W port W0: WZ=0, WWL=1, WS=1 W1: WZ=1, WWL=1, WS=0WS

WWL

Low Power Design Essentials 2008

[Ref: Y. Chang, TVLSI04]

7.27

Low-Swing Write

Drive the BLs with low swing Use amplification in cell to restore valuesSLC WL EQ WE

VDD_Prech EQ BL WL Q QB BLB

SLCVWR=VDD-VTH-delVBL VWR DinVDD-VTH column decoder

BL/BLBQ/QB

VDD-VTH-delVBL

WE

Low Power Design Essentials 2008

[Ref: K. Kanda, JSSC04]

7.28

Write Margin Fundamental limit to most power-reducing techniques Recover write margin with write assist, e.g. Boosted WL Collapsed cell VDD [Itoh96, Bhavnagarwala04] Raised cell VSS [Yamaoka04, Kanda04] Cell with amplification [Kanda 04]

Low Power Design