circuitos digitales ii the general computer architecture the cpu control unit semana no.9 semestre...
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![Page 1: Circuitos Digitales II The General Computer Architecture The CPU Control unit Semana No.9 Semestre 2008-2 Prof. Gustavo Patiño gpatino@udea.edu.co Prof](https://reader036.vdocument.in/reader036/viewer/2022062404/5519c13655034660578b4b9e/html5/thumbnails/1.jpg)
Circuitos Digitales IICircuitos Digitales II
The General Computer Architecture
The CPU Control unitSemana No.9Semana No.9
Semestre 2008-2Semestre 2008-2
Prof. Gustavo PatiñoProf. Gustavo Patiñ[email protected]
Prof. Eugenio DuqueProf. Eugenio [email protected]
Departamento de Ingeniería ElectrónicaDepartamento de Ingeniería Electrónica
Facultad de IngenieríaFacultad de Ingeniería
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
The Central Processor Unit (CPU)
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
The CPU Control Unit
Having “designed” the ALU or datapath so that it can perform the necessary instructions, we now have to do the same thing for the control unit, which decodes instructions and provides direction to the CPU.
The MIPS control unit decodes the six bits on either end of the 32-bit instruction word, that is, the op code and function code* fields, to determine each instruction sequence.
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Functionality of Control Unit
The control unit determines ALU functions in each instruction and selects operands for the ALU.
The operation code (the left six bits of the instruction) determines the type of operation and in some cases (such as jump instructions) the actual instruction itself.
In the case of register-register instructions, the function code determines the instruction (for example, in the R/R instruction above, the function code 0x 20 means “add”).
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Functionality of Control Unit (…cont)
The control unit is a collection of decoders and multiplexers.
The decoded instruction fields tell The ALU what function to
perform, What operands to use.
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Completing ALU Design
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Current Architecture
The ALU control uses instruction bits 0-5 to obtain information about the ALU operation in register-to- register instructions.
Note in the following diagram that some of the decoding is done in the register block, which has the decoding mechanism that identifies source and destination registers in load/store and register/register operations.
The ALU control also has input control lines from the operation code decoder which decodes bits 26-31, and which will be shown later.
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
ALU Design with ALU Control Design shown
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
ALU Control Block
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Single-Cycle ALU Design with Full Control Block
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Stages on the MIPS processor
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Op Code Control Block Signal Identifier
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Function OpCode Control Signals
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
OpCode Control Block Circuitry
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Instruction Disposition Showing Destination Units
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Data/Control Signal Flow Examples The following diagrams illustrate the flow of control
signals and data in some example MIPS instructions in the single cycle implementation.
The “single cycle” implementation is just a stepping stone to the final MIPS design, but this simpler example has all the features of the more complex final design in terms of data routing and the way in which the control signals determine the specific operation for each given instruction.
Note the data flow in these instructions.
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Start of R-Type Instruction
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Next Step of R-Type Instruction
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Third Step of R-Type Instruction
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Completion of R-Type Instruction
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Load Instruction
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Branch Instruction
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Jump Instruction Circuitry Added
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Jump Instruction Flow
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Drawbacks of the Single-Cycle Implementation
We have now completed “design” of the basic MIPS CPU. Although a good basic design, it has a serious drawback:
The processor is designed so that all instructions complete in one clock cycle.
While this assures that there is sufficient time to complete any instruction, it also means that one clock period must be long enough to accommodate the longest and most complicated instruction.
Thus, ALL instructions take as long as the longest instruction.
Since many (most!) instructions in the MIPS architecture take less time to execute than the longest instructions (which are usually the lw memory reference instructions), this means that we are slowing execution of the CPU a large part of the time to accommodate instructions that occur substantially less frequently.
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Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia
2008-2
Comparative Instruction Timing