circuitos digitales ii the general computer architecture the multicycle design semana no.10 semestre...

Circuitos Digitales IICircuitos Digitales II

The General Computer Architecture

The Multicycle DesignSemana No.10Semana No.10

Semestre 2008-2Semestre 2008-2

Prof. Gustavo PatiñoProf. Gustavo Patiñ[email protected]

Prof. Eugenio DuqueProf. Eugenio [email protected]

Departamento de Ingeniería ElectrónicaDepartamento de Ingeniería Electrónica

Facultad de IngenieríaFacultad de Ingeniería

Departamento de Ing. Electrónica Circuitos Digitales II Universidad de Antioquia

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Data/Control Signal Flow Examples The following diagrams illustrate the flow of control

signals and data in some example MIPS instructions in the single cycle implementation.

The “single cycle” implementation is just a stepping stone to the final MIPS design, but this simpler example has all the features of the more complex final design in terms of data routing and the way in which the control signals determine the specific operation for each given instruction.

Note the data flow in these instructions.


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Start of R-Type Instruction


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Next Step of R-Type Instruction


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Third Step of R-Type Instruction


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Completion of R-Type Instruction


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Load Instruction


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Branch Instruction


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Jump Instruction Circuitry Added


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Jump Instruction Flow


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Drawbacks of the Single-Cycle Implementation

We have now completed “design” of the basic MIPS CPU. Although a good basic design, it has a serious drawback:

The processor is designed so that all instructions complete in one clock cycle.

While this assures that there is sufficient time to complete any instruction, it also means that one clock period must be long enough to accommodate the longest and most complicated instruction.

Thus, ALL instructions take as long as the longest instruction.

Since many (most!) instructions in the MIPS architecture take less time to execute than the longest instructions (which are usually the lw memory reference instructions), this means that we are slowing execution of the CPU a large part of the time to accommodate instructions that occur substantially less frequently.


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Comparative Instruction Timing


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MultiCycle Implementation

A solution to the single-cycle problem is stated as follows: Each instruction has several phases, such as fetch/decode,

register selection, ALU processing, etc. Instead of using a single clock cycle for the whole

instruction, run the clock much faster, and have a single clock cycle for each of the elements or phases of the instruction process.

Many instructions take fewer phases (for example, jump, branch [the fewest phases], register-register or store instructions), so these instructions execute much faster.

As most instructions execute faster than the longest instructions (such as lw), the average instruction time will be reduced substantially.


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MIPS Multicycle Concept

Split the processing into five processing segments. Run the clock much faster (essentially 5X faster!). Do one instruction segment per clock cycle. PC updates, branches and jumps take 3 processing

segments since they are simpler; they run much faster. Register-register instructions do not require memory

access. They take four instruction segments and finish in about 30% more time than jumps and branches.

Only load memory-access instructions take a full five processing segments (store takes only four), but do not slow down the other instructions to their speed.


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Multicycle Implementation


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Times Instruction Cycle Times


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Multicycle Advantages

For most instructions, it is saved 20-40% in clock cycles and the processor is much faster, as mentioned earlier.

Since different parts of the circuit are active only for one cycle at a time, we can use less circuitry because parts of the computer can be reused in different cycles. The CPU now needs only one ALU, since it can do the PC

update functions prior to the ALU processing. Since we access memory for data and instructions in

different clock cycles, we only need one path to memory.


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Major Impediment to Multicycle Implementation The multicycle processor takes up to 5 clock cycles

to complete an instruction. Each time the clock ticks, part of the instruction is

completed, not all of it. That means that at the end of each clock cycle, we

have partial instruction results, but no place to store them!

A first concern is therefore a way to store intermediate data as the instruction winds its way through the various segments of processing.


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Intermediate Results Storage Requirements


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First-Pass Register Placement


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Preliminary Multicycle Design Without Control

The preliminary processing design is more compactThe preliminary processing design is more compact


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Multicycle with ALU Control and PC


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Completed Multicycle Design


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Multicycle Summary

We have redesigned the MIPS CPU to accommodate a 5-segment instruction partition with each segment taking one clock cycle.

In doing so, instruction execution time was decreased ~ 30-40% and greater efficiency was obtained by reducing the circuitry.

In the next lecture, we will take the final step in the MIPS design and complete the R2000 architecture.

circuitos digitales ii the general computer architecture the multicycle design semana no.10 semestre...

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