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Cadence schematic and layout of a CMOS inverter

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  • ENEE 640 | Spring 2015 Homework 1

    Ariyan M Kabir

    113412592

    CMOS Inverter Vout (red) & Vin (yellow) for m=1

  • CMOS Inverter Vout (red) & Vin (yellow) for m=2

  • CMOS Inverter Vout (red) & Vin (yellow) for m=3

    m Rise Time Fall Time

    1 13.53 E-10 4.713 E-10

    2 6.875 E-10 4.724 E-10

    3 4.60 E-10 4.737 E-10

    Observation

    The rise time decreases as 'm' increases.

    Explanation

    The factor 'm' is the multiplication factor for the width of PMOS. Increase in 'm' is increase in the width of

    PMOS. Which reduces the resistance of the device. Resistance is inversely proportional to the width of the

    transistor. As the mobility of PMOS is almost half the mobility of NMOS, therefore resistance drops

    significantly for PMOS than NMOS.

    As the resistance drops, higher current flows which charges the capacitances much faster. Therefore the rise

    time of the inverter decreases as 'm' increases.


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