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presented by John Coughlan RAL

FED Hardware Status

Pre-Series Manufacture

Final Production Plans

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FEDv2 Pre-SeriesQ3/2004 : Manufacture and commission first 2 FEDv2s. Both at CERN.

Q4/2004 : Prepare pre-series production of 25 FEDv2 boards.Final tests of FEDv2 design:Fine tuning of Front-End analogue passive components. Change Rload = 62R (now verified on FEDv2).

Q1/2005 :Pre-series of 5 + 20 (to verify full VME crate operation and then deliver to LSA centres) 5 boards delivered to RAL during Tracker week Feb.

4 boards are good. (1 sent to CERN , 1 at Imperial)1 board traced damaged BGA sent back for rework

10 further boards arrived end of last week under test. 10 remaining boards expected this Friday.

Summary: Pre-series proceeding to original schedule.3 FEDv2s now at CERN. A few more could be sent before May.Larger deliveries after Full Crate Test.

FEDv1s

Upgrade FEDv1s (minor mod to be compatible with FEDv2, except no S-LINK).

2 boards returned in February upgraded and pass system tests.

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Full Crate Test at RAL

To verify operation ~ 16 FEDs. And later for production tests with slink/optical/ttc systems.

Received Rack (arranging for chiller)

TTC interface to FED Tester ready by Easter Software ready to test now

Additional Equipment still needed in April

2nd LHC 9U Crate & SBS Crate Controller adapter (PCI-X)

And will need (1+1) more crates for Assembly plant tests starting this summer

FED Tester Crate

+ FED Crate

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Other Items

Further soak tests of SLINK readout in extreme data rate conditions.

Finalised design of 6U VME SLINK Transition card this month. Making 6 off.

SLINK cables (see talk by Attila)

Several improvements to FED firmware ready needed for final CMS operation (updated Technical Document).

New unambiguous FED channel numbering scheme adopted (suggestion by Francois to match optical cabling)

Other equipment CAEN interfaces, 6U->9U adapters ?

TTC splitters, switch to single mode fibres ; switch to TTCci?

B904 preparations ?

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FED Final Production

Final Production Schedule

Q3/2004 : EU Tender for PCB & Assembly. Done.

Q4/2004 : Company selection (DDi Technologies Europe Ltd). Done.

Obtain Quotes including CMS custom Testing at Assembly plant. Done.

Q1/2005 : Submission to CERN Finance Committee. Not required.

Arrange procedures between CERN (on behalf of CMS FAs) and RAL. In progress.

Q2/2005 : Sign formal contract with DDi. Starts procurement. Meeting on 21st March.

Q3/2005 -> Q3/2006 : Manufacture 500 FEDs @ ~ 50 / month.

Fully test boards in UK. At Assembly Plant and at RAL.

Ship to CERN B904; re-test full crates and store until USC55 available.

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FED StatusCMS Tracker 9U FED Status.Last update on 14.03.2005 by John Coughlan

Serial Nr Type

Responsible

Last Known

LocationLast known

Holder

All Channels Working

First Delivered to CMS at CERN Comments Current Plans Assembly

Delivered to RAL

1 v1 Imperial Imperial G. Iles Unknown FE-FPGAs 2000 UK tests SAETech Jan-032 v1 CERN CERN F. Vasey Unknown Sep-04 FE-FPGAs 2000 ; FE analogue mods on Rload and capsAt CERN B14 for OptoRx/FE analogue testsSAETech Jan-03

3 v1 Pisa Pisa P. Verdini Yes Dec-03 LSA SAETech Jun-034 v1 RAL RAL I. Church Yes Used for Power tests. OptoRx post-fitted. RAL tests SAETech Jun-035 v1 RAL RAL I. Church Yes Nov-03 Readout problems reported. Upgraded to v2 firmware.Complete tests. Send back to CERN. SAETech Jun-03

6 v1 RAL RAL I. Church No Maybe usable. 2x FE FPGA's need replacing SAETech Oct-037 v1 RAL RAL I. Church No Maybe usable. BE FPGA needs replacing SAETech Oct-038 v1 RAL RAL I. Church No Beyond repair. Use for power tests. OptoRx removed. SAETech Oct-039 v1 RAL RAL I. Church No Beyond repair. Use for power tests. OptoRx removed. SAETech Oct-0310 v1 RAL RAL I. Church No Beyond repair. Use for power tests. OptoRx removed. SAETech Oct-0311 v1 RAL RAL I. Church No Beyond repair. Use for power tests. OptoRx removed. SAETech Oct-03

DDi PCB & Assembly12 v1 RAL RAL I. Church Yes reworked with Samsung QDRs RAL tests DDi Mar-0413 v1 RAL RAL I. Church Yes Mar-04 Readout problems reported. Upgraded to v2 firmware.Complete tests. Send back to CERN. DDi Mar-0414 v1 Pisa Pisa P. Verdini Yes Apr-04 Beam Tests 2004 LSA DDi Mar-0415 v1 CERN CERN J. Fulcher Yes May-04 Beam Tests 2004. CRack Tests. B186 DDi Mar-0416 v1 CERN CERN J. Fulcher No May-04 Beam Tests 2004. 1 channel with problem. Tracker DAQ tests. B598 DDi Mar-0417 v1 RAL RAL I. Church No 2 channels with analogue problems. Send to CERN DDi Mar-04

18 v2 RAL RAL I. Church Yes Feb-05 Tracker DAQ tests DDi Aug-0419 v2 Imperial Imperial G. Iles Yes Feb-05 Tracker DAQ tests DDi Aug-04

Pre-series batch of 520 v2 RAL RAL I. Church Yes Power reset glitches due to LM82 Acceptance tests DDi Jan-0521 v2 Imperial Imperial G. Iles Yes Acceptance tests DDi Jan-0522 v2 RAL RAL I. Church No 4 bad channels due to FE3 FPGA damaged At eXception for FPGA rework DDi Jan-0523 v2 RAL RAL I. Church Yes Acceptance tests DDi Jan-0524 v2 RAL RAL I. Church Yes Feb-05 Tracker DAQ tests DDi Jan-05

Pre-series batch of 2025 v2 RAL RAL I. Church Passes Boundary Scan Analogue Tests eXception Mar-0526 v2 RAL RAL I. Church Passes Boundary Scan Analogue Tests eXception Mar-0527 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0528 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0529 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0530 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0531 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0532 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0533 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-0534 v2 RAL RAL I. Church Boundary Scan tests eXception Mar-05

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FED web pages

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