com bi national circuit

8/4/2019 Com Bi National Circuit

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Combinational Circuits


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Combinational Components

A combinational circuit is a logic circuit whoseoutputs at any time are determined directlyand only from the present input combination.

It performs a specific information-processingoperation fully specified logically by a set ofBoolean functions


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Combinational Circuits

Block diagram of a combinational circuit


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Designing Combinational Circuits

In general we have to do following steps:

1. Problem description

2. Input/output of the circuit

3. Define truth table

4. Simplification for each output

5.

Draw the circuit


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Logic Diagram for Circuit Analysis

Sample Circuit


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Half-Adder (HA)

Most basic arithmetic operation is theaddition of 2 bits.

A combinational circuit that performs addition

of 2 bits.


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Half-Adder


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Implementation of Half Adder


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Full-Adder

A combinational circuit that performs theaddition of 3 bits is called a full adder (FA),which can be implemented by 2 half-adders

and an Or gate.


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Full-Adder


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Derivation of Carry

y)z(xxyC

y)xyz(xxyC

yzxzyxxyC

yzxz)yx(yC

yzxz)x(yC

yzxxzxyC

y)xz(xxyC

y)z(xxyCy)z(xxyyzxzxyC


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Binary Parallel Adder

For example to add A= 1011 and B= 0011

subscript i: 3 2 1 0

Input carry: 0 1 1 0 CiAugend: 1 0 1 1 Ai

Addend: 0 0 1 1 Bi

--------------------------------

Sum: 1 1 1 0 Si

Output carry: 0 0 1 1 Ci+1


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Binary adder that produces the arithmeticsum of binary numbers can be constructedwith full adders connected in cascade, with

the output carry from each full adderconnected to the input carry of the next fulladder in the chain


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Note that the input carry C0 in the leastsignificant position must be 0.


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Binary Subtractor

The subtraction A B can be done by:

Designing a Half subtractors, and Full-subtractors;

or

Taking the 2s complement of B and adding it to A

because A- B = A + (-B)


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Design of Half and Full subtractors


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Binary Subtractor (2s complement)

The subtraction AB can be done by taking the 2scomplement of B and adding it to A because A- B =A + (-B)

It means if we use the inventers to make 1s

complement of B (connecting each Bi to an inverter)

and then add 1 to the least significant bit (by settingcarry C0 to 1) of binary adder, then we can make abinary subtractor.


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4 bit - 2s complement Subtractor

= 1


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Adder/Subtractor Circuit

Can be combined into one circuit with onecommon binary adder.

Mode M controls the operation. When M=0

the circuit is an adder when M=1 the circuit issubtractor. It can be done by using exclusive-OR for each Bi and M.

Note: 1x = x (subtract) and0x = x (add)


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Note:S input is the M mode controller


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Magnitude Comparator

It is a combinational circuit that compares twonumbers and determines their relative magnitude

The output of comparator is usually 3 binaryvariables indicating: A>B

A=B

A


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Comparators For a 2-bit comparator we have four inputs A1A0 and B1B0

and three outputs

E =1 if two numbers are equal, G = 1 when A > B, and

L = 1 when A < B). If we use truth table and KMAP the resultis:

E=(( A0

B0) + ( A1

B1)) G = A1B1 + A0B1B0 + A1A0B0

L= A1B1 + A1A0B0 + A0B1B0

Comparator

A0

A1

B0

B1

E

G

L


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Magnitude Comparator (A=B)

Here we use simpler method to find E (called X) and G (called Y) and L(called Z)

A = B, if all Ai= BiAi Bi Xi X1 X0------------0 0 1 A = A1 A00 1 0 B = B1 B01 0 01 1 1

It means X0 = A0B0 + A0B0 and X1= A1B1 + A1B1If X0 = 1 and X1 = 1 then A0 = B0 and A1=B1

Thus, if A = B then X0X1 = 1 it meansX= (A0B0 + A0B0)(A1B1 + A1B1)

Since (xy) = (xy +xy)

Then, X= ( A0B0) ( A1B1) = (( A0B0) + ( A1B1))


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Magnitude Comparator (A > B)

A > B if Ai Bi Xi

------------

0 0 0

0 1 0

1 0 11 1 0

Ai>Bi or

A1 = B1 and A0 >B0 Therefore: For A> B: A1 > B1 or A1=B1 and A0 >

B0

Means: Y= A1B1 + X1A0B0 should be 1


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Magnitude Comparator (A < B)

For A


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4-bit Magnitude Comparator


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Sample Problem #1

Design a combinatorial circuit that converts the 4-bit

BCD code to Excess-3 code.

Input BCD Output Excess-3

A B C D w x y z

0 0 0 00 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

0 0 1 10 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

Note:

The other inputcombinations have dont

care states.


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CD 00 01 11 10AB

00

01

11

10

1 1

1 1

X X X X

1 X X

CD 00 01 11 10AB

00

01

11

10

1 1

1 1

X X X X

1 X X

CD 00 01 11 10AB

00

01

11

10

1 1 1

1

X X X X

1 X X

CD 00 01 11 10AB

00

01

11

10

1 1 1X X X X

1 1 X x

z = D y = CD + CD

x = BC + BD + BCD w = A + BC + BD

Drawthecircuit

Z101

01010

10

Y100

11001

10X

011110000

1

W000001111

1


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Sample Problem #2

A combinational circuit has four inputs andone output. The output is equal to 1 when (a)all the inputs are equal to 1 or (b) none of the

inputs are equal to 1 or (c) an odd number ofinputs are equal to 1.

Obtain the truth table

Find the simplified output function

Draw the logic diagram


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Sample Problem #3

Design a combinational circuit whose outputis HIGH only when a majority of inputs A, B,and C are LOW.


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Seven segment decoder

Generates the outputs for selection ofsegments in a display indicator used fordisplaying the decimal digit

Has seven inputs as shown.


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BCD-to-7 segment decoder

Combinational circuit that accepts a decimaldigit in BCD and generates the appropriateoutputs for selection of segments in a display

indicator used for displaying the decimal digit.The numeric designation chosen to representthe decimal digit is shown. Design the BCD-to-seven segment decoder circuit.


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7-segment decoder

a

b

c

d

e

f

g

w x y z a b c d e f g Number0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1


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Exercises

1. Design a combinational circuit that acceptsa three-bit number and generates a binarynumber output equal to the square of the

input number.

2. Design a combinational circuit whose inputis a three-bit number and whose output is

the 2s complement of the input number.


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Combinational Logic

with MSI and LSI


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Decoder

A combinational circuit that converts binary information from ninput linesto a maximum of 2nunique output lines. Can beimplemented with And gates.

For example if the number of input is n = 3 the number of outputlines can be m = 23. It is also known as 1 of 8 because one

output line is selected out of 8 available lines:

3 to 8decoder

enable

Z

Y

X

D0

D1D2

D3

D4D5

D6

D7


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Decoder

With 4 input lines, there are 24 =16 outputs. With 5 input lines, there are 25 =32 outputs.

With 9 input lines, there are 29 =512 outputs.

With 10 input lines, there are 210

=1024 outputs.

9 to 512decoder

enable

X0

: :: :: :

X8

D0

: :: :: :: :

D511


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3 to 8 Line decoder (Truth Table)

X Y Z D7 D6 D5 D4 D3 D2 D1 D0-------------------------------------------------------0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0


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Decoder with Enable Line

Decoders usually have an enable line,

If enable=0 , decoder is off. It means all

output lines are zero If enable=1, decoder is on and

depending on input, the corresponding

output line is 1, all other lines are 0


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Truth table for 3 x 8 decoder w/ Enable

E X Y Z D7 D6 D5 D4 D3 D2 D1 D0-----------------------------------------------------------0 x x x 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 01 0 1 0 0 0 0 0 0 1 0 01 .1 .....

11 1 1 0 0 1 0 0 0 0 0 01 1 1 1 1 0 0 0 0 0 0 0


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Major application of Decoder

Decoder is used to implement any combinational circuits ( fn )

For example the truth table for full adder is S(x,y,z) = (1,2,4,7)and C(x,y,z)= (3,5,6,7). The implementation with decoder is:


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Sample Problem #1

1. A combinational circuit is defined by the ff.two functions:

F1(x,y) = (0,3)

F2(x,y) = (1,2,3)

Implement the combinational circuit bymeans of the decoder.


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Sample Problem #2

2. A combinational circuit is defined by the ff.three functions:

F1 = xy + xyz

F2 = x + y

F3 = xy + xy

Design the circuit with a decoder and

external gates.


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Encoder

Encoder is a digital circuit that performs the reverse

operation of a decoder Generates a unique binary code from several input

lines.

Generally encoders produce 2-bit, 3-bit or 4-bit code.

n bit encoder has 2n input lines

2 bit encoder


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2-bit Encoder (Truth Table)

D3 D2 D1 D0 X Y----------------------------------

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

X = D2 + D3

Y = D1 + D3


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2-bit Encoder Circuit


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2-bit Encoder

If one of the four input lines is active encoderproduces the binary code corresponding tothat line

If more than one of the input lines will beactivated or all the output is undefined. Wecan consider dont care for these situations

but in general we can solve this problem byusing priority encoder.


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Multiplexer

A combinational circuit that selects binaryinformation from one of the input lines and directsit to a single output line. Also called Selector.(MUX)

There are 2n input lines and n selection lineswhose bit combinations determine which inputline is selected

For example:2-to-1 MUX. If selection S =0 thenI0 has the path to output and if S =1 then I1 hasthe path to output.


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2-to-1 multiplexer


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4 x 1MUX

B l f i I l i


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Boolean function Implementation

Another method for implementing Booleanfunction is by using MUX.

For doing that assume Boolean function has nvariables. We have to use multiplexer with n-1selection lines and

1- first n-1 variables of function is used for datainput

2- the remaining single variable ( named z )is usedfor data input. Each data input can be z, z, 1 or 0.

From truth table we have to find the relation of Fand z to be able to design input lines. For example: f(x,y,z) = (1,2,6,7)


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MUX P bl #1


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MUX Problem #1

Given the ff. Boolean function F, construct acombinational circuit that uses MUX.

F(A,B,C) = (1,3,5,6)

A B C F--------------------0 0 0 0 F = C0 0 1 10 1 0 0 F = C

0 1 1 11 0 0 0 F = C1 0 1 11 1 0 1 F = C1 1 1 0

MUX P bl #2


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F (A,B,C,D) = (1,3,4,11,12,13,14,15)

MUX Problem #2

U MULTIPLEXER


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Usage:MULTIPLEXER

Helps share a single communication line among anumber of devices.

At anytime, only one source and one destination canuse the communication line.

LARGE MULTIPLEXER


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LARGE MULTIPLEXER

Large multiplexer can be built from smallermultiplexer

8:1 multiplexer can be built from smaller multiplexerlike this:

LARGE MULTIPLEXER


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LARGE MULTIPLEXER

Other example the building of 8:1 multiplexer fromsmaller multiplexer

D l i l


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Demultiplexers

A decoder with an enable (E) input is alsocalled a demultiplexer (DMUX or DEMUX).

A circuit that receives information on a single

line and transmits this to one of the 2npossible output lines. The selection of theoutput line is controlled by the bit values of nselection lines.

2 4 D d i h E bl (E)


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2 to 4 Decoder with Enable (E)

C i


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Comparison

Decoder with EnableDemultiplexer

D d /d MUX


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Decoder/deMUX

Circuits can be connected together to form alarger decoder circuit.

Example:

Construct a 4 x 16 decoder out of 3 x 8decoders with enable inputs.

Inputs : 3 + 1 (add one 3 x 8 decoder)

Outputs: 8 x 2 ( 2 decoders needed) = 16

4 16 D d


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4 x 16 Decoder

When E = 0, the topdecoder is enabledand the other is

disabled.

When E = 1, thebottom decoder is

enabled and theother is disabled.

D d C t ti P bl


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Decoder Construction Problem

Construct a 5 x 32 decoder with four 3 x 8decoder/deMUX and a 2 x 4 decoder.

Thri St t G t


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Thri-State Gates

Thri-state gates exhibit three states instead of twostates. The three states are:

High : 1

Low : 0

High impedance

n High impedance that state the output isdisconnected which is equal to open circuit. In otherwords the circuit has no logic significance. We can

have AND or NAND tree-state gates but the mostcommon is thri-state buffer gate

Thri St te G tes


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Thri-State Gates

We may use conventional gates such asAND or NAND as tri-state gates but the mostcommon is thri-state buffer gate.

Note that buffer produces transfer functionand can be used for power amplification. Thristate buffer has extra input control lineentering the bottom of the gate symbol (seenext slide)

Three-state buffer


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Three-state buffer

C A Y

----------------------0 0 z0 1 z1 0 0

1 1 1


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Three-state buffers can be used to implementmultiplexer

com bi national circuit

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