convolution final slides
TRANSCRIPT
Presented By :D.Ramu (09605A0401)M.Sirisha (08601A0471)
P.Ramya Sree (08601A0497)
EFFICIENT FPGA IMPLEMENTATION OF
CONVOLUTION
Under the Esteemed Guidance of
Mr. S.Nagireddy
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INTRODUCTION
Reduces convolution processing time using hardware
computing
Implements discrete linear convolution of two finite
length sequences (N x N)
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EXISTING SYSTEM
Convolution is implemented using DSP processor Chips
Consumes more PowerRequires more Chip Area Low Speed
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PROPOSED SYSTEM
Convolution is implemented using VLSI Architechture
Consumes less PowerRequires less Chip Area High SpeedExtended for Signed and Unsigned Nos.Reduces Processing time
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PURPOSE
Proves the feasibility of an application specific integrated circuit (ASIC)
Digital images can be modified using Point wise operations
Image processing operations
Provides great significance in discrete signal processing
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PROJECT OVERVIEW
Identify the Architecture From the literature survey
Model the Architecture into RTL [Register Transfer Level]modeling
Verify the functionality of Modeled architecture in MODELSIM®
Synthesis the verified design in Xilinx ISE
Generation of Bit map file for Dump into Spartan 3E FPGA
Program the Bit map file into FPGA.
Post simulation in ChipScope pro.
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ADDITIVE PORTION OF LINEAR PROPERTY
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LINEAR CONVOLUTIONImpulse response
Shifted version of the input signal
Scaling aspect of linearity of the system
Additive aspect of linearity of the system.
= y(t) 8
BLOCK DIAGRAM
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Multiplexer Multiplexer referred to as “multiplexor” or “mux”
MUX contains
2n Inputs lines
n Select lines
1 Output line
Working of MUX:
Selects any one of the inputs from 2n inputs
Directs to the output depending on n-select lines.
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Each input is 4-bit signed form
Each output is also a 4-bit signed form
Convolution design uses two 4*1 Multiplexers
Multiplexer 4*1
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Multiplexers 4*1
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Serial in parallel out block(SIPO)
SIPO converts serial input into parallel output Each serial input will be in a 4-bit signed form
Working of SIPO
Takes SIN(0 to 3) as a input Produces four parallel outputs Q0,Q1,Q2,Q3 Each parallel output will be in a 4-bit signed form
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Serial In Parallel Out Registers
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Binary multiplier
It is a 4-bit multiplier
Takes two four inputs
Each input is 4-bit signed form and gives an 8-bit output
Special Characteristic of Binary multiplier:
Internal carry will not be forwarded to next stage
So,number of outputs obtained here is seven only
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Binary Multiplier
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Multiplexer 8*1
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Register A Register is a group of flip-flops
It holds information within a digital system
The logic units get access to the Info during the
computing process
It may have combinational gates that perform certain
data-processing tasks.
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Register
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FPGA DESIGN FLOW
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4-INPUT LUT BASED IMPLEMENTATION OF LOGIC BLOCK
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ADVANTAGES
The advantages of convolution by proposed architecture
has following advantages:
Reduce area
Reduce Power
More speed
No data loss
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Simulation ResultsConvolution Top Level
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Multiplexers
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Serial In Parallel Out Registers
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Binary Multiplier
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Multiplexer 8*1
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Register
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Synthesis ResultsRTL Schematic View
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RTL Internal View
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APPLICATIONS Digital image processing(Frequency Filtering)
Real-time signal processing like:
Audio signal processing
Video / Image processing
Large-capacity data processing
In Linear Acoustics
In statistics
In Probability theory
In Optics(The “Blur” is described by Optics) 31
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CONCLUSION Optimized implementation of Discrete Linear
Convolution. Uses the mean squared error measurement and
objective measures of enhancement to achieve a more effective signal processing model and accuracy
The proposed circuit uses only 5mw and saves almost 35% area and it takes 20ns to complete. This shows improvement of more than 50% less power.
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FUTURE SCOPE Extracting a periodic signal from noise. Software Applications: GUI Module. Echo Detection in Linear acoustics. Speech Analysis and pitch. In time-resolved Fluorescense Spectroscopy In Radiotherapy treatment planning systems , most
part of all modern codes can use convolution.
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Thank You
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QUERIES??
QUERIES??
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