cost effective reconfigurable logic

7/28/2019 Cost Effective Reconfigurable Logic

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Cost Effective Reconfigurable Logic

Final Project Report

Presented to

The Faculty of the Department of

General Engineering

San Jose State University

April 23, 2010

By

Piyush Patel (005810493)

Ipsita Praharaj (003819596)

Nagendra Donepudi (005783986)

Committee Members

Industrial Advisor

Dr. Love Singhal

Sr. Member of Technical Staff, Synopsys Inc.

University Reader

Professor Morris Jones

Electrical Engineering Department


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2010

Piyush PatelIpsita Praharaj

Nagendra Donepudi

ALL RIGHTS RESERVED


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APPROVED FOR THE DEPARTMENT OF GENERAL ENGINEERING

_________________________________________________________Professor Morris Jones, Department of Electrical Engineering


____________________________________________________________Dr. Love Singhal

Senior Member of Technical Staff, Synopsys, Inc. Mountain View, CA

____________________________________________________________Dr. Ali Zargar.

Graduate Coordinator, Department of Aviation and Technology



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ABSTRACT

In the current digital era, the demand for the new electronic device is increasing in a high pace

while the designers and manufacturers are trying their best to provide cheaper solutions in order

to satisfy the consumers requirement. The main goal of this project is to develop a methodology

to replace the high cost FPGA chip by cheaper microcontroller circuit to make it cost effective.

The project's objective is to identify the real time low power applications which employs FPGA

chip for its operation to replace it by cheaper microcontroller by achieving a frequency of 1 GHz.

This report basically explains, how to design the workflow of converting verilog language to 'C'

programming language and then design the microcontroller as per the specification in order to

achieve the goal. The methodology and the technical specifications are included in the report.

Market research, business case analysis, and economic analysis provided very useful feedback

about the current market and helped to conclude that this project has plenty of business potential

and capability of being milestone in embedded world.


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ACKNOWLEDGEMENT

We would like to express our sincere gratitude to Professor. Morris Jones, Part-Time Assistant

Professor, Dept. of Electrical Engineering, San Jose State University for his guidance and

support for this project.

We would like to sincerely thank Dr. Love Singhal, Senior Member of Technical Staff, Synopsys

Inc. for his guidance for this project.

We would like to express our deep gratitude to Dr. Ali Zargar, Graduate Coordinator, Dept. of

Aviation and Technology, San Jose State University for giving us an opportunity to enroll in

ENGR 281 course under his guidance and recommendations.

Piyush Patel

Ipsita Praharaj

Nagendra Donepudi


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Table of Contents

1

Introduction ............................................................................................................................. 1

2 Background ............................................................................................................................. 22.1 Microcontrollers ............................................................................................................... 32.2 FPGA ................................................................................................................................ 5

3 Experimental Procedure .......................................................................................................... 84 Resources Utilized .................................................................................................................. 8

4.1 Software requirement ....................................................................................................... 94.2 Hardware requirement (If we implement practical design) ............................................. 9

5 Applications ............................................................................................................................ 96 Preliminary Literature Review ................................................................................................ 9

6.1 Literature Review of Microcontroller ............................................................................ 106.2

Literature Review of FPGA ........................................................................................... 11

7 Technical details of the Project ............................................................................................. 13

7.1 System Design methodology .......................................................................................... 137.1.1 Fist phase :( Verilog to 'C' language Conversation process) .................................. 14 7.1.2 ANTLR Workflow .................................................................................................. 157.1.3 Architecture of ANTLR compiler ........................................................................... 17

7.2 Second phase: Design and Implementation of Microcontroller ..................................... 217.2.1 Microcontroller design flow ................................................................................... 217.2.2 System Architecture ................................................................................................ 23

8 Economic Justification .......................................................................................................... 298.1 Executive summary ........................................................................................................ 298.2

Problem Statement ......................................................................................................... 29

8.3 Solution and Value proposition ...................................................................................... 308.4 Market size ..................................................................................................................... 308.5 Competitors .................................................................................................................... 318.6 Customers ....................................................................................................................... 328.7 Cost summary ................................................................................................................. 33

8.7.1 Fixed cost ................................................................................................................ 338.7.2 Employee Wages .................................................................................................... 348.7.3 Variable cost ........................................................................................................... 34

8.8 Price Point ...................................................................................................................... 358.9 SWOT Assessment ......................................................................................................... 368.10 Investment Capital Requirement ................................................................................ 378.11 Personnel .................................................................................................................... 378.12 Business and Revenue Model ..................................................................................... 388.13 Strategic Alliance/Partners ......................................................................................... 388.14 Profit/Loss .................................................................................................................. 398.15 Breakeven Analysis .................................................................................................... 408.16 Return on Investment (ROI) ....................................................................................... 418.17 Exit Strategy ............................................................................................................... 42


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9 Project Schedule.................................................................................................................... 4210 Conclusion ............................................................................................................................ 4211 Future Work .......................................................................................................................... 4312 List Of References: ............................................................................................................... 4413 APPENDIX A ....................................................................................................................... 4914

APPENDIX B ....................................................................................................................... 50

15 APPENDIX C ....................................................................................................................... 5316 APPENDIX D ....................................................................................................................... 7317 APPENDIX E ....................................................................................................................... 7618 APPENDIX F........................................................................................................................ 91

List of Figures

Figure 1: Microcontroller in FPGA graph ...................................................................................... 2Figure 2: Basic Architecture of Microcontroller ............................................................................ 4Figure 3: (a) Basic architecture of FPGA (b) Basic architecture of logic block............................. 6

Figure 4: Evolution of FPGA Architectures ................................................................................... 7Figure 5: Technology vs. Design cost........................................................................................... 12Figure 6: High-level process flow of the project design ............................................................... 14Figure 7: Overall translation data ................................................................................................. 16Figure 8: Architecture of ANTLR compiler module .................................................................... 18Figure 9: AST generated by ANTLR............................................................................................ 19Figure 10: Close up view of AST ................................................................................................. 20Figure 11: Microcontroller design flow ........................................................................................ 22Figure 12: Microcontroller Architecture ....................................................................................... 24Figure 13: Decision box block diagram ........................................................................................ 28Figure 14: Market Scale forecast for Microcontrollers................................................................. 30Figure 15: Worldwide Processor Market In 2010......................................................................... 31Figure 16: Profit/Loss graph ......................................................................................................... 40Figure 17: Break Even Analysis Graph ........................................................................................ 41 Figure 18: Project Schedule .......................................................................................................... 42

List of Tables

Table 1: Instruction Set ................................................................................................................. 25Table 2: Mode Conditions ............................................................................................................ 25Table 3: Opcodes .......................................................................................................................... 26Table 4: Fixed Cost ....................................................................................................................... 33Table 5: Employee Wages ............................................................................................................ 34Table 6: Variable Cost .................................................................................................................. 34Table 7: Estimated cost for 100K units ......................................................................................... 35Table 8: SWOT assessment .......................................................................................................... 36Table 9: Human Resources ........................................................................................................... 38Table 10: Profit/Loss..................................................................................................................... 39


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1 Introduction

In todays technology world, microcontroller is playing an important role which is the most used

component in all kinds of digital electronic component. Its applications vary from simple

household electronics to complex aerospace systems. Currently, hardware engineers and chip

designers are working hard to improve the key areas of microcontroller like functionality,

performance, clock speed, shorter time to market, and reduced Bill of Material (BOM). The

single chip of microcontroller used for storing and processing of the data and events in the logic

block of an integrated circuit. The highly integrated processor can be used as stand alone device.

The compact size, low cost, and simplicity of the microcontroller circuit make it extremely

famous in the digital market and a significant number of microcontroller applications are

designed and developed to satisfy the consumer requirements. The objective of this project is to

develop a solution to replicate the operations done by high speed Field Programmable Gate

Array (FPGA) chip by low power microcontroller circuit. FPGA is usually being used when high

performance computing applications like digital signal processing, image processing, high speed

communication and high speed data transfer is involved. The FPGA provides considerably good

computational throughput even at a low clock rates because it employs parallelism in its

operation (Field Programmable Gate Array, 2009). Many of the applications dont require the

high speed performance which FPGA proffers. Those applications are targeted and the FPGA

can be replaced by the redesigned microcontroller which can employ the same operations by

using assembly code as a programming language. These redesigned microcontrollers can reduce

the cost of product with a big architecture of microcontroller using latest fabrications technology

and then convert the verilog code to C code and C code to assembly code for existing

applications employed by FPGA.


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Figure 1: Microcontroller in FPGA graph

Figure 1 shows the graph of the FPGA with respect to cost and Features. From the graph it is

clear that as the number of features in the FPGA increase the price also rises. With this modified

microcontroller design we will able to develop a microcontroller that provides all the features of

the FPGA at lower cost. If the microcontroller is plotted in the FPGA graph it would appear as

shown in Figure 1. It provides all the features of the low end FPGA at a lower price.

2 Background

Microcontrollers and FPGAs are introduced and are being widely used over the past 10-15 years.

The project is to develop a methodology to replace the FPGA by microcontroller. Before

designing or developing, it is important to first understand the present technology, architecture,

and design of the existing microcontroller and the FPGA. An extensive research was performed

over a wide range of resources to understand the basic architecture, design, and different

Cost

Fast

Features

SlowMicrocontroller

FPGA graph


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components of microcontroller and FPGA. The background of the basic architecture of

microcontroller and FPGA are described below.

2.1 MicrocontrollersMicrocontroller is a small computer inside a single chip. It is basically a programmable chip

invented in 1970s. This device is most widely used in automotive products. Initially the

microcontrollers were developed using TTL (Transistor-Transistor Logic) technology which are

having CMOS (Complementary Metal-Oxide-Semiconductor) technology at present. Currently,

microcontrollers are very popular due to its functionality, simplicity, low power consumption,

easy programmability, and low cost. The basic components of microcontroller are CPU (Central

Processing Unit), Data bus, Timers, Interrupts, ROM (Read Only Memory), I/O (Input Output)

unit, RAM (Random Access Memory). In the current market, many kinds of microcontrollers are

available with other components in them to perform special errands like USB port, Ethernet port,

Bluetooth port, external memory slot, Analog to Digital converter etc. The basic architecture of

microcontroller is shown in Figure 2. Some basic components of microcontroller are explained

below.

CPU (Central Processing Unit): The CPU is the brain of processor which is responsible for

controlling all other units inside the controller. All modules inside processors are connected to

CPU and it is responsible to manage the functions of other units, input/output data, and various

processes on data, computation and logic performance.

Data Bus: It is the medium through which the data moves from one module to another module.


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Figure 2: Basic Architecture of Microcontroller

Source:What is Microcontroller? Retrieved on 27 September, 2009 from

http://o.mneina.googlepages.com/what_is_microcontroller.htm

Input/output unit: This unit is responsible to take the data in and give the resultant data out.

The input unit collects the data from external environment and makes it available tomodules to

perform functions. The output unit collects computed data and gives as resultant data.

RAM and ROM: RAM (Random access memory) and ROM (Read only memory) are memory

units to store the data temporary or permanently.

Timers: The timers are responsible to make the processor functions real time. In the processor

more than one timer may be also available for specific purpose. Modifications of the basic

architecture of microcontrollers can solve many technical problems. Now industries are

approaching to change the architecture of microcontrollers as per their requirement and many of

researchers and developers prefers to do advancement in the microcontrollers design.


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2.2 FPGAFPGA is one of the revolutionary inventions in the field of the semiconductor industry. The first

FPGA was XC2064, introduced in 1984 by Ross Freeman, Co-founder of Xilinx Inc. It had 800

gates in it and was manufactured using 2.0u process technology. As the technology continued to

become popular, FPGA has undergone a tremendous amount of changes with respect to

architecture, process technology, and complexity. Additional components were included in the

FPGA to improve the functionality and complexity. Figure 3 shows the basic architecture of

FPGA.

The basic FPGA architecture include three main components such as programmable interconnect,

logic blocks, and configurable I/O blocks. It also contain additional logic components like

decoders, ALUs, memory and programmable elements like static RAM and EPROM are

included in the FPGA architecture. A clock circuit decides the speed at which the FPGA works.

Configurable Logic Blocks (CLBs): All the FPGAs have small logic components which can be

programmed called logic blocks. The logic blocks can be programmed and configured to

implement complex logic functions.


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Figure 3: (a) Basic architecture of FPGA (b) Basic architecture of logic block

Source: Ma Xiaojun; Tong Jiarong; Design and Implementation of a New FPGA

Architecture, 21 Oct, 2003. 2, 816 819. Retrieved on 1 October, 2009 from

http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=127733

5&isnumber=28525

Configurable I/O blocks: The configurable I/O blocks on FPGA are used to get the inputs and

send the outputs. Pull up and pull down registers are included and are used to terminate signals.

Programmable Interconnect: A set of long wires are used to connect the critical logic blocks

which are far from each other. Logic blocks which are nearer to each other are connected with

short wires. To turn on and off the connections between the lines transistors are used in the form

of switches.


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As the technology developed and the speed of the applications increased, the architecture of

FPGA experienced some major changes. The graph in Figure 4, published in a press conference

by Xilinx Inc. provides a brief overview of the changes made in FPGAs over the past 20 years.

Figure 4: Evolution of FPGA Architectures

Source: Revolutionary Architecture for the Next Generation Platform FPGAs, Xilinx.

Xilinx press release, December 8, 2003, retrieved on 5 October, 2009 from

http://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf

Even though the FPGA has under gone major changes in the past 20 years, the price and the

power consumption of the FPGA remained high when compared to ASIC(Application Specific

Integrated Circuit)chips.


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4.1 Software requirement ANTLR Parser generator to convert the verilog code to convert into C code Modelsim Simulator tool for verilog code simulation Linux Open Source as C code compiler (gcc compiler)

4.2 Hardware requirement (If we implement practical design) FPGA circuit board (Altera or Xilings) Microcontroller IC

5 Applications

The low power real time applications are identified which uses FPGA chip and can be replaced

by microcontroller. Those are mentioned below.

Home based portable medical device like Insulin pump Low power mixed-signal FPGAs in employed in Hemodialysis machine LCD panels of digital cameras, personal digital assistants (PDA), and handheld devices,

Touch screen controller

In storage device such as memory stick which are used for portable devices like digitalcamera, PDAs, digital music players

6 Preliminary Literature Review

We have reviewed considerable publication like IEEE journals, white papers, online newsletters,

and publications of pertinent organizations to discover current technology trends, market

behavior, and significant methodologies about our hypothesis. We have analyzed the IEEE


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journals and publications of applicable organizations to know more about the advancement in the

architecture of a FPGA chip as well as the microcontroller and regarding the real time operations

carried out by a FPGA chip that need to be replaced by microcontroller circuit. We have

investigated regarding the current market share of FPGA and microcontrollers for automotive

products. We also carried out the economic analysis for FPGA and microcontroller to understand

future inclination of automotive world. We have focused on entire premise of our project to get

the information for justifications of our project scope during literature survey.

6.1 Literature Review of MicrocontrollerWe analyzed the fact that, the compiler architecture, multithread programming model,

reconfigurable computing by hardware and software hybrid model etc will be the future trends.

Performance of processor can be increased using reconfigurable microcontroller array which is

applicable for applications like high speed data handling, image processing, and pattern

reorganization.

An IEEE paper about Survey on microprocessor architecture and development trends was

published by Yao Yingbiao; Zhang Jianwu; and Zhao Danying on November, 2008 in 11th

IEEE

international conference of Communication technology where authors talked about the future

requirements of new amendments in microcontroller architecture. These new architectures can

resolve the problems of workload parallelism, speed mismatch problems, and overall recital

(Survey on microprocessor architecture and development trends, 2008).

One of the IEEE paper published by Maslennikov, O.; Shevtshenko, J.; Sergyienko, A.; about

Configurable microcontroller array on September 2002 in the international conference on

parallel computing in electrical engineering. In this paper authors have suggested a

reconfigurable microcontroller array fori8051 processor. In this paper they have suggested


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implementation of reconfigurable computing. They justified their proposal by showing detailed

work about this new methodology. Authors also showed how the performance of processor can

be speed up by this technique which can be useful for such applications like high speed data

handling, image processing, and pattern reorganization (Configurable microcontroller array ,

2002).

The authors Golbert A. and Israel I. mentioned about latest trend in microcontrollers

architectures by publishing an IEEE paper about Trends in microprocessor cache architectures

in the 17th Convention of Electrical and Electronics Engineers in Israel on March, 1991. They

explained the initial architecture of processors and then concluded that the cache memory

architecture is requirement of future. They also suggested developing the external cache

architecture for some designs as per requirements (Trends in microprocessor cache architectures,

1991).

According to IEEE paper Design of an 8 bit general purpose microcontroller with sea-of-gates

design style published by Nalan Erdas and Mustafa Gunduzalp in the eleventh international

conference on 22-24 November, 1999 is discussing about increasing the capabilities and

reliability of microcontrollers and the electronic component size should be minimized. The

modification in basic execution style of microcontroller is also necessary (Design of an 8 bit

general purpose microcontroller with sea-of-gates design style, 1999).

6.2 Literature Review of FPGAFPGAs are typically less efficient due to the overhead on the device for the configuration

circuitry, including I/O and the SRAM cells required to hold the current design. This leads to

larger device sizes and larger power consumption. While it is getting easier all the time, it is


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still true that developing any system on an FPGA usually requires some savvy when it comes to

digital design.

Even though the FPGA has under gone major changes in the past 20 years, the price and the

power consumption of the FPGA remained high when compared to other non FPGA chips.

A presentation on Low Power FPGAs A New Era was given by Rich Kapusta, Vice

President, Marketing & Business Development, Actel Corporation. In this presentation the

speaker clearly explains the problems faced by todays semiconductor industries. He explains the

increase in the cost of designing as the process technology develops (Low Power FPGAs A

New Era, 2009).

Figure 5: Technology vs. Design costSource: Low Power FPGAs A New Era, Rich Kapusta, Vice President,

Marketing & Business Development, Actel Corporation. Retrieved on 1 October,

2009 from http://www.actel.com/company/events/default.aspx

In a recent article on FPGA architectural power-saving techniques at 40 nm by Seyi Verma,

Altera Corp, the author gives a theoretical description on how the power consumption of FPGA

can be reduced using the 40nm process technology. In this article the author describes that the

40nm process technology offers more benefits when compared to 45nm and 65nm process

technology (FPGA architectural power-saving techniques at 40 nm, 2008).


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In an IEEE paper by W. James MacLean on An Evaluation of the Suitability of FPGAs for

Embedded Vision Systems presented at 2005 IEEE Computer Society Conference on Computer

Vision and Pattern Recognition, the author describes some of the major disadvantages on FPGAs.

The author states that FPGAs are typically less efficient due to the overhead on the device for

the configuration circuitry, including I/O and the SRAM cells required to hold the current design.

This leads to larger device sizes and larger power consumption. The author also describes that

the designers of the FPGA need to have a complete knowledge and understanding about clock

signals, flip-flops, FIFOs and propagation delay. He states that the software designers need know

about the target platform the software is going to be used. He also describes that the designers of

the FPGA need to have a good idea about the architecture of the Adders and Multipliers (An

Evaluation of the Suitability of FPGAs for Embedded Vision Systems, 2005).

7 Technical details of the Project

To design and implement the workflow of converting verilog to 'C' code and then design the

microcontroller involves the following technical specification. The project is divided into two

phases. In the first part, ANTLR parser is used to convert verilog HDL to C language. In the

second phase, microcontroller is designed using the required specification in order to mimic the

functionality of FPGA chip.

7.1 System Design methodologyThe design of this project took place in different phases. The basic flow chart is given in

Figure 6 below. This is the high level process flow of the design shown in Figure 6.


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Figure 6: High-level process flow of the project design

7.1.1 Fist phase :( Verilog to 'C' language Conversation process)

ANTLR parser is used for the language conversion purpose. It can generates a program, then by

adding codes to the grammar file, the code parser becomes a translator. It converts behavioral

verilog code to 'C' code and the resultant code can be compiled using open source gcc compiler.

There are several reasons behind choosing ANTLR passer for this purpose which are described

below.

ANTLR parser is a platform independent parser and can works in Window, Linux, andMac operating systems. It basically has a Java based IDE(Integrated Development


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Environment) that can support data structure like structure, tree walking, and error

recovery

Very reliable, automates tasks, supports multiple languages like Java, C#, python,objective C, C etc.

ANTLR is easier to understand and use than other parser generators. ANTLR is used to build interpreters for domain specific languages which are high level

languages to be used

ANTLR has a good user friendly GUI development environment to produce ANTLRversion3 grammars and it contains all the jar files are needed for the application

ANTLR v3 has many different kinds of run time liberalities to support different kinds oflanguage like Java, C, C++, python,C#, PERL, ActionScripts, and JavaScript

The verilog grammar can be parsed in eclipse IDE in order to support the verilog HDLlanguage

The tool can generate AST(Abstract Syntax Tree) out of the verilog module when theverilog grammar file is plug in into the IDE

7.1.2 ANTLR Workflow

A translator's job is to map the input of one language to an output of other language. To

complete mapping, the translator parses user provided codes. The translator can translates in two

phages, first phase is lexical analysis. The second phage is known as parsing that parse

symbols. ANTLR tool automatically generate lexer and parser by analyzing the grammar. This

is shown in Figure 7.


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The intermediate structure is a tree data structure called AST(Abstract Syntax Tree). The final

output provides structure using all the data structure from previous inputs. The lexer's work is

to break the input language into tokens. The parser can parse tokens to understand the input

structures. ANTLR has a GUI grammar environment to help edit, compile, and, debug grammars.

The method of translating verilog HDL to its equivalent 'C' coding is parsing a verilog pattern in

a verilog file and substituting the verilog code with a 'C' language. It helps to debug grammar

analysis errors. The GUI development environment has following features.

1. Grammar-aware editor

2. Abstract Syntax diagram grammar

3. Dynamic parse tree view

4. Dynamic AST view

out utLexer

symbol,table, flow

graph

Parser

Treewalker

tokens

Fi ure 7: Overall translation data


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5. Debugger for grammar errors

7.1.3 Architecture of ANTLR compiler

ANTLR parser tool compiles the verilog RTL (Register Transfer language) behavioral model to

convert it to 'C' programming language. The architecture of ANTLR is similar to most of the

modern day parser generator like Lex, Yacc etc. However, the advantage behind using this tool is,

it can create parse tree in the intermediate stage of language conversion which is very easy to

visualize and test in the GUI. Below in Figure 8, it is clearly shown the high level design of

ANTLR architecture.


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Figure 8: Architecture of ANTLR compiler module

Front End:

The front end of parsor consists of the parser, lexical analyzer and, the semantic analyzer.

LexerThe lexer's input accept a verilog code to make small structures. If there is some error in the

input, error is reported in the interpreter. It has a particular value with each structures which

passed to the parser which is mainly the start of a line, end of a line number and the file name of

the source.

Parser:The job of parser is to accept files passed by the tool and match with the particular grammar

rules. If syntax error found, it can be compiled at this stage. Each supported verilog code is

modeled as Java class. The verilog constructs are converted into objects in Java classes. The

classes together form an internal tree known as Abstract syntax tree or parse tree.

Semantic AnalyzerSemantic analyzer's work is to make parse tree an AST(Abstract Syntax Tree). It does error

checking which was skipped the lexer. The AST is basically an intermediate form between the

front end and back end of language compiler.

Optimizer:

These mainly implemented in order to increase the capacity and reliability of the code.

Back end (Code generator)

The backend is code generator which gives the output code from a standard input. It use the 'C'

codes for behavioral codes in verilog language. The codes can be mapped into equivalent code


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structure. The code generator takes the AST and outputs the targeted 'C' code. The 'C' program

can be compiled using standard gcc complier.

Abstract Syntax Tree (AST) generated by ANTLR:

Below there is a verilog test case which was run in the interpreter and it created the AST clearly.

The AST is shown in Figure 9 and a close-up view is shown in Figure 10.

Verilog test case:

module TOP(in, out);input [7:0] in;

output [7:0]out;assign out=~in;endmodule

Figure 9: AST generated by ANTLR


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Figure 10: Close up view of AST

Verilog RTL to 'C' code generation

After the intermediate phase, i.e. after creating the AST, the next phage is the conversion of

Verilog to C code. A class hierarchy is needed to be implemented in JAVA object oriented

programming language and the actions were embedded in the codes in order to do the conversion

process. A main driver program is written in Java to test the language conversion process. Below

is the example of a verilog test case which is used to test.

Verilog code for 2:1 MUX

module simple_mux(a, b,sel,out);input [31:0] a, b;input sel;

output [31:0] out;assign out = (sel)? b : a;endmodule

Equivalent 'C' code for 2:1 MUX

The C code out of the above verilog module looks like below.


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static void simple_mux(int *pa, int *pb, int *psel, int *pout) {if (*psel == 1) {

*pout = *pb;} else {

*pout = *pa;

}}

7.2 Second phase: Design and Implementation of MicrocontrollerThe existing microcontrollers are not fast enough to replace the FPGAs. The decision making

capability of the microcontroller is limited and slow. On the other hand the FPGAs are fast and

can take multiple decisions in one step. We are focusing on increasing the speed of the

microcontroller and improve the decision making capability of the microcontroller by adding

additional memory and giving the ability for the microcontroller to take multiple decisions. Few

bits of the instruction are dedicated to help the microcontroller in making decisions.

7.2.1 Microcontroller design flow

The flow of the microcontroller design is as shown in Figure 11. The complete flow is divided

into two major parts, Front End and the Back End. The Front End design starts with defining the

design specifications followed by the behavioral description. The designing of the

microcontroller is done using Verilog HDL. Functional verification and testing is performed on

the microcontroller design. Depending on the verification, the design is altered or modified.

Once the design is verified functionally it is then synthesized. Synthesizing the design helps to

determine the area of the microcontroller. It also helps to determine the timing closures, and

delays. Synthesizing the design generates a gate level netlist. Logical verification is the last step

in the Front End. Logical verification is performed on the gate level netlist and based on the

results the verilog design is modified to incorporate the timing and area specifications.


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The second part of the design flow is the Back End. Back End includes floor planning and

automatic place and route, physical layout and layout verification and implementation. All the

Back End work will be outsourced to different companies. Once the Back End is completed the

chip will be taped for manufacturing.

Figure 11: Microcontroller design flow

Source: Magma Design Flow, V. Kamakoti and Shankar Balachandran

http://nptel.iitm.ac.in/courses/IIT-

MADRAS/CAD_for_VLSI_Design_II/magma_tutorial/magma_tutorial.html


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7.2.2 System Architecture

The microcontroller is designed using Harvard Architecture and uses separate buses to access

program and data. This helps the microcontroller to fetch program data with one bus and

read/write to the memory with data bus at the same time. With the help of Harvard architecture it

is easy to implement pipelining and allows the fetch and execution cycles to overlap each other.

The microcontroller has a 32 bit wide instruction set and 8-bit wide data path.

The architecture of the microcontroller is shown in Figure 12. The microcontroller has an 8-bit

Arithmetic Logic Unit (ALU). The microcontroller has 256 byte data memory and 256 byte

program memory. The databank is divided into register bank and special function register bank.

The special function registers are used for assigning the port inputs, timer, status word, etc. An

additional memory of 256 bytes is used by the decision box. Currently in our design we are

supporting only 32 I/O inputs. In addition to the regular microcontroller architecture, an

additional block known as decision box is implemented which helps the microcontroller to take

decisions faster.


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Figure 12: Microcontroller Architecture

The instruction is fetched from the program memory and is decoded by the instruction decoder.

Depending on the decoded bits the respective bits are enabled for ALU operation, branch

operation and decision box operations. A new instruction is fetched at every clock cycle. After

the operation is performed according to the instruction the result is sent back to the CPU and it is

written into the memory at the destination address specified in the instruction. For the decision

box instructions the 5 decision box bits along with the destination address are sent as inputs to

the decision box. The last 5 bits of the destination address are replaced with the output of the

decision box and a new destination address is calculated to fetch the instruction from.


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No interrupts are supported in the design. The microcontroller has 32 I/O inputs connected in the

form of four 8-bit ports. This I/O signals are used in the decision making of the microcontroller.

The different components of the microcontroller are described below.

Instruction Set

The instruction set for the microcontroller is 32-bit wide. Bits 7-0 are signed for the source

address and bit 15-8 are assigned to address the destination address. Bits 20-18 are used as mod

bits which decide the nature of the source and destination. Bits 25-21 are used by the selection

box to make decisions. Table 1 shows the distribution of the instruction set.

31-26 25-21 20-18 15-8 7-0

opcode decisionbox_sel mod_bits destination_address source_address

Table 1: Instruction Set

Mod bits

Mod bits are used to define the source of inputs. These bits define whether the operation is

between a register and a register, register and immediate data, port and register etc. Table 2

describes Mode options.

Case Operation

000 Reg (S) & Reg (D) -----> Reg (S)

001 Immediate(S) & Reg(D) ------> Reg(D)

010 Port(S) & Reg(D) ------> Reg(D)

011 Reg(S) & Port(D) ------> Port(D)

100 Extension ports

Table 2: Mode Conditions


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Opcode

The microcontroller design supports arithmetic, logic and branch operations. Each opcode

represents a different operation, so it is easy for the programmer to choose specific operation.

Our design supports 64 different operations, but right now we are implementing only 16

operations. Table 3 describes the opcodes and their respective operations.

Opcode Operation

000000 MOV

000001 Clear Carry

000010 Set carry

000011 ADD

000100 SUB

000101 ADD with carry

000110 NOT

000111 AND

001000 OR

001001 XOR

001010 Shift Right

001011 Shift Left

001100 Shift rotate right

001101 Shift rotate left

001110 Swap

001111 Jump

Table 3: Opcodes


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CPU

The CPU is the brain of the microcontroller. The CPU fetches the instruction from the program

memory, decodes and executes the instruction. The CPU fetches the instruction form the

program memory using a 32 bit program bus. It also writes the data into the memory using an 8-

bit bus. The main components of CPU are Arithmetic Logic Unit (ALU), Instruction Register

(IR), and Program Counter (PC).

Arithmetic Logic Unit (ALU)

ALU has two 8-bit inputs, 1-bit carryin and the opcode. Depending on the opcode the ALU

performs the respective operation on the two inputs. The ALU has an 8-bit output which is the

result of the operation performed on the two inputs. It also has a single bit carryout output. The

alu_enable input acts as the enable signal for the ALU. The operations are performed by the

ALU only when the enable signal is 1.

Program Counter (PC)

A register known as program counter holds the address of the next instruction. The program

counter is incremented after every fetch operation unless any operation is performed on the

program counter.

Instruction Register (IR)

The instruction pointed by the program counter is fetched and stored in the instruction register.

The instruction is then decoded from the instruction register and the type of operation to be

performed is determined.


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Decision Box

Decision box is the additional mechanism that is being incorporated into the architecture of the

microcontroller. The design of the decision box is shown in Figure 13. The decision box helps

the microcontroller to make decisions faster. The decision box allows the microcontroller to take

decisions from multiple options.

Figure 13: Decision box block diagram

There are 32 I/O inputs connected to the decision box. The decision box has a 35X256 bit

memory. The memory consists of 35bit words. The 5 bits of the instruction are used as address

bits of the memory. The decision box has 5 multiplexers. The 32 I/O are connected as inputs to

all the 5 multiplexers. The selected 35 bit data from the memory is then divided into 7 parts. 5

bits of each part is used as select lines for the multiplexer and other 2 bits are used as AND and

XOR bits. These bits allow the output of each multiplexer to be set or reset depending on the

requirement of the programmer. All the outputs of the multiplexers are then combined and are


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sent as the output. The 5 bit output is then replaced on the last 5 bits of the destination address

used to fetch the next instruction.

8 Economic Justification

8.1 Executive summaryThree engineers from San Jose State University had developed a methodology to replace the high

power, high cost FPGA application by low cost custom designed microcontroller. The project

was completed in two phases. In the first phage, an open source parser generator, ANTLR is

used to convert verilog HDL to C code and then the design of microcontroller was completed in

the second phase.

The targeted customers are mainly the manufactures who are using low power FPGAs and have

their logic and functionality already developed in HDL which is compatible with FPGAs. It will

cost more for these customers to switch completely from FPGA to microcontroller and design

their applications in assembly code. Hence, the company is going to provide a solution to convert

the HDL logic to assembly level, by using the algorithm that the company is generating.

8.2 Problem StatementMany of the applications dont require that high speed for the performance which FPGA offers.

These FPGAs can be replaced with redesigned less expensive microcontrollers.


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8.3 Solution and Value propositionPresent microcontrollers are not fast enough to replace the FPGAs. Redesigning and adding

some decision making capabilities to the microcontroller will increase the speed and

functionality to be able to replace the low speed FPGAs.

8.4 Market sizeThe worldwide microcontroller market is increasing day by day. The market of 8-bit

microcontrollers is expected be reach $6000 million by 2016. The graph in Figure 14 shows the

expected growth of the microcontroller market.

Figure 14: Market Scale forecast for Microcontrollers

Source: Development of the RX Family, Renesas. Retrieved on 16 October, 2009 from

http://america.renesas.com/fmwk.jsp?cnt=backgroud.htm&fp=/products/mpumcu

/rx_family/child_folder/&title=Development%20of%20the%20RX%20Family

Microcontrollers are used in most of the electronic appliances in our daily life. The graph in

Figure 15 shows the distribution of microcontrollers in various applications.


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Figure 15: Worldwide Processor Market In 2010

Source: Retrieved on October 24, 2009 fromhttp://www.etforecasts.com/products

8.5 CompetitorsThe company identified its potential competitors and their product specification while doing the

market analysis. Here is the list of some of the key players of microcontroller and FPGA.

Key Players of Microcontroller

Microchip technology Atmel STMicroelectonics Renesas Technology Corporation MIPS computer system Intel Inc. NEC Electronics Corporation Cypress semiconductor Rabbit semiconductor

Cellphones

60%Smartphone

3%

Computers

34%

Handhelds

3%

PDA

0%


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Texas InstrumentsKey players of FPGA

Altera Inc. Xilinx Inc. Actel Inc Siliconblue chip Lattice Semiconductor Quick logic Inc.

8.6 CustomersThere are many manufactures who are using low speed FPGAs and have their logic and

functionality already developed in HDL which is compatible with FPGAs, it may cost more for

these customers to switch completely from FPGA to microcontroller and design their

applications in assembly code. So for these types of customers the company is going to provide a

solution to convert the HDL logic to assembly level, by using the algorithm that the company is

generating. Some of the customers are

Diabetes network (e.g. Insulin pump) Abbott lab (e.g. Insulin pump) Casio (e.g. Calculators, PDA) Handspring Inc (e.g. PDA) Sinucircuit Inc (e.g. Memory stick) Automobile companies


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8.7 Cost summaryThe cost summary includes fixed cost, variable cost and employee wages. Manufacturing of the

microcontrollers will be outsourced to other companies.

8.7.1 Fixed cost

Fixed costs of the company include office building lease and maintenance, wages of the

employees, electricity and internet, licensing cost for hardware tools, furniture costs, etc.

Category/Year 2010 2011 2012 2013 2014 2015 2016

Licensing cost forHardware Tools $100,000 $100,000 $100,000 $100,000 $100,000 $100,000 $100,000

Licensing cost forSoftware Tools $50,000 $50,000 $50,000 $50,000 $50,000 $50,000 $50,000

Building Rent $80,000 $100,000 $100,000 $110,000 $110,000 $140,000 $140,000

Maintenance $15,000 $17,000 $20,000 $25,000 $25,000 $27,000 $27,000

PG & E bills $10,000 $14,000 $19,000 $21,000 $21,000 $25,000 $25,000

Furniture Cost $15,000 $5,000 $5,000 $8,000 $8,000 $10,000 $10,000Computer

Equipment andStationary $21,000 $25,000 $30,000 $33,000 $33,000 $50,000 $50,000

Internet andTelephone $5,000 $6,600 $7,200 $8,400 $8,400 $12,000 $12,000

Employee wages $500,000 $760,000 $980,000 $1,200,000 $1,600,000 $1,980,000 $2,280,000

Third party IP's $400,000 $550,000 $600,000 $700,000 $900,000 $1,000,000 $1,400,000

Miscellaneous $60,000 $30,000 $30,000 $30,000 $30,000 $30,000 $30,000

Patent cost $2,000 $2,000 $3,500 $3,500 $3,500 $4,500 $4,500

TOTAL $1,258,000 $1,659,600 $1,944,700 $2,288,900 $2,888,900 $3,428,500 $4,128,500

Table 4: Fixed Cost


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8.7.2 Employee Wages

The wages of the employees are decided depending on their role and experience.

Department 2010 2011 2012 2013 2014 2015 2016

Design andevelopment $100,000(1) $360,000(3) $480,000(4) $720,000(6) $780,000(6) $1,000,000(8) $1,080,00

Executives 0 $140,000(1) $140,000(1) $260,000(2) $270,000(2) $520,000(3) $520,000

Marketingand Sales $180,000(2) $330,000(3) $880,000(4) $660,000(6) $800,000(7) $900,000(8)

$1,100,00)

Administration $90,000(1) $100,000(1) $100,000(1) $200,000(2) $200,000(2) $300,000(3) $300,000

Operations 0 0 $90,000(1) $270,000(3) $270,000(3) $360,000(4) $360,000

Management 0 $90,000(1) $90,000(1) $200,000(2) $200,000(2) $300,000(3) $400,000

Table 5: Employee Wages

8.7.3 Variable cost

Variable cost includes advertising costs, wages of contract employees, outsourcing,

manufacturing cost and customer service cost.

Category/Year 2010 2011 2012 2013 2014 2015 2016

Advertisement $100,000 $190,000 $220,000 $250,000 $330,000 $400,000 $600,00

Contractemployee $130,000 $600,000 $1,000,000 $1,300,000 $1,400,000 $2,500,000 $2,300,0

Outsourcing $300,000 $1,100,000 $1,500,000 $2,100,000 $2,500,000 $3,300,000 $4,500,0

Manufacturing $900,000 $2,600,000 $4,040,000 $6,800,000 $8,400,000 $13,000,000 $16,500,

Customer

service $100,000 $150,000 $180,000 $200,000 $220,000 $250,000 $300,00TOTAL $1,530,000 $4,640,000 $6,940,000 $10,650,000 $12,850,000 $19,450,000 $24,200,0

Table 6: Variable Cost


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8.8 Price PointAs the company is focusing on taking over the market of low speed FPGAs, the price of our

product will be less than the price of the FPGAs. This will help to approach the market easily.

We have decided to produce 100K units initially. An assumption of all the values used to derive

the initial price of the product is shown below.

Department Assumed Cost for 100K units(Millions of dollars)

Building lease and Maintenances .3

Insurance and Taxes .2

Manufacturing Cost .4

Hardware design and development .5

Software design and development .2

Outsourcing .4

Marketing and Sales .5

Miscellaneous costs .3

Total 2.7

Table 7: Estimated cost for 100K units

The value was derived after considering the cost of all the issues involved like product design,

maintenance, software, manufacturing of the microcontroller, salaries, etc. We have decided our

initial price of our microcontroller to be $15. The initial price of the product is less than the

amount obtained by dividing the estimated cost with the number of units. To enter into the

market and to sustain and takeover the low speed FPGA market; the price of the microcontroller

has to be less than the FPGA.


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8.9 SWOT AssessmentSWOT assessment was done after doing the market analysis and business case analysis. FPGA

market is already popular in the market and this project is proposing a methodology to

penetrating into the FPGA market to replace some of the application by microcontroller. The

company realizes that this project is a big challenge to enter into an already established

competitive market. The biggest challenge is to satisfy the customer need by providing the

cheaper solution with all kinds of features in it. Any kind of start up company has to face lots of

completion in order to make profit in this recession.

There is a brief overview of the SWOT analysis is given below.

STRENGTH

Low cost

Faster than present microcontrollers

Frontend design implemented

successfully

WEEKNESS

Not enough resources

Startup company in the currentrecession period.

OPPERTUNITY

The market of 8-bit microcontrollersis expected be reach $6000 million by2016

The custom designed controller canprovide a better solution in the currentcontroller market.

THREATS

Competitors are always trying theirbest to come up with newtechnologies.

Recession period is really a risk forthe small start ups.

Table 8: SWOT assessment


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8.10 Investment Capital RequirementThe company will break even by the end of 2012. The company requires around 2.7 million

dollars before it breaks even. We will be raising part of this money from the investors and the

rest will be taken from the banks as a long term loan. Once the company has reached the

breakeven point, the profits will be reinvested on the company.

8.11 PersonnelSince the company is focusing on a newly emerging technology, it is stared with only three

employees initially. The tasks will be distributed equally among the three employees. One

employee will take care of the product design and development; the second employee will

concentrate on development and testing, i.e. converting Verilog HDL to C codes and testing it.

The third employee will be in charge of the non-technical part like marketing, resources, and

administration. The product needs to be done in two phases. The first phase will be the front end,

where the product will be designed, developed and tested using simulators. The second phase is

the backend where the product will be manufactured and the actual testing of the real product

will be done. The company will be working with third party vendors for manufacturing the

product.

As it is small company, the plan is to outsource the backend work to other companies have less

time to market. Table- shows the expected human resources of our company in the next 5 years.

Most of the employees will not be full time, but will be hired as contractors, based on the

requirement of the projects.


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Department/Year 2010 2011 2012 2013 2014 2015 2016

Design and

development

1 3 4 6 7 8 9

Executives0 1 1 2 2 3 3

Marketing andSales

2 3 4 6 7 8 10

Administration 1 1 1 2 2 3 3

Operations 0 0 1 3 3 4 4

Management 0 1 1 2 2 3 4

Table 9: Human Resources

8.12 Business and Revenue ModelFrom the market survey we have learned that there is a big growth for microcontroller market.

Introducing microcontrollers that can replace low speed FPGAs will be ideal for present and

future market. The microcontrollers will be directly sold to the Original Equipment Manufacturer

(OEMs) companies who manufacture low speed equipment and applications. The initial price of

the microcontroller will be $15. The company's target is to sell 3 million microcontrollers by the

end of 2016.

8.13 Strategic Alliance/PartnersOur company will be partnered with the leading foundries like Fujitsu for manufacturing the

microcontrollers. Our company is also planning to form alliance with Synopsys for the

development of the software tool used to convert Verilog HDL to assembly code. These


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partnerships and alliances will help us to approach the present and future market with cheaper

microcontrollers.

8.14 Profit/LossThe expenses for developing and manufacturing the microcontroller and estimated and the price

of the microcontroller is decided. Once the price of the microcontroller is decided, the revenues

are calculated for each year depending on the estimated number of microcontrollers sold each

year. With the numbers for the estimated expenses and revenues the profit/loss is derived. The

company is expecting loss for the first two years and will start gaining profits from the last

quarter of third year. Below the table and graph which show the estimated profit/loss for the next

7 years.

Year ExpectedRevenue(Millions

of dollars)

Fixed Cost(Millions

of dollars)

Variablecost/unit(dollars)

VariableCost

(Millionsof dollars)

Total Cost(Millions

of dollars)

Loss/Profit(Millions of

dollars)

2010 - 1.2 13.9 1.5 2.7 - 2.73

2011 1.6 1.2 13.9 1.5 2.7 -1.08

2012 5.4 1.5 13 4.6 6.2 -0.89

2013 8.54 1.9 11.4 6.9 8.8 -0.38

2014 13.2 2.2 11.1 10.7 12.9 0.39

2015 17.7 2.8 9.8 12.8 15.5 2.17

2016 28.6 3.5 8.8 19.4 12.9 5.74

2017 37.8 4 8.1 24.3 28.3 9.53

Table 10: Profit/Loss


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Figure 16: Profit/Loss graph

8.15 Breakeven AnalysisBreakeven point is the point where the revenue of a product is equal to the cost of making the

product. To calculate this point we use a financial tool known as Breakeven Analysis.

Our company is expected to reach the breakeven point by the end of 2012. The breakeven point

graph is shown in Figure 17.


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Figure 17: Break Even Analysis Graph

8.16 Return on Investment (ROI)

Return on investment is the ratio of the investment and the profit.

Investment

LossofitROI

)(Pr= * 100

Our initial investment was 2.7 million and cumulative benefit ~12.75 million by the end of 2016

12.75Return on Investment = ----------------- X 100 = 471.8%

2.7

The company is expecting to breakeven by the end of 2012. By the end of 2016, the company

will gain about 464.8% of the investment over a period of 7 years. Which means, for every dollar

spent, the investor will receive $4.64 in return over a period of 7 years.


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8.17 Exit StrategyOur company is open for either going public or acquisition depending on the market growth and

economy. We also have plans to merge into other microcontroller manufacturing companies.

9 Project Schedule

The gantt chart for the schedule of the project is shown below.

Figure 18: Project Schedule

10 Conclusion

The project developed a methodology in order to penetrate into the popular FPGA market to

replace it by a cheaper custom designed microcontroller. The several steps of the project used

many kinds of open source software. The conversion of verilog HDL to C language and

designing the multiway branch switching microcontroller has been completed. The custom

designed microcontroller is simulated and tested using open source ModelSim. After the


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verification of a working design, the startup will be ready for the marketing its first design. The

break even analysis shows, profit will be stated from the third quarter of year 2012. From the

market analysis, it can be concluded that the low cost microcontroller with improved

performance can be a key player in the world of automotive products for low power applications.

11 Future Work

The company has planed to add and implement new features in the workflow of this project.

Right now, the verilog to C conversion is supporting only the synthesizable verilog constructs

and the future plan is to support the simulation constructs. There is also plan to enhance the

features of the custom designed microcontroller in order to make it more powerful, cost effective

and customer centric.


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12 List Of References:

Actel Corporation. System Solutions. Retrieved October 2, 2009

from http://actel.com/company/default.aspx

Altera Inc.End Markets. Retrieved October 2, 2009

from http://www.altera.com/end-markets/end-index.html

Amy Leong (August, 2008). Dataquest Insight: Microcontrollers Are Key Enablers

for Green Vehicles. Gartner, Inc. Retrieved on 1 October, 2009 from

http://www.gartner.com/DisplayDocument?ref=g_search&id=737912&subref=simplesea

rch

ANTLR v3, retrieved on October 2, 2009 from

http://www.antlr.org/

Arnold, Henri(2007).EETimes. Wireless microcontrollers achieve new performance

and price points. Retrieved October 2, 2009 from

http://eetimes.eu/showArticle.jhtml?articleID=196801875&queryText=price

Bringing ARM7(TM) to the Masses design-reuse. Retrieved October 12, 2009 from

http://www.design-reuse.com/articles/11767/bringing-arm7-tm-to-the-masses.html

Budd, Graham, & Milne, George (1996) ARM7100 - A High-Integration, Low-

Power Microcontroller for PDA Applications [Electronic version]. Retrieved on October

3, 2009 from


&isnumber=10694


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Cadden, Cheryl & Worchel, Jerry (May, 2006). Semiconductor Logic Markets . FPGA Market

Will Reach $2.75 Billion by Decades End. Retrieved on 30 September, 2009 from

http://www.instat.com/press.asp?Sku=IN0603187SI&ID=1674

Christoph,Hammerschmidt (2007). EETimes. Automotive applications to drive

microcontroller market. Retrieved on October, 15 2009 from

http://www.eetimes.eu/germany/202101848

Development of the RX Family - Driven by key embedded-system design

issues. Renesas Inc. Retrieved October 12, 2009 from

http://america.renesas.com/fmwk.jsp?cnt=backgroud.htm&fp=/products/mpumcu

/rx_family/child_folder/&title=Development%20of%20the%20RX%20Family

Directory listing for /grammar/verilog, retrieved on January 12, 2010 from

http://www.antlr.org/grammar/verilog

Ed, Sperling (2005).Bottom of the Market, Top of the Game. Retrieved on

October, 15 2009 from http://www.edn.com/article/CA6250222.html

Erdas, Nalan ,& Gunduzalp, Mustafa (1999) Design of an 8 bit general purpose

microcontroller with sea-of-gates design style [Electronic version]. Retrieved on

September 30, 2009 from

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=884834&isnumber=19105

Field Programmable Gate Array, retrieved on 2 October, 2009 from

http://en.wikipedia.org/wiki/Field-programmable_gate_array

FPGA projects dominate by a 30 to 1 margin. GateRocket, Inc. Retrieved on October

12, 2009 from http://www.gaterocket.com/device-native-

verification/?Tag=FPGA+Market


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Gartner Says Green Vehicles to Drive Automotive Microcontroller Market to Reach $6.3 Billion

in 2012. Gartner Inc. Retrieved on 1 October, 2009 from

http://www.gartner.com/it/page.jsp?id=744612

Golbert A. & Israel I. (1991) Trends in microprocessor cache architectures

[Electronic version]. Retrieved on October 3, 2009 from

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=217645&isnumber=5704

Hammerschmidt, Christoph (September, 2009).EE Times Europe. Automotive applications to

drive microcontroller market. Retrieved on 27 September,2009 from

http://www.eetimes.eu/germany/202101848

In 2009 to shrink China's MCU market will reach double-digit rate. Toeney Electronics Corp.

Retrieved October 10,2009 from

http://www.toeny.com/en/news13.html?id=79

Le, Meghan (June, 2004).EE Times. 8-bit microcontrollers: still going. Retrieved on 1 October,

2009 from http://www.eetimes.com/showArticle.jhtml?articleID=54202120

MacLean, W.J. (2005). An Evaluation of the Suitability of FPGAs for Embedded Vision

Systems,IEEE Computer Society Conference on Computer Vision and Pattern Recognition. 131.

Retrieved on 1 October, 2009 from

http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=1565446&isnu

mber=33215?tag=1

Ma Xiaojun; Tong Jiarong; Design and Implementation of a New FPGA Architecture, 21 Oct,

2003. 2, 816 819. Retrieved on 1 October, 2009 from


5&isnumber=28525


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http://www.bloomberg.com/apps/news?pid=conewsstory&refer=conews&tkr=ALTR%3

AUS&sid=aPyV1AmGEEBk

Revolutionary Architecture for the Next Generation Platform FPGAs, Xilinx. Xilinx press

release, December 8, 2003, retrieved on 5 October, 2009 from

http://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf

Rich Kapusta, Low Power FPGAs A New Era, Actel Corporation. retieved on 1 October, 2009

from

http://www.actel.com/company/events/default.aspx

Robert Jania (2009). PRODUCT HOW-TO: Make the transition from 8- to 32-bit

MCU design as painless as possible Retrieved on October, 15 2009 from

http://www.embedded.com/products/220301132;jsessionid=CZL2IIBXUIWZVQE1GHR

SKHWATMY32JVN?pgno=2

Verilog to C compiler simulator generator, retrieved on 12 February, 2010 from

http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf

http://www.antlr.org/grammar/verilogXilinx Inc.Market Solutions. Retrieved October 3, 2009

from http://www.xilinx.com/esp/index.htm

Yingbiao, Yao; Jianwu, Zhang; & Danying , Zhao (2008). Survey on microprocessor

architecture and development trends [Electronic Version]. Retrieved on October 3, 2009

from


7&isnumber=4716080?tag=1


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13 APPENDIX A

Set up ANTLR environment:

Set up eclipse by downloading Eclipse Classic 3.5.1(162MB) distribution fromwww.eclispe.org.

Go to www.antlr.org to download ANTLR v3 Click on the "Download" button and download Complete ANTLR 3.2jar, all tools,

runtime, etc.

To add the ANTLR IDE in to the eclipse, go to www.antlr.org/wiki and under the wikicontents, click on the "Integration with Development Environment" link.

After the ANTLR IDE and Eclipse integration is done, load the verilog grammar file intothe environment.

Load the verilog test case modules into the eclipse in order to check how ANTLR isgenerating lexer and parser automatically.

Integrate the ANTLR generated lexer, parser, verilog grammar and test case in the eclipseenvironment.

Run the test case to check the AST formation


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14 APPENDIX B

Supported Verilog Constructs

List of verilog keywords

always endmodule localparam deassign

and endprimitive macromodule default

assign endspecify medium defparam

automatic endtable module disable

begin endtask nand edge

buf event negedge else

posedge for nor end

negedge forever not endcase

case force notif0 endfunctioncasex fork notif1 highz0

casez function or highz1

signed deassign else if

while default join initial

wire defparam large inout

xnor disable output input

xor edge parameter integer

(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors)

Lexical Constructs

OperatorsWhiteSpaces

CommentsSingle line, multiple linecomments

NumbersDecimal, binary, hexadecimal &octal

Identifiers Simple, Escaped & system names



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Supported Verilog Operators

UnaryOperators +,, !,&, |, &, |, ,

BinaryArithmeticOperators +,, /,%,

BinaryLogicalOperators &&, ||BinaryBitwiseOperators &, |,,,, &,|

ShiftOperators ComparisonOperators ,=,==, !=,===, !==TernaryOperator ?,:


Data types

Resisters width registersNets Wire type nets are supported

Parameters Parameter, localparam


Behavioral Modeling

Continuous assignments

Case statement

Conditional statementProcedural assignments

Loopsfor, while, repeatloop

Blocks

Timing controls

Tasks

Functions

Initial

Always



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Unsupported Verilog Constructs

Data types Time

Real numbers

Eventsparameter(defparam)

Behavioral modeling Loops(forever)

Specify blocks Ignored by parser



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15 APPENDIX C

//****************SJSU_298_VERILOG_GRAMMER***************************//

grammar veri l og;

options {l anguage = J ava;

}

@header {package com. j avadude. ant l r 3x;

}@l exer: : header {package com. j avadude. ant l r 3x;

}

/ / PARSERsour ce_t ext : ( descr i pt i on ) *

EOF;

descri pt i on : modul e | di r ect i ve;

modul escope {

St r i ng modName;

}: ' modul e' name_of _modul e{

/ / Syst em. out . pri nt l n( "Found a modul e "+$name_of _modul e. t ext ) ;TopHandl er . Cr eat eModul e( $name_of _modul e. t ext ) ;$modul e: : modName = $name_of _modul e. t ext ;

}( l i st _of _por t s) ? SEMI ( modul e_i t em) * ' endmodul e';

l i s t_of _por t s : LPAREN port ( COMMA port)* RPAREN;

por t : name_of _var i abl e {

/ / System. out . pr i nt l n( "Found a por t "+$name_of _var i abl e. t ext) ;TopHandl er . Cr eat ePor t ( $modul e: : modName, $name_of _var i abl e. t ext ) ;

};

modul e_i t em :/ / ambi gui t y between net _decl arat i on and cont i nuous_assi gn,/ / but par ser get s i t r i ght : keyword chosen over I DENTI FI ER.

i nput _decl ar at i on | out put _decl ar at i on | i nout _decl ar at i on|


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net _decl ar at i on | r eg_decl ar at i on | t i me_decl ar at i on |di rect i ve |

par amet er _decl ar at i on | i nt eger _decl ar at i on | r eal _decl ar at i on |gat e_decl ar at i on | i nst ant i at i on |paramet er _over r i de | cont i nuous_assi gn |i ni t i al _st at ement | al ways_st at ement | t ask |

f uncti on;

i nst ant i at i on: modul e_i nst ant i at i on;

t ask : ' t ask' name_of _t ask SEMI ( t f _decl ar at i on) * st at ement _or _nul l ' endt ask';

f unct i on : ' f unct i on' ( r ange_or _t ype) ? name_of _f unct i on SEMI( t f _decl ar at i on) + st at ement ' endf unct i on'

;

r ange_or _t ype : r ange | ' i nt eger ' | ' r eal '

;

t f _decl arati on :par amet er _decl ar at i on | out put _decl ar at i on | i nput _decl ar at i on |

i nout _decl ar at i on |r eg_decl ar at i on | t i me_decl ar at i on | i nt eger _decl ar at i on |

r eal _decl ar at i on;

paramet er _decl arat i on : ' parameter ' ( r ange) ? l i st _of _par am_assi gnment s SEMI;

l i st _of _par am_assi gnment s : param_assi gnment (COMMA param_assi gnment ) *;

param_assi gnment : i dent i f i er ASSIGN expr essi on;

i nput _decl ar at i on : ' i nput ' ( r =r ange) ? l ov=l i st _of _var i abl es SEMI{

TopHandl er . SetPor t Di r ( $modul e: : modName, $l ov. t ext , "input") ;if ( $r. val ue ! = null) {

TopHandl er . SetRange( $modul e: : modName, $r . val ue,$l ov. t ext , "port") ;

}};

out put _decl ar at i on : ' out put ' ( r =r ange) ? l ov=l i st _of _var i abl es SEMI{

TopHandl er . SetPor t Di r ( $modul e: : modName, $l ov. t ext , "output") ;if ( $r. val ue ! = null) {

TopHandl er . SetRange( $modul e: : modName, $r . val ue, $l ov. t ext ,"port") ;

}};


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i nout _decl ar at i on : ' i nout ' ( r =r ange) ? l ov=l i st _of _var i abl es SEMI

{TopHandl er . SetPor t Di r ( $modul e: : modName, $l ov. t ext , "inout") ;if ( $r. val ue ! = null) {

TopHandl er . SetRange( $modul e: : modName, $r . val ue, $l ov. t ext ,"port") ;

}};

net _decl ar at i on : ' wi r e' ( r =r ange) ? l ov=l i st _of _var i abl es SEMI / / wi re [ 9: 0]w1, w2;

{TopHandl er . Cr eat eWi r e( $modul e: : modName, $l i st _of _var i abl es. t ext ) ;if ( $r. val ue ! = null) {

TopHandl er . SetRange( $modul e: : modName, $r . val ue,$l i s t_of _var i abl es. t ext , "wire") ;

}}

;

net_ type : ' wi re' | ' t r i ' | ' t r i 1' | ' suppl y0' | ' wand' | ' t r i and' | ' t r i 0' | ' suppl y1' |' wor ' | ' t r i or ' | ' t r i r eg'

;

r eg_decl ar at i on : ' r eg' ( r =r ange) ? l ov =l i st _of _var i abl es SEMI / / r eg [ 5: 0]ra, rb;

{TopHandl er . Cr eat eReg($modul e: : modName, $l i st _of _var i abl es. t ext ) ;if ( $r. val ue ! = null) {

TopHandl er . SetRange( $modul e: : modName, $r . val ue,$l i s t_of _var i abl es. t ext , "reg") ;

}};

t i me_decl arati on : ' t i me' l i st_of_r egi ster_var i abl es SEMI / / t i me t 1, t 2;;

i nt eger _decl arati on : ' i nt eger' l i st_of_r egi ster_vari abl es SEMI / / i nt egercount , di f f ;

;

real _decl arat i on : ' real ' l i s t_of _var i abl es SEMI / / real r1, r2;;

cont i nuous_assi gn : ' assi gn' ( del ay) ? l i st _of _assi gnment s SEMI / / assi gn #5w1=a&b;

{

};

paramet er _over r i de : ' def param' l i st _of _par am_assi gnment s SEMI / / def par amg1. wi dth=8, g2. wi dth=4;


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56

;

l i st _of _var i abl es : name_of _var i abl e ( COMMA name_of _vari abl e ) *;

l i st_of _regi ster_vari abl es : r egi ster_var i abl e ( COMMA regi ster _vari abl e )*/ / r a, r b, r c

;

r egi st er _var i abl e : name_of _r egi st er / / r a| name_of _memor y LBRACK expr essi on COLON expr essi on RBRACK / / r am[7 :0 ]

i . e. reg [ 3: 0] r am [ 7: 0] ;;

/ / r ange : LBRACK expressi on COLON expr essi on RBRACK / / [ 7: 0] , [ a+b: a- b]r ange returns [ St r i ng val ue] : LBRACK DIGIT+ COLON DIGIT+ RBRACK

{Syst em. out . pr i nt l n( "Found Range "+$r ange. t ext ) ;$val ue = $r ange. t ext ;

}

;

l i st _of _assi gnment s : assi gnment ( COMMA assi gnment ) *;

/ / Pr i mi t i ve I nstances/ / - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --

gat e_decl ar ati on : gat e_t ype ( del ay)? gate_i nst ance ( COMMA gate_i nst ance ) *SEMI / / not n1( o1, i 1) , n2( o2, i 2) ;

;

gat e_type : ' and' | ' nand' | ' or ' | ' nor ' | ' xor ' | ' xnor ' | ' buf ' | ' not ';

del ay : POUND NUMBER | POUND i dent i f i er | / / #5 or #d1POUND LPAREN mi ntypmax_expressi on

( COMMA mi ntypmax_expressi on ( COMMA mi ntypmax_expr essi on ) ?) ?RPAREN / / #( 5) , #( 5, 6) , #( 5, 6, 7)

;

gate_i nst ance : ( name_of _gat e_i nst ance) ? LPAREN t er mi nal ( COMMA t er mi nal ) *RPAREN

;

t er mi nal : expr essi on

;

/ / Modul e I nst ant i at i ons/ / - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --

modul e_i nst ant i at i on : name_of _modul e modul e_i nst ance(COMMAmodul e_i nst ance ) * SEMI

;


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modul e_i nst ance : name_of _i nst ance LPAREN l i st _of _modul e_connect i ons RPAREN/ / g1( a, b, c) , g2( . A( a) , . B( b)

;

l i st _of _modul e_connect i ons :modul e_port _connect i on ( COMMA modul e_port _connect i on ) * |named_por t _connect i on ( COMMA named_por t _connect i on ) *;

modul e_por t _connect i on : expr essi on;

/ / expr essi on bel ow i sn' t opt i onal accor di ng t o Pal ni t kar , but/ / several exampl es generat ed by Cadence use t hi s synt ax.named_por t _connect i on : DOT IDENTIFIER LPAREN ( expr essi on) ? RPAREN/ / . A( ) , . B( b)

;

/ / Behavi oral St atement s/ / - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-

i ni t i al _st at ement : ' i ni t i al ' s tat ement;

al ways_st atement : ' al ways' st at ement;

st at ement _or _nul l : ( st atement ) => st atement | SEMI;

st at ement :( l val ue ASSIGN) => bl ocki ng_assi gnment SEMI | / / a = b&c ;( l val ue LE) => non_bl ocki ng_assi gnment SEMI | / / a


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non_bl ocki ng_assi gnment : l val ue LE ( del ay_or_event _cont r ol ) ? expr essi on

;

/ / "el se" cl ause i s i nher ent l y ambi guous; ANTLR get s i t r i ght ,/ / so suppr ess warni ng.

condi t i onal _st at ement :' i f ' LPAREN expr essi on RPAREN st atement _or _nul l( ' el se' statement _or _nul l ) ?;

case_st at ement :case_keywor d LPAREN expr essi on RPAREN ( case_i t em) + ' endcase';

case_keywor d : ' case' | ' casez' | ' casex';

case_i t em :

expr essi on ( COMMA expr essi on )* COLON st at ement _or_ nul l |' def aul t ' ( COLON) ? st at ement _or_ nul l;

l oop_st atement :' f or ever ' st at ement |' r epeat ' LPAREN expr essi on RPAREN st at ement | / / r epeat ( 6) begi n . . .

end' whi l e' LPAREN expr essi on RPAREN st at ement | / / whi l e( cond) begi n. . .

end' f or ' LPAREN assi gnment SEMI expr essi on SEMI assi gnment RPAREN

st at ement;

pr ocedur al _t i mi ng_cont r ol _st at ement : del ay_or _event _cont r olst atement _or _nul l

;

wai t _st atement : ' wai t ' LPAREN expr essi on RPAREN st atement _or _nul l;

event _t r i gger : TRIGGER name_of _event SEMI;

di sabl e_st at ement : ' di sabl e' IDENTIFIER SEMI;

seq_bl ock : ' begi n'( COLON name_of _bl ock ( bl ock_decl ar at i on) * ) ? ( st at ement ) * ' end';

par _bl ock : ' f ork'( COLON name_of _bl ock ( bl ock_decl ar at i on) * ) ?( st atement ) *' j oi n';


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bl ock_decl ar at i on :parameter _decl arat i on |r eg_decl ar at i on |i nt eger _decl ar at i on |r eal _decl ar at i on |t i me_decl ar at i on;

t ask_enabl e : name_of _t ask ( LPAREN expr essi on ( COMMA ( expr essi on) ?) *RPAREN ) ? SEMI

;

syst em_t ask_enabl e : SYSTEM_TASK_NAME ( LPAREN expr essi on ( COMMA( expr essi on) ?) * RPAREN ) ? SEMI

;

pr ocedural _cont i nuous_assi gnment :' assi gn' assi gnment SEMI |' deassi gn' l val ue SEMI |' f or ce' assi gnment SEMI |

' rel ease' l val ue SEMI;

del ay_or _event _cont r ol : del ay_cont r ol | event _cont r ol;

/ / Expr essi ons/ / - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --

l val ue : ( i dent i f i er r ange) => i dent i f i er r ange | i dent i f i er | concat enat i on; / / x[3: 0] = . . . OR x = . . OR {x, y} = . .

concat enat i on : / / {x, {y, z[ 5] }, x[ 6] }( LCURLY expr essi on LCURLY) => LCURLY expr essi on LCURLY expr essi on

( COMMA expr essi on ) * RCURLY RCURLY | LCURLY expr essi on ( COMMA expr essi on )*RCURLY

;

mi ntypmax_expr essi on : expr essi on ( COLON expr essi on COLON expr essi on ) ?;

exp11 : STRING | NUMBER | ( f uncti on_cal l ) => f uncti on_cal l | l val ue | DEFINE;

exp12 : exp11 | LPAREN expr essi on RPAREN / / ( a+c)

;

exp9 : exp12 | unary_operat or exp9 / / &a;

exp8 : exp9 ( bi nar y_oper at or exp9 ) * / / a+b+c&d;

exp7 : exp8 ( QUESTION exp7 COLON exp7 ) ? / / ( a

cost effective reconfigurable logic

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