cs/coe 536 : lockwood 1 cs/coe 536 reconfigurable system on chip design lecture 9 : mp3 working...

CS/CoE 536 : Lockwood 1

CS/CoE 536

Reconfigurable System On Chip Design

Lecture 9 : MP3 Working Draft

Washington UniversityFall 2002

http://www.arl.wustl.edu/~lockwood/class/cs536/

John Lockwood

Copyright [email protected]


Overall CS536 Machine Problem Structures

Layered Protocol Wrappers

Content-basedMatch

(regex)

(MP2)

CAM-basedFirewall

(MP1)

FlowBuffer

Queue Manager

(MP 3)

InputTraffic

FromLinecard

Firewall on a Chip ( Boundry of the RAD on the FPX,

a VirtexE 2000 FPGA )

OutputTraffic

ToLinecardor switch

p p p p

Off-Chip Synchronous Random Access Memory (SDRAM)

Matchvector

Flow#from CAM

Free List Manager

Identify packetsBased on

Head.Ptr Tail.Ptr

Free.Ptr

16

Off-Chip Static RandomAccess Memory (SRAM)


Extension to CAM Lookup Filter

• Number of CAM entries– Expanded to 4 entries

• Additional Field in CAM– FlowID returns

• Additional Field in Control Packet– FlowID – Now 128 bits

• Priority Encoder– Output from the CAM has the FlowID from the

lowest matching CAM entry.


Interface to Flow Buffer

• Signal Description --packet data going to the flow buffer PktDataIn : in std_logic_vector(31 downto 0); PktDataInValid : in std_logic; SoPktIn : in std_logic; EoPktIn : in std_logic;--packet data going out of the flow buffer PktDataOut : in std_logic_vector(31 downto 0); PktDataOutValid : in std_logic; SoPktOut : in std_logic; EoPktOut : in std_logic;--Interface with the Queue Contex ---The following two signals come from the QueueContext Tail : in std_logic_vector(31 downto 0);; TailValid : in std_logic; ---The following two signals go to the queue context NextTail : out std_logic_vector(31 downto 0);; NextTailValid : out std_logic; ---The following two signals come from the QueueContext Head : in std_logic_vector(31 downto 0);; HeadValid : in std_logic; ---The following two signals go to the queue context NextHead : out std_logic_vector(31 downto 0);; NextHeadValid : out std_logic;


`



• Protocol



• Timing Diagram Example


RAD Module Interface

• Cell I/O and Flow Control– 32-bit wide UTOPIA-style interface w/ unique timing

• Off-chip Memory Access– Arbitrated access to SRAM and SDRAM via standard

interface• Control (clock, reset, and reconfiguration control)


SRAM Interface Module

• Interface to off-chip ZBT SRAM

• Abstracts modules from device specific timing

• Independent interface for each module

• Arbitrates requests and issues grant to winning module

• Modules retain access by holding request high after receiving grant– Modules responsible for

preventing starvation


SRAM Interface Timing

• All I/O signals must be flopped at module boundary to ensure timing constraints are met

• Timing diagrams take reference point from inside module and assume boundary flops


Design Issues & Recommendations

• Conform to the Module Interface Specification– Make your design as easy to integrate as possible

• Use provided infrastructure– Enables resources on the FPGA to be shared

• Use Synchronous Design Techniques– Flop all module I/O signals– Use synchronous reset

• Simulate Design– Verify that the device

• Synthesize Design– Over-constrain timing delays– Optimize along the critical path of the circuit

• Share experience and wisdom with other developers


Queue Management

A

B

C

Reserved Empty Slot[implementation dependant]

M[x]

M[y]

M[z]

M[u]OtherFlowState

Fi

Head Pointer

D M[v]

Note thatpackets can

be storedanywhere in

memory

Packet StoreFlow State

Head Pointer

Tail Pointer

Empty Slot

Head Pointer

Tail Pointer

Packet Reads= 3

Packet Writes= 3


Initial State of Queue

Reserved Empty Slot

[implementation dependant]

M[0]

F1

F0

Head Pointer

M[64k]



memory


Head Pointer

Tail Pointer

Empty Slots

Head Pointer

Tail Pointer

Packet Reads= 3

Packet Writes= 3

Reserved Empty Slot

[implementation dependant]

M[1]


New Packet Arrives

A

B

C

NewData

Reserved Empty Slot[implementation dependant]

M[u]

Fi


Head Pointer

Tail Pointer

Empty Slot

Updated Pointers

Head Pointer

Tail Pointer

Packet Reads= 3

Packet Writes= 3


Packet Departs

Head Pointer

Tail Pointer

Packet Reads= 3 B

C

Fi



memory


Head Pointer

Tail Pointer

Empty Slot

Packet Writes= 3


2: Queue Manager provides an address

Memory pointer, x = Flow[i].tail

Detailed Operation of the Flow Buffer

FlowBuffer

QueueManager

p p

Off-Chip Synchronous Random Access Memory (SDRAM)

Free List Manager

Tail.Ptr Head.Ptr

Free.Ptr

1: New packet data arrives on Flow

Number i

Packet Data

Flow#

Packet Data

5: Queue Manager provided with new memory pointer, y.Set Flow[i].tail = y

4: New memory pointer, y,

provided from free list

1: QM Decides it is time for a packet to depart. Reads Flow[i].head = z

2: packet from M[z]

3: Packet Data stored in M[x]

3: QM sets Flow[I].head =

M[z].next

5: z returned to the Free

List 4: M[z].data transmitted


L NE

H E EMPTY

L NE

H

A a a 1 2 n

a a a 1 n

servicequeues

traffic vector of 3DQ :

destination group(for outport n)

destination group(for outport 1)

per-VC queues

VCWVCy

HEAD

tail

(cell room

available)

freelist

ATM cell in cell room

free cell room

NE

Aj

j

LEVELpriority

VCX

multicast VC

non-empty

unicast VC

VC..

linked list pointers

VC table

3DQ Architecture

• Traffic groups– Can avoids HOL

blocking

• Prioritized Service Queues– N Priority levels (4)– Highest priority first

• Per-flow Queues– Linked list– Multicast


VCw VCx VCy VCw VCx VCy

HEADtail tail head

VCW VCx VCy

tail head VC LINK TO

service queue

removed

VC re-enters

link to VC removed

(b) an non-SQR case(a) a service queue (c) a SQR case

per-VC queueper-VC queue per-VC queue

service queue: service queue: service queue:

Queue Re-entry Mechanism

– VC queue re-enters service queue when the VC queue is not empty

– SQR Statistically and Fairly Allocates Bandwidth to VCs That Belong to the Same Service Queue.


DiffServ Topology

• At the Edge of network– Uses only a few bits of

information per packet– Typically marked by a

Packet Classifier• Cannot trust end users to

mark their own packets– Everyone would want

their packets to be most important!

– Berkeley Unix defaults to using high priority

• Cannot usually trust other networks

IngressRouter

(Classify)InteriorRouter

EgressRouter

InteriorRouter

EgressRouter

SourceHost

DestinationHost

IngressRouter

(Classify)

Autonomous System 1

Autonomous System 2


Acknowledgements

• This presentation mentions:– DiffServ material

• Van Jacobson, Differentiated Services for the Internet, First Internet2 Joint Applications/Engineering QoS Workshop, May 21-22, 1998

– IntServ / DiffServ material• http://www.cs.unc.edu/Courses/comp249-s02/lectures/

comp249_s02_17/

– Hardware Queuing Design• H. Duan, J. W. Lockwood, S. M. Kang, J.D. Will, A High-

performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches, IEEE Infocom '97, Kobe, Japan, April 7-11, 1997, pp 20-28.


MP3 Assignment To Do List

• CAM – Provide 4 CAMs (from 2) – Add 16-bit entry called “Flow ID” to each CAM

• Provide output called FlowID from the CAM module• Provide priority encoder so that the lower number CAM

provides a value when multiple CAMs match

– Add 16-bit entry called “Flow Hash” • XORs bits in the header fields to produce a pseudo-

unique flow identifier for each of the possible 2^112 Bits available to the CAM

• SRAM Flows– Initialize values to i for i=0..64k–


MP3 Laboratory Todo

• Coregen “tutorial”– Just a few screen shots that show

• Creation of a FIFO• Instantiation of a FIFO• Simulation of FIFO

– We will demonstrate this in class on Monday• PPT slides with screen dumps


• Control Packet Update– Provide ability to update any CAM number, not

just the first two

– Add “No Transmit” and “Transmit” Control Bit (extra bit in header)

• Corresponds to Transmit_enable signal to QM• When set, stops the QM from transmitting data.• I.e., All data stays in the queue.• I.e., Turn off the output• I.e., Set C=0

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