Design and Construction of Direct Sequence Spread Spectrum CDMA Transmitter and Receiver

M. Habib Ullah, Akhmad Unggul Priantoro, M. Jasim Uddin,

Department of Electrical and Computer Engineering International Islamic University Malaysia

habib_ctg@yahoo.com Abstract - Spread Spectrum Communication techniques have been widely accepted in mobile and wireless communications. They have very beneficial and tempting features, like Antijam, security, and multiple accesses. It is the purpose of this paper to describe the features of Spread Spectrum systems. The emphasis will be on the Direct Sequence Spread Spectrum (DS-SS) scheme, Pseudo Noise signals (PN), Modulators and Demodulators, Hardware implementation and illustrate some of the DS-SS system features.

Index Terms - CDMA, PN Code, Modulation, Demodulation, DS-SS.

I. INTRODUCTION Spread Spectrum Communications is one of the widely used data communication schemes nowadays. It has many features that make it suitable for secure, multiple accesses, and many other properties that are needed in a communication system. Spread Spectrum is defined as: Spread Spectrum is a means of transmission in which the signal occupies a bandwidth in excess of the minimum necessary to send the information. The band spread is accomplished by means of a code, which is independent of the data, and synchronized reception with the code at the receiver is used for dispreading, and subsequently data recovery. Basically spread spectrum is a coding technique for digital transmission. It was originally developed for the military under a veil of secrecy. The purpose of coding is to transform an information signal so that it looks more like noise. In the receiver, the incoming signal is decoded, and the decoding operation provides resistance to interference and multi path fading. The spreading or dilution of energy in spread spectrum systems over a wide bandwidth results in several possible advantages, short-range interferences-free overlays on their emissions, and resistance to interference, from other emissions, and low detestability. The low spectral density needed for spread spectrum communication systems, as well as ability of some of these systems

to process signals that are carried far into the noise, offer a potential for shared spectrum use with existing Systems on a non-interference basis. Finally, Spread spectrum systems could be useful in applications to control multi path interference [1] .

II. CDMA OVERVIEW Spread Spectrum communication techniques provide a new method of multiple access, known as CDMA (Code Division Multiple Access) that is proposed as an interesting alternative with respect to the traditional methods, i.e.: the well-known TDMA (Time Division Multiple Access) and FDMA (Frequency Division Multiple Access) [2]. The main parameter in spread spectrum systems is the processing gain the ratio of transmission and bandwidth has shown in equation 1.

i

ip BW

BWG = (1)

The processing gain determines the number of users that can be allowed in a system, the amount of multi-path effect reduction, the difficulty to jam or detect a signal etc. For spread spectrum systems it is advantageous to have a processing gain as high as possible. A PNcode is a sequence of chips valued -1 and 1 (polar) or 0 and 1 (non-polar) and has noise like properties. This results in low cross-correlation values among the codes and the difficulty to jam or detect a data message. Several families of binary PNcode exist, they are addressed in another. A usual way to create a PNcode is by means of at least one shift-register. When the length of such a shift-register is n, the following equation 2 can be said about the period of the above mentioned code-families:

12 −= nDSN (2)

In direct-sequence systems the length of the code is the same as the spreading-factor with the consequence has shown in equation 3:

Proceedings of 11th International Conference on Computer and Information Technology (ICCIT 2008)25-27 December, 2008, Khulna, Bangladesh

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NSp NDSG =)( (3) This can also be seen from figure 1, where it shows how the PNcode is combined with the data signal (NDS=7). The bandwidth of the data signal is now multiplied by a factor NDS. The power contents however stay the same, with the result that the power spectral density lowers.

Figure 1: direct-sequence spreading

The generation of PN codes is a number of shift-registers are all that is required. For this reason it is easy to introduce a large processing-gain in Direct-Sequence systems. The main problem with applying Direct Sequence spreading is the so-called Near-Far effect. This effect is present when an interfering transmitter is much closer to the receiver than the intended transmitter. Although the cross-correlation between codes A and B is low, the correlation between the received signal from the interfering transmitter and code A can be higher than the correlation between the received signal from the intended transmitter and code.

A. General model of a spread spectrum digital communication

The input is fed into a channel encoder that produces an analog signal with a relatively narrow bandwidth around some center frequency. This signal is further modulated using the sequence of digits known as spreading code or spreading sequence. Typically, but not always, the spreading code is generated by pseudo noise or pseudo random number, generator. Figure 2 shows General model of a spread spectrum digital communication [1].

Figure 2: General model of a spread spectrum digital

communication

The effect of this modulation is to significantly increase the bandwidth (spread the spectrum) of the signal to be transmitted. On the receiving end, the same digit sequence is used to demodulate the spread spectrum signal. Finally, the signal is fed in to a channel decoder to recover the data. Spread spectrum uses wide band, noise-like signals. Because spread spectrum signals are noisy they are hard to detect. Spread spectrum signals are also hard to intercept or demodulate. Further spread spectrum signals are harder to jam (interfere with) than narrow band signals due to the increased bandwidth. To qualify as a spread spectrum signal, two criteria should be met: 1. The transmitted signal bandwidth is much greater than the information bandwidth. 2. Some function other than information being transmitted is employed to determine the resultant transmitted bandwidth. B. Pseudo-Random Noise Codes: A PNcode used for DS-spreading exists of NDS units called chips, these chips can have 2 values: - 1/1 (polar) or 0/1. As we combine every data symbol with a complete PNcode, the DS processing gain is equal to the code-length. The sequences must be building from 2-leveled numbers. The codes must have a sharp (1-chip wide) autocorrelation peak to enable code synchronization. The codes must have a low cross-correlation value, the lower this cross correlation, the more users we can allow in the system. This holds for both full-code correlation and partial-code correlation. The latter because in most situations there will not be a full-period correlation of two codes, it is more likely that codes will only correlate partially (due to random-access nature).The codes should be ``balanced'': the difference between ones and zeros in the code may only be 1. This last requirement stands for good spectral density properties (equally spreading the energy over the whole frequency-band). C. Direct Sequence-spread Spectrum Transmitter and Receiver In Direct Sequence-Spread Spectrum the baseband waveform is multiplied by the PN sequence. The PN is produced using a PN generator. Frequency of the PN is higher than the Data signal. This generator consists of a shift register, and a logic

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circuit that determines the PN signal. After spreading, the signal is modulated and transmitted. The most widely modulation scheme is BPSK (Binary Phase Shift Keying) [10]. Figure 3 shows the PN Generator Block Diagram.

Figure 3: PN Generator Block Diagram The equation 4 represents this DS-SS signal.

)2cos()()(2 θ+Π= tftptmTES cs

sn

(4)

where m(t) is the data sequence, p(t) is the PN spreading sequence, fC is the carrier frequency, and θ is the carrier phase angle at t=0. Each symbol in m(t) represents a data symbol and has a duration of Ts. Each pulse in p(t) represents a chip, and has a duration of Tc. The transitions of the data symbols and chips coincide such that the ratio Ts to Tc is an integer. The waveforms m(t) and p(t) are shown in fig. 5. Here we notice the higher frequency of the spreading signal p(t). The resulting spread signal is then modulated using the BPSK scheme. The carrier frequency fc should have a frequency at least 5 times the chip frequency p(t). In the demodulator section, there has been simply done reverse the process. We Demodulate the BPSK signal first, Low Pass Filter the signal, and then despread the filtered signal, to obtain the original message. The process has shown in equation 2.1. In the demodulator section, we simply reverse the process. Demodulate the BPSK signal first, Low Pass Filter the signal, and then despread the filtered signal, to obtain the original message. The process has been described in equation 5 [3] .

θ+Π×= )2cos()()( tftstm css (5)

Figure 4: DS-SS Transmitter Block Diagram

Figure 5: m(t) and p(t) for a Maximum Length PN

)]24cos(1[21)()(2)( θ+Π+= tftptm

TEtm ci

i (6)

As shown in equation 5 and 6 when we multiply two cosine signals together, we will obtain two expressions, one of which has twice the frequency of the original message. And this part can be removed by a LPF. The output is )( tm ss as shown in figure 5. This design is based on Coherent Detection BPSK, so we don’t have to worry about carrier synchronization issues. Basically we have tried to construct the modulated part in our project. But for receiving data we have designed the Demodulator circuit by the software of ‘Electronic Workbench’. As for the PN sequence in the receiver, we mentioned earlier that it should be an exact replica of the one used in the transmitter, with no delays, because this might cause severe errors in the incoming messages. Again, my design is based on the idea that PN sequences are matched, and actually we are going to use the same generator for both to ease the design. There are various techniques that deals with PN delay problems and mismatches, but we are not going to encounter any in this design [4] . After the signal gets multiplied with the PN sequence, the signal dispreads, and we obtain the original bit signal m(t), that was transmitted. The block diagram of the receiver is shown in figure 6 [5] .

Figure 6: DS-SS rece iver

This simple straightforward description of DS-SS systems, will allow us to design the Modulator

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circuits with some ease. We are going to take advantage of the block diagrams for each one of them.

D. The Direct sequence spread spectrum Modulator Design:

In this chapter, we are going to illustrate the circuit design and show the simulation of the DS-SS Modulator (Transmitter). Simulations were conducted using the EWB (Electronics workbench) software and also Hardware. Ideal components were used for the ease of the design, and to try to avoid other factors, that might directly affect the performance of the system. And since we are going to design a simple circuit for educational purposes, we decided to use the ideal components offered inside the software although I constructed it in hardware[9] . E. The PN Generator Design

The design of the PN generator is based on the block diagram shown in figure 7. Here we are going to need 4 D–Flip–Flops (FFs), a XNOR gate, and a Clock source. Since we are using 4 FFs, m=4 and the PN signal will repeat every 15 clock cycles. We have chosen the CLK frequency, fCLK=100 KHz. The period of the PN chip is TPNchip = 1/100k =10-

5 seconds. The total period of the PN sequence TPN = 15*TPN = 510*15 − seconds. The period of the Binary Input signal (per bit) is going to be Tb = TPN=15* 510− seconds, that is a frequency fb= 6.6667 KHz. The Clock signal was taken from an external source (a Function Generator) [6 , 7] . We can design a clock using an oscillator. But we are not going to go into that. The Circuit that resembles this PN is now easily understood. It is shown in figure 7. In our project we used only PN without data. We can let PN is the data. From this design, the output level from the PN is not 1,-1 as was indicated in the signal diagram of p(t). The output PN sequence is shown in figure 8.

Figure 7: The PN Generator Circuit Diagram.

Figure 8: The PN Signal F. The Input Word Generator Design:

The Word Generator Circuit design is based on the one designed and illustrated in equation 6. The Word Generator consists of two ICs, an Inverter, a Clock signal with frequency of 6.666KHz, and a DC supply. The 74163 IC is a TTL 4-bit binary counter, and the 74166 is a TTL 8-bit Parallel-In/Serial-Out Shift Register. The Clock signal feeds both ICs as shown in 9. The shift register loads the levels on its inputs when the Parallel Load signal is activated. Then it starts to shift the data, and sends them serially. The Parallel Load signal is taken from a 4-bit binary counter, so that after the counter finishes its count cycle, it will issue the RCO 1 signal, which is used to trigger the shift counter to activate the Parallel Load function. There would be obtaining a controllable 8-bit periodic Word Generator signal. The Signal obtained is shown is figure 10. The 8-bit Word is then multiplied by the PN signal. In the block diagram there has been used a NRZE 2 to adjust the Word level voltages. Now, assuming that we are using the NRZE, the output of the multiplier given the word signal shown in figure 10.

Figure 9: The 8-bit Generator Circuit diagram with a

data rate (period of one bit)of 6.666 KHz

Figure 10: The 8-bit word signal.

There has been seen the PN signal affects the incoming word signal that is 1/15 of its frequency.

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When a • 5 is multiplied with a +5 the result is • 25. And when a • 5 is multiplied by a • 5 the result is a +25. I mentioned in the previous section that the output of the PN is a 0–5 volts, not a • 5–5 level. Also, the Word levels are 0–5 not • 5–5. This means that i can’t use the multiplication procedure here, because a 0 * 0 is not equal to 1. To overcome this problem, and to eliminate the use of a NRZE for the word signal, i substituted the Multiplier with a XNOR gate. G. The BPSK Modulator Design:

This section illustrates the design of the BPSK modulator. The design is directly based on the block diagram shown in figure 9. Figure 11 shown in BPSK Modulator circuit. The design and simulations are based on the use of ideal components. The BPSK Modulator is based on the idea of changing the phase of the carrier signal whenever the incoming Bit changes its state, for example, if the incoming message changes its state from 0–1, the carrier changes its phase by +180°, and if it changes its state from 1–0 the carrier changes its phase by -180°.

Figure 11: The BPSK Modulator circuit

For the design of BPSK modulator we used two inverting OP-AMP with the gain 1 and also two analogue switch and one inverter. At operation of the BPSK, the carrier signals are entered into the OP-AMPs through the analog switches which are active at the positive pulse. So switches are controlled by the data. When PN is +ve, the switch one is on and the signal pass and enter into the 1st OP-AMP it inverts this signal [8]. At the same time 2nd switch remains off because it is connected with an inverter. When this signal cross 2nd OP-AMP the signal is inverted again and comes to the original position. On the other hand the 2nd switch will be on when the PN is –ve and it will enter into only the 2nd OP-AMP and invert. In this way it transmits

data. The input carrier frequency used in this design is 5 times fpn chip, which is 500 kHz. But in our circuit implementation we used carrier of 100 kHz if we give more as like simulation, it is difficult to find out the phase shift in the oscillator. Though one can rise the frequency of the signal in wireless applications to end up with a shorter antenna for the devices. Anyway, this isn’t our concern in this report. The modulation process, we finally get the Sss(t) which is the signal obtained from the output of the Modulator circuit. The output of the DS-SS Modulator is shown in figure 12 and precise mode figure 13. Here, a couple of the bits from Sss(t) has illustrate the output signal.

Figure 12: )(tsss The DS-SS signal coming out

Figure 13: )(tsss The DS-SS signal coming out of of

the Modulator (Precise mode). H. Bandwidth consideration of BPSK:

A balance modulator is a product modulator, the output signal is the product of the two input signal. In a BPSK modulator, the circuit output signal is multiplied by the binary data. If +1V is assigned to a logic 1 and -1V is assigned to a logic 0, the input carrier (sin ωct) is multiplied by either a +1 or -1. Consequently, the output signal is either +1sin ωct or -1sin ωct [9 , 10] . This paper described the design of the modulation technique of direct sequence-spread spectrum with its hardware implementation. It also describes the characteristics of BPSK modulator. There has been found the circuit’s output characteristics and the BPSK modulated signal’s characteristic is same

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although a fault was found in our circuit’s OP-AMP (at BPSK modulator circuit). As in obvious form the observed out put and simulated out put there is same anomaly. The amplitude of the observed output (fig 14) is not uniform all along. There are sudden jumps in the output wave shape. The cause of these jumps may be manufacturing non uniformly of the integrated circuits.

Figure 14: Circuit’s output

In the physical structure, it has been used available components. Firstly there has been first designed it by the simulation software named EWB (Electronics Workbench). There also has been designed the Demodulator circuit with the software and it works successfully.

Figure 15: DS-SS receiver circuit diagram

Figure 14 shows the diagram of the filter (the Sallen-Key second order active filter) and figure 15 shows the full diagram of the demodulator circuit. One who is interested as for Multiplier (Balance Modulator) he can use MC1496 IC. Here all equipments are common and available. Finally, hope that this report has supplied you with some new information, techniques, and ideas. Again, it is intended to be as an educational supplement for any advanced communications course, where the student wants to see a practical application on what is studying.

III. Conclusion This paper demonstrated the design of a simplified Direct Sequence Spread Spectrum CDMA system. Design of 8-bit word generator is given. Spreading technique is clearly implemented. Finally, original data are recovered by dispreading in receiver. REFERENCES [1] “An Introduct ion to Direct -Sequence

Spread-Spectrum Communica t ions” . ht tp: / /www.cs.c lemson.edu/~westa l l /851/spread-spec trum.pdf

[2] Simon Haykin, “Communication Sys tems” , four th edi t ion, publ ished by JOHAN WILEY & SONS, INC.

[3] “Digita l downconverter /despreader for direc t sequence spread spectrum CDMA communicat ions sys tem”. ht tp : / /www.patentstorm.us/patents/6141372-descr ip t ion.html

[4] “Acquisi t ion o f Direct Sequence Spread Spec trum Acoust ic Communica t ion Signals” . ht tp : / /www.mit .edu/~mill i t sa /resources /pdfs/acq.pdf

[5] Samuel C. , Yany, “CDMA RF System Engineer ing”, F ir st edi t ion

[6] “Supplementa l Text Book of CDMA-One Basic Technologies” Training text book-FUJITSU, July 2000.

[7] “CDMA Technology Resources : Welcome to the wor ld o f CDMA: Common air in ter face” 2003 CDMA Development group ht tp: / /www.cdg.org/ technology/index.asp) .

[8] “COFDM as a modula t ion technique o f wire less te lecommunicat ion wi th a CDMA comparison” Thesis-Erc Lawrey-1997

[9] J .K. Thomacy “Digi ta l co mmunicat ion sys tem”.

[10] S.L. Gupta & Dr. V. Kumar “Handbook of electronics”, 31st revised and enlarged edition.

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