VLSI Design06-88-531

Assignment #1

Design, Characterization and Use of Custom Standard Cells

June 29, 2014

Submitted By:

School of Electrical Engineering

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1. Introduction:This report presents design, characterization and simple tests of standard logic cells in VLSIdesign. All tasks including layout design, characterization and testing are done in Cadence dfIIsoftware tool using 180nm technology.

1.1 DesignThe general outline of a cell is shown in Fig. 1. Power supply and ground rails are 0.32um thickand placed respectively at the top and bottom of the cell. Rail to rail inclusive height is 7um.Width of a given cell varies depending on the gate being implemented and the number oftransistors used. Input and output connections are deliberately placed just above/below grid linesso that multiple cells can be cascaded horizontally when building larger logic circuit. Alsowhenever possible the output is provided at two places for convenience of cascading.Input/output connection runs are 0.38um thick.

Since p-type material has lower mobility, pMOS transistors are designed to be about 2.6 timeswider than nMOS ones. Exact transistor lengths, widths and spacings are varied across differentgates, but they are kept minimum without violating DRC rule.

NOT, 2NAND, 2NOR and 2XOR logic gates are designed in this work. Using these as buildingblocks a full-adder is then designed. Detailed layout, sizes, characterization and test results arereported.

Fig. 1: General outline of a gate design.

1.2 CharacterizationEach cell designed implementing a particular logic gate is first tested for correct functioningusing test waveforms as input. Further it is characterized by some standard metrics. Theseinclude DC characteristics, capacitance, propagation delay, rise/fall time, and power dissipation.

1.2.1 DC CharacteristicsDC characteristic also called transfer characteristic is the plot of output voltage against the inputvoltage. This is done in SPICE in the form of DC analysis by sweeping the input voltage fromzero to 1.8V (supply voltage) in a small increment. At the same time the total current drawn bythe gate can be measured and plotted to see the power dissipation characteristics.

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1.2.2 CapacitancePower dissipation and speed of a gate depend largely on its load capacitance. Since the load isoften another gate, the load capacitance is a sum of input capacitance of the driven gate, parasiticcapacitance and the capacitance due to wire. In this assignment the focus is on the inputcapacitance as wire capacitance is relatively difficult to calculate and the parasitic capacitance isreadily available in MOS models.

To estimate the input capacitance I setup a test circuit of a gate loaded with 4 other same gates.Fed with the same signals another gate drives a capacitive load. The capacitance is varied untilboth outputs are reasonably matched. One fourth of the capacitance will represent the inputcapacitance of the driven gate.

1.2.3 Propagation DelayPropagation delay or simply the delay is the time difference between input and correspondingoutput signal of a gate. The delay is caused by various capacitance, and needs to be estimated. Asthe output signal waveform is almost always different from the input one, one needs to define thedelay in exact terms. A generally accepted rule is: take 50% voltage level of both the input andoutput signals and note the time delay between them at that level during rising. The exact methodof comparing waveforms is the same as the one reported in the Cadence Tutorial.

1.2.4 Rise and Fall TimeWhen there is a finite load the output of a gate does not change as fast as the input changes. Risetime quantifies how fast or slow a signal rises from zero to the maximum voltage. In present caseit is the time to rise from zero to 1.8. However, as there are noise margins in input and outputsignals, exact zero is impractical, and often a 10% to 90% level is considered. Some studiesconsider 20% to 80% level. Similar to rise time, fall time measures the time a signal takes to gofrom high to low. High and low levels are defined similarly.

In this assignment rise/fall times are recorded for both 10-90% and 20-80% levels. The actualmethod of calculating the time is the same as one shown in the Cadence tutorial.

1.2.5 Power DissipationCMOS gates dissipate almost no power when in stable logic levels. However, during thetransition from 01 and 10 both the nMOS and pMOS transistors conduct thusdissipating a power. To keep the power dissipation minimum, the transition time should be asshort as possible, meaning the operating frequency or the load to a gate can not be excessive.Power dissipation is estimated using the same circuit setup and method as described in theCadence tutorial.

1.2.6 Power SupplyThe TMSC 180nm technology has a nominal supply voltage of 1.8V. I will reduce the supplyvoltage and see if the gates still function properly.

For all test setup, the primary ( A) input signal has a rise and fall time of 200pS, pulse duration of3.6nS and a total pulse width of 8nS. Secondary signal (B) is either a delayed version of A orfixed high/low voltage levels.

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2. NOT Gate:The layout of the not gate is shown in Fig.2a. Input and output waveforms are shown in Fig. 2b.The sizes of the nMOS and pMOS transistors are shown in Fig.2c. For nMOS, length = 0.18um,width=0.22um, and for pMOS length=0.18um, width=0.57um (which is approximately 0.22umtimes 2.6).

Fig. 2: NOT gate cell layout, size, and the input/output waveforms.

I assume that the n-well for pMOS will be merged horizontally with others, and be at about 1umdistance from any ground rails of another cell row on the up side. Ignoring the banks of n-wellthe overall cell area is about 7um x 2.5um = 17.5 um2.

Transfer characteristic of the NOT gate as well as the trans-conductance curves are shown in Fig.3. We note that the transfer curve is not symmetrical about 0.9V. Also to note the rise time (wheninput voltage is > 0.9) is slower than the fall time (input voltage < 0.9). This is due the fact thatpMOS has relatively higher resistance. Making the pMOS transistor 2.6 times wider still doesnot make the response fully symmetrical. This is probably a weakness of the extractionalgorithm.

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Also to be noted the DC characteristics do not change if the parasitic capacitors are taken intoconsideration.

Fig. 3: Output voltage and circuit current vs the input voltage.

Characterization data for the NOT gate are furnished in the Table 1.

Table. 1. Characterization data of NOT gate

Metric

Measured valueChange%Without parasitic capacitor With parasitic capacitor

Input Capacitance, fF 1.55 2.45 58Delay (at 50%), pS 34.08 47.04 38Rise time, pS 10%-90% 83.42 99.53 19

20%-80% 52.93 62.25 17Fall time, pS 10%-90% 66.77 78.36 17

80%-20% 45.05 53.02 17.6Power consumption, uW 1.78 2.28 17.7Minimum supply voltagerequired, V

0.8 0.9

The rise time is about 15-20% longer than the fall time. This is due the lower mobility of p-typematerial.

Parasitic capacitance causes the rise and fall times to increase by about 17%. The overall delay at50% level is about 38% longer due to parasitic capacitance. Ideally the gate capacitance shouldnot change with parasitic capacitance, but in this test setup I found the input capacitance haschanged too.

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3. NOR Gate:CMOS circuit of a 2-input NOR gate is shown in Fig. 4a. The layout of the gate is shown in Fig.4b. Sizes of nMOS and pMOS are the same as the not gate. Approximate cell area is 7um x3.75um. Test waveforms with a simple setup are shown in Fig. 4.c. Characterization data of thegate are given in Table 2.

Fig. 4: Circuit diagram, cell layout and test waveforms for NOR gate.

Propagation delay, rise/fall times and power consumption all depend on the input values. If bothinputs are shorted and fed the same signal, the NOR gate acts like an inverter. As the pMOStransistors are in series, they both must be ON before the load capacitor gets charged. This meansthe rise time is longer. The fall time is however shorter as both the nMOS transistor are inparallel offering a low resistance discharge path.

When one input (say B) is held at logic LOW while a signal is fed to the other input (A) the gatestill acts as an inverter. But as one pMOS is now always ON, the rising time is slightly shorter.As one of the nMOS transistors is now switched off, the resistance of the discharge path is nowhigher meaning longer fall time.

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Table. 2. Characterization data of the NOR gate

Metric

Measured value%diffmean

Without parasitic capacitor With parasitic capacitorB=A B=0 Mean B=A B=0 Mean

Input Capacitance, fF - 1.62 - - 2.10 -Delay (at %50 ), pS 68.5 61.6 65.05 83.35 73.0 78.2 20Risetime, pS

10%-90% 194.4 164.6 179.5 229.2 186.9 208.1 1620%-80% 129.8 103.3 116.5 155.05 116.1 135.6 16

Falltime, pS

10%-90% 60.02 72.47 66.2 67.76 81.0 74.4 1220%-80% 40.67 50.3 45.5 46.2 54.94 50.6 9

Power consumption,uW

2.76 2.12 2.4 3.3 2.44 2.8 17

The average rise time for NOR gate is higher than the fall time by factor of about 3. This issignificant. The effect of parasitic capacitance is an increase of about 16% in rise time. The falltime is however is less affected by the parasitic capacitance, about 10% increase. Powerconsumption increases by 17% due to parasitic capacitance; as in the NOT gate.

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4.NAND Gate:A circuit of a CMOS NAND gate is shown in Fig. 5.a. Cell layout of the same is shown in Fig.5b. Sizes of nMOS and pMOS transistors are the same as the not gate. Approximate cell area is7um x 3.5um = 24.5 um2 (ignoring n-well banks). Test waveforms with a simple setup are shownin Fig. 5.c. Characterization data of the gate are given in Table 3.

Fig. 5: Circuit diagram, cell layout and waveforms of NAND gate.

Like NOR gate, the propagation delay, rise/fall times and power consumption of NAND gatedepend on the input values. If both inputs are shorted and fed the same signal, the NAND gateacts like an inverter. As the pMOS transistors are in parallel, when both are ON, the effectiveresistance is lower that causes the load capacitor gets charged relatively quickly. This means therise time is quicker. The fall time is however longer as the two nMOS transistor are in seriesoffering a a higher resistance discharge path.

When one input (say B) is held at logic HIGH while a signal is fed to the other input (A) theNAND gate still acts as an inverter. However, as one nMOS is now always ON, the fall time isslightly shorter. But as one of the pMOS transistors is now switched off, the resistance of thecharging path is now higher meaning higher rise time.

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Table. 3. Characterization data of the NAND gate

Metric

Measured value%diffmean

Without parasitic capacitor With parasitic capacitorB=A B=1 Mean B=A B=1 Mean

Input Capacitance, fF - 1.7fF - - 2.15fF -Delay (at %50 ), pS 59.8 56.5 58.2 72.52 65.3 70.4 19Rise time,pS

10%-90% 82.76 102.2 92.3 89.5 111.9 100.7 920%-80% 50.92 64.4 57.7 57.09 70.86 63.9 10

Fall time,pS

10%-90% 120.2 92.8 106.5 140.07 103.8 121.9 1420%-80% 77.1 61.6 69.4 91.0 68.8 79.9 15

Power consumption, uW 2.92 2.32 2.62 3.4 2.65 3.03 15

The average rise time for NAND gate is shorter than the fall time but only by a small percentageof about 15%. This is significantly different from the behaviour of NOR gate. The effect ofparasitic capacitance is an increase of about 10% in rise time. The fall time is however is moreaffected by the parasitic capacitance, about 15% increase. Power consumption increases by 15%due to parasitic capacitance. In general the NAND is found to consume slightly more powercompared to the NOR gate.

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5. XOR Gate:The circuit diagram and cell layout for XOR gate are shown in Fig. 6 and Fig. 7 respectively.The XOR cell has a height of 7um and width of about 11.5um. Transistor sizes are the same aspreviously designed gates. Characterization data for the XOR gate are compiled in Table 4.

Fig. 6: XOR circuit diagram.

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Fig. 7: Cell layout of XOR gate.

Fig. 8: Input/output waveforms of XOR gate.

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Like NOR and NAND gates the rise/fall times, delay and power consumption of XOR gatedepend on the data inputs. In my test setup, the B input is held to LOW and HIGH in turn while asignal is applied to the input A and data collected.

When one input is held at LOW, the XOR gate acts like a non-inverting buffer. If one input isheld at HIGH, the XOR gate acts like an inverter.

Table. 4. Characterization data of the XOR gate

Metric

Measured value%diffmean

Without parasitic capacitor With parasitic capacitorB=0 B=1 Mean B=0 B=1 Mean

Delay (at %50 ), pS 144.50 128.9 136.7 195.25 156.5 175.8 28Rise time,pS

10%-90% 212.57 244.96 228.7 277.34 298.9 288.1 2520%-80% 145.73 162.78 154.3 190.65 209.47 200.1 29

Fall time,pS

10%-90% 115.4 159.9 137.6 151.4 193.4 172.4 2520%-80% 77.76 107.4 92.5 100.9 128.59 114.7 24

Power consumption, uW 4.69 5.35 5.02 6.16 6.72 6.44 28

Like a standard CMOS gate the falling time is slightly shorter than the rising time. The effect ofparasitic capacitance makes the gate approximately 30% worse.

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6. Full Adder:I implemented the full adder using XOR, AND and OR gates. Since I had only NAND and NOR, a NOT gate is attached to theiroutputs to respectively make AND and OR. The logic diagram is shown in Fig. 9.

sFig. 9: Full adder logic diagram.

The cell layout for full adder is shown in Fig.10. Cell area is 43um in width and 7um in height.

Fig. 10: Full adder cell layout.

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Sample input/output waveforms for the full adder is shown in Fig. 11. Though the sum outputlooks fine, the carry out has occasional glitches. Later the full-adder is modified so that it doesnot produce any glitches.

Fig. 11: Input/output waveforms of the full adder.

Characterization data for the adder are furnished in Table 5. Like NOR and NAND gates, therise/fall times, power consumption etc depend on the input values. One representative scenario issetting input B and Cin to opposite values (say B=0, Cin=1) and feeding a signal to input A. Dataobtained under this scenario are given in the following table.

Table. 5. Characterization data of the full adder.

B=0, Cin=1

Metric

Measured valueWithout parasitic

capacitorWith parasitic

capacitor%difference

Sum

Delay at 50% 303.6 410.6 35Risetime, pS

10%-90% 284.1 363 2720%-80% 197.1 250.5 27

Falltime, pS

90%-10% 199.3 265.5 3380%-20% 137.8 180.2 30

Cou

t

Delay at %50 304 411.1 35Risetime, pS

10%-90% 40.26 49.3 2220%-80% 24.5 30.5 24

Falltime, pS

90%-10% 41.4 53.3 2880%-20% 28.4 36.8 29

Power consumption, uW 18.18 24.1 32

Rise/fall times of the carry out are much quicker than the sum out but the propagation delays arealmost of same order. The power dissipation of the adder is just about the sum of the powerdissipation of individual gates.

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7. Improving the Full adder:Careful examination of the gate diagram in Fig. 9 reveals that the two signals arriving at the inputs of the NOR gate have unequaldelay. One input comes directly from the output of NAND-NOT pair which is fed with inputs A and B. However, the other inputcomes from the NAND-NOT pair one input of which is the output of an XOR gate. As XOR gate has about 4 times longerpropagation delay compared to an inverter, the final carry out is only meaningful when the sum output is valid. The glitch in carry outoccurs when there is a carry out due to Cin=1 (and A=B=1), and the sum output changes state from 1 to 0 (due to either A or Bchanging from 1 to 0). The carry out is still 1, but during the transition, there is a short circuit current that momentarily pulls downCout.

Following a rough count based on [1] the bottom path in Fig. 9 needs about 4 units of delay to make the inputs of NOR arrivingapproximate at the same time. This will not delay Cout, it will cause the NOR to hold the value. In the modified full adder I will insertfour inverters in the designated path. A screen-shot of the modified cell is shown in Fig. 12. Cell area for the improved adder is 7um X54um.

Fig. 12. Cell layout of the improved full adder.

A test setup of the improved full adder is shown in Fig. 13. The test also includes the original full adder for easy comparison.Waveforms from the test setup are shown in Fig. 14. For brevity I have omitted the fixed signals B and Cin. Note that the originalCout has itself pulled down to about 0.75V, bellow the gate threshold of 0.9V (Vdd/2). The carry out of the improved adder Cimpmaintains the voltage level of 1.8, other than a few transients of amplitude less than few millivolts.

Characteristics of the improved adder are mostly same as the original adder except when the inputs are all 1s. In this case the adderconsumes some extra power. Table 6 furnishes the power consumption data for the improved adder. The power dissipation for theoriginal adder shown in Table 6 is 26.89uW (36.72 when considering parasitic capacitance) which is slightly different from the valuesreported in Table 5. This is purely due to the input data pattern. For Table 6 B and Cin B are set to 1 whereas for Table 5, B=0 andCin=1.

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Fig. 13. Test setup for the improved full adder.

Fig. 14. Waveforms of the improved full adder (B=1, Cin=1).

Interestingly, the improved adder in fact consumes lower power than the original adder whenconsidering the effect of parasitic capacitance.

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Table 6: Power consumption of the improved full adder.

B=1, Cin=1Measured value

Without parasiticcapacitor

With parasiticcapacitor

%difference

Original adder, uW 26.89 36.72 36Improved adder, uW 28.58 34.18 19

8. Vertical vs horizontal cascading:One might think that cascading the cell blocks in horizontal direction will require long runs ofmetal connections which will increase both wire capacitance and resistance. However in mydesign I placed the pin inputs in such a way that major wire runs are of almost same lengths. Torefute the idea I have built another full adder cell with the gate cells stacked vertically as well ashorizontally so that the overall cell has a somewhat square shape. A screenshot of the vertical fulladder is shown in Fig. 15.

Fig. 15: Square shaped full adder layout.

Characterization data for the vertical design is shown in Table 7. Comparing with Table 5 itappears that the vertical design in fact slightly worse than the original horizontal design.

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Table. 7. Characterization data of the vertical full adder design.

B=0, Cin=1

Metric

Measured valueWithout parasitic

capacitorWith parasitic

capacitor%difference

Sum

Delay at 50% 303.4 418.4 37Risetime, pS

10%-90% 282.5 372.2 3120%-80% 196.7 260.6 32

Falltime, pS

90%-10% 198.4 267.9 3580%-20% 123.2 183.5 48

Cou

t

Delay at %50 303.9 418.6 37Risetime, pS

10%-90% 40.2 49.1 2220%-80% 24.7 30.6 23

Falltime, pS

90%-10% 41.5 54.1 3080%-20% 28.3 36.8 30

Power consumption, uW 18.18 24.57 35

Summary:In this assignment I designed NOT, NOR, NAND, and XOR gates using TMSC 180nmtechnology using Cadence dfII tool. The gates are tested and characterized in detail. Then I builta full adder using the gate cells as building blocks. The full adder is also tested and characterized.An improvement is then made to avoid glitch in carry out by adding additional delay in a path.The improved design consumes almost the same power on average. Finally a comparison is madebetween horizontal and vertical design. I found that careful pin placement and routing are theimportant factors: vertical design is not necessarily better than the horizontal one.

References:[1] Neil H. E. Weste and David M. Harris, CMOS VLSI Design, 4th Ed., Addison-Wesley.