digital control of power converters - upm · digital control of power converters 31 z-transform...

2 Digital controller design

DIGITAL CONTROL OF POWER CONVERTERS

Digital control of Power Converters 2

Outline

▪ Review of frequency domain control design

Performance limitations

▪ Discrete time system analysis and modeling

▪ Digital controller design

Review of frequency

domain control design


Response of linear systems

G(z)

{uk} {yk}

R(z)

{ek} {rk}

-

G(s) R(s)

r(t)

-

e(t) u(t) y(t)

0 1 2 3 4 5 6 7-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1 2 3 4 5 6-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Analog system Discrete system


Review of Continuous system design

|G(jw)|

w G(jw)

G(s) Frequency response

A B

C

A

B

C

u y


Ideal controller

( )y f u z

1( ( ))y f f r z z

y r

f(o) f-1(o)

r(t)

-

e(t) u(t) y(t)

z(t) disturbances

Conceptual controller


Realization of a conceptual controller

h(o)

r(t)

-

u(t)

y(t)

z(t) disturbances

Conceptual controller

f(o)

f(o)

r - h-1u r

The loop implements an approximate inverse of f o, i.e. u = f r, if


Realization of a conceptual controller

h(o)

r(t)

-

u(t)

y(t) f(o)

f(o)

Open loop controller

G(s) R(s)

-

y(t)

Feedback controller

r(t)



G(s) R(s)

r(t)

-

e(t) u(t) y(t) ??

|G(jw)|

w

error 1

1e r

RG

|R(jw)|

|RG(jw)|

wc

For ( ) cwRG s

s ( ) ( )

c

jwe jw r jw

jw w

w=0.1wc |e| 0.1r e

r

w=wc |e| 0.7r

w=10wc |e| r

e

e

The control is useful bellow the loop gain bandwidth

|S(jw)|



G(s) R(s)

r(t)

-

e(t) u(t) y(t)

??

|G(jw)|

w

error 1

1e z

RG

|R(jw)|

|RG(jw)|

wc

w=0.1wc |e| 0.1r e

z

w=wc |e| 0.7r

w=10wc |e| r

e

e

The same effect of feedback for disturbances

z(t) disturbances

z

z

|S(jw)|



▪ The higher the bandwidth the better the performance

w

|RG(jw)|

wc

|S(jw)|

G(s) R(s)

r(t)

-

e(t) u(t) y(t)

??

z(t)



G(s) R(s)

r(t)

-

e(t) u(t) y(t)

??

|G(jw)|

w

|R(jw)|

z(t) disturbances

output

Control effort

1

RGy r

RG

1

Ru r

RG

1u r

GBelow wc

u

High values of u can lead to saturation!!



G(s) R(s)

r(t)

-

e(t) u(t) y(t)

??

n(t)

noise

referene

Noise

1

RGy r

RG

1

RGy n

RG

Noise and reference are amplified in the same way

Limit the bandwidth to limit the effect of noise


Stability margins and sensitivity peak

▪ If G0 is stable

▪ Stability is assured if R·G does not enclosed -1

Gain and Phase Margins Peak Sensitivity

Z = N + P


Stability margins

The gain margin, Mg, and the phase margin Mf are defined as:

Peak sensitivity:

S0 is a maximum at the frequency where G0(jw)R(jw) is

closest to the point -1. The peak sensitivity is thus 1/

1,

1S

GR


Stability margins in Bode diagrams

0G R

G(s) R(s)

-

y(t) r(t)

Useful Control Action


Performance limitations: Bode’s Integral constraint

G(s) R(s)

-

y(t) r(t)

for an open loop stable plant, the integral of the logarithm of the closed loop sensitivity is zero; i.e.

0 0 0|)(|ln dwjwS

0.01 0.1 1 10 10010

5

0

2

10

S.2frsp1

1000.01 S.1frsp0

+

-

Equal areas



G(s) R(s)

-

y(t) r(t)

0.01 0.1 1 10 100 50

0

50

100

Loop gain

0.01 0.1 1 10 10040

30

20

10

1.321 105

40

S.1frsp1

S.2frsp1

1000.01 S.1frsp0

Sensitivity function

Improved performance at low freq

Worse performane around bandwidth


Sensitivity dirt

1

Slog

w


▪ Physical interpretation

0 0 0|)(|ln dwjwS


Effect of RHP zeroes and poles

To avoid large frequency domain sensitivity peaks it is necessary to limit the range of sensitivity reduction to be:

(i) less than any right half plane open loop zero

(ii) greater than any right half plane open loop pole.

freq fRHPZ

½ fRHPZ

|RG(jw)|

G(s) R(s)

-

y(t) r(t)

freq fRHPP

2 fRHPZ

|RG(jw)|



This begs the question - “What happens if there is a right half plane open loop zero having smaller magnitude than a right half plan open loop pole?”

Clearly the requirements specified on the previous slide are then mutually incompatible. The consequence is that large sensitivity peaks are unavoidable and, as a result, poor feedback performance is inevitable.


Outline

▪ Review of frequency domain control design


▪ Discrete time system analysis and modeling

▪ Digital controller design


Modelling of discrete systems

Inside the digital processor the system input and output simply appear as sequences of numbers

It therefore makes sense to build digital models that relate a discrete time input sequence, {e(k)}, to a sampled output sequence {d(k)}.

+

ve

-

iC

R

L

iR

+

vs

-

C

iL

ADC

R(z)

{ek} {dk}

vo(t)

H(s)

DPWM

Driver

{vref,k}

G(z) {dk} {vk}

v (t) {vk}

{dk}

PWM

{vk}

v(t)

processor


Sampling and Aliasing

Consider the signal

if the sampling period is chosen equal to 0.1[s] then

the high frequency component appears as a signal of low frequency (here zero). This phenomenon is known as aliasing.

HF

LF


Aliasing effect when using low sampling rate

▪ Rule of thumb sampling rate should be 5 to 10 times the bandwidth of the signals

is chosen equal to 0.1s


Signal Reconstruction

{u[k]}

{u[k]}

DPWM

Sample and hold


Signal reconstruction

▪ Sample and Hold vs PWM

0 2 4 6 8 10 12 140

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

29 Digital control of Power Converters

Typical discretization of G(s)

HO G(s)

Zero-order

Hold Sampler

G(z)

Power

converter PWM ADC

The zero order hold is used to model the PWM

Matlab function:

C2D(G(s),TS,’zoh’)


Discrete systems basics

G(z)

{uk} {vk}

G(s)

u(t) v(t)

{uk}

v (t)

{vk}

sequences Continous functions

u(t)

( 1) ( ) · ( )sv k v k T u k

Integral

00( ) ( ) ( )

t

tv t v t u d

Discrete Integral


Z-Transform

Z-transform for discrete time signals is equivalent to the Laplace transform (s) for continuous systems.

Consider a sequence {y[k]; k = 0, 1, 2, …]. Then the Z-transform pair associated with {y[k]} is given by

Z-transforms have a similar property than the S-transform for discrete time models, namely they convert difference equations (expressed in terms of the shift operator q) into algebraic equations.


Discrete systems basics

sequences Continous functions

( 1) ( ) · ( )sv k v k T u k

Continous Integral

00( ) ( ) ( )

t

tv t v t u d

Discrete Integral

u(t) {uk}

k·Ts

Continous derivative Discrete derivative

{uk} {vk}

sT

kukukv

)1()()(

dt

tdutv

)()(

u(t) {uk}

k·Ts


z-transform vs s-tranform

( ) · k

k

k

X z x z

x(t) {xk}

k·Ts

·( ) ( )· s tX s x t e dt

( 1) ( ) · ( )sv k v k T u k

· ( ) ( ) · ( )sz V z V z T U z

Z-transform

( ) ( )1

sTV z U z

z

Z-transfer function

00( ) ( ) ( )

t

tv t v t u d

0

1 1( ) ( ) ( )V s V t U s

s s

s-transform

1( ) ( )V s U s

s

s-transfer function


Z- transfer function

Ignoring the initial conditions, the Z-transform of the output Y(z) is related to the Z-transform of the input by Y(z) = Gq(z)U(z) where

Gq(z) is called the discrete (shift form) transfer function.


An interesting observation

The Z-transform of a unit pulse is 1

Y(z) = Gq(z)U(z)

Gq(z) {uk} {yk}

G(z) is the z transform of the output when the Input is a unit pulse

0( ) 1·U z z

{uk}={1,0,0…} {yk}


Example of a buck converter

+

ve

-

iC

R

L

iR

+

vs

-

C

iL

ADC R(z)

{ek} {dk}

vo(t)

e (t)

H(s)

DPWM

Driver

vref(t)

G(z) {dk} {ek}

e (t) {ek}

{dk}

PWM



+

ve

-

iC

R

L

iR

+

vs

-

C

iL

ADC R(z)

{ek} {dk}

vo(t)

e (t)

H(s)

DPWM

Driver

vref(t)

G(z) {dk} {ek}

e (t)

{ek} {dk} G(s) ADC H(s) DPWM

{dk} {ek}



+

ve

-

iC

R

L

iR

+

vs

-

C

iL

ADC

R(z)

{ek} {dk}

vo(t)

H(s)

DPWM

Driver

{vref,k}

G(z) {dk} {vk}

v (t) {vk}

{dk}

PWM

{vk}

v(t)



+

ve

-

iC

R

L

iR

+

vs

-

C

iL

ADC

R(z)

{ek} {dk}

vo(t)

H(s)

DPWM

Driver

{vref,k}

v (t) {vk}

PWM

{vk}

v(t)

G(z) {dk} {vk}

v (t)

{vk} {dk} G(s) ADC H(s) DPWM

{dk} {vk}



G(z)

{dk} {vk}

R(z)

{ek}

+

ve

-

iC

R

L

iR

+

vs

-

C

iL

ADC

R(z) {ek} {dk}

vo(t)

H(s)

DPWM

Driver

v (t) {vk}

PWM

{vk}

v(t)

{vk}

-

G(s) ADC H(s) DPWM

{dk} {vk}

discretization


Digital controller design



Analog design Discrete design

vo(t) vref(t)

G(z) {dk}

{vk} {ek}

G(s) ADC H(s) DPWM

{vk}

R(z)

1

2

Design the analog controller

Discretize the analog controller

R(s)

1 Discretize the converter

G(z) R(z)

-

{vk}

2 Design the discrete controller

G(s) R(s)


Discrete controllers design

▪ Good knowledge of averaged models for converters

▪ Complete design in the frequency domain?

▪ Good design practices and experience

Analog design Discrete design

Use this kwoledge as basics and push beyond with digital control


Discrete controllers design

Analog design

1 Design the analog controller

|G(jw)|

w

|R(jw)|

|RG(jw)|

wc

( ) ·(1 )i

z

w sR s

s w

vo(t) vref(t)

G(s) R(s)

zoh

foh

matched

N/A

tustin

Matlab C2D

There are different methods:

Zero order hold or step invariant

First order hold

Pole/zero match

Backward Euler, derivative operator or rectangular integration

Blinear, Tustin or trapezoidal integration

Recommended by Duan, APEC 1999

-

2 Discretize the controller = How to map s poles to z?


Example

v (t)

ADC ZOH G(s) R(z)

vref(t)

-

vo(t) vref(t)

G(s) R(s) -

discretize

digital control of power converters - upm · digital control of power converters 31 z-transform...

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