digital logic and state machine designcis.poly.edu/cs2204/vhdlint.pdf · synthesis simulation of...

Introduction to VHDL

Haldun Hadimioglu

Fall 2013

CS2204Digital Logic and

State Machine Design

Fall 2013CS2204 Digital Logic and State Machine Design

OutlineIntroductionLanguage OverviewVHDL DetailsConclusionsFuture Directions

AcknowledgementsJohn Wakerly, Cisco Systems, Stanford UniversityVijay Polavarapu, Polytechnic University

NUDT Tianhe-2 supercomputerFastest computer in world : 3,120,000 cores

1.024 Peta Bytes of RAM memory12.4 Peta Bytes of disk space


IntroductionVHDL is a hardware description language (HDL)

We use VHDL to write a programA VHDL program describes hardware

Just like a schematic describes hardwareA VHDL program describes a chipAn HDL program is used to develop a chip

DesignSynthesisSimulation of chip

Why an HDL program, why not schematics ?Real life circuits are too complex to be designed(described) by schematics

There would be too many and complex schematics

Intel 8-Core Xeon 7500 die with 2.3 billion transistors


IntroductionVHDL was developed in the 1980s under Department of Defense (DoD) sponsorship

Mandated for federally-sponsored VLSI designs

VHDL stands for ?VHSIC Hardware Description Language

VHSIC : Very High Speed Integrated CircuitVHSIC was a DoD research program to encourage research on high-speed integrated circuit (chip) technologies

Today VHDL is widely used across the industry, around the world

Established as IEEE standard IEEE 1076 in 1987Extended in IEEE standard IEEE 1164 in 1993In 1996, IEEE 1076.3 became a VHDL synthesis standard


IntroductionVHDL has ADA flavour

ADA is a software language developed under the DoD sponsorship in the 1980s

Another common HDL language : Verilog HDL

Verilog has C flavour

Knowing one HDL language helps one learn another HDL language faster


IntroductionA VHDL program is a collection of modules

Top-down design (hierarchical designs) for large projects

Designs described at various levels of abstractionMore details at lower levels

Block-based (modular) design

Team-based designEach team member works on a different block (module)

Core-based designComplex blocks (modules) can be licensed as VHDL programs


Language Overview : BasicsSoftware : Statements are executed sequentially

The sequence of statements is significant, since they are executed in that order

Java, C++, C, Ada, Pascal, Fortran,…

Hardware : Events happen concurrentlyA software language cannot be used for describing and simulating hardware

Concurrent software languages cannot be used eitherBecause we do not have powerful tools yet

Programs in C/C++, etc. will be converted to hardware in the futureIt is already done for

MatlabLabVIEWC++Modified C++ language (SystemC)C

First these programs are converted to HDL programs and then to hardware

Catapult C from Mentor Graphicsworks on ANSI C++ and SystemC

Vivado from Xilinx works on C


Language Overview : BasicsVHDL is STRONGLY typed

VHDL is not case sensitive“A” or “a” does not matter

A VHDL program describes a digital system

A digital system consists of blocksA VHDL program is a collection of modules

A module consists of an entity and an architecture

IBM BG/Q supercomputer microprocessor die with 1.47

Billion transistors


Language Overview : ModuleEntity: shows inputs and outputs

The black box view of the module

Architecture : internal description : implementationIt can be written in one of three different detail levels

Structural (very detailed) Dataflow (less detailed)Behavioral (least detailed)


Language Overview : Module

entity declarations

architecture definition

A VHDL programA text file

(caralarm.vhd)

AND

NOTbelt

engine

alarm

A SchematicA schematic sheet

(caralarm.sch)

alarm = engine belt

Sound the alarm if the engine is on and the belt is not fastened


Language Overview : Xilinx VHDL Programs for Car Alarm Circuit

library IEEE;

use IEEE.std_logic_1164.all;

entity caralarm is

port (

engine: in STD_LOGIC;

belt: in STD_LOGIC;

alarm: out STD_LOGIC

);

end caralarm;

architecture caralarm_dataflow of caralarm is

begin

alarm <= engine and not belt ;

end caralarm_dataflow ;

library IEEE;


entity caralarm is

port (


belt: in STD_LOGIC;

alarm: out STD_LOGIC

);

end caralarm;


begin

alarm <= ‘1’ when engine = ‘1’ and belt = ‘0’

else ‘0’ ;


Stru

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iled)

Dat

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(less

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Beha

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Stru

ctur

al (v

ery

deta

iled)

Dat

aflow

(less

deta

iled)

Beha

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east

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Language Overview : Full Adder VHDL ProgramData-flow description of the Full Adder circuit :

FullAdder

ki

misi

ci co

si = ki mi ci + ki mi ci + ki mi ci + ki mi ci

co = ki mi + ki ci + mi ci



Language Overview : VHDL System DescriptionA VHDL program describes a system

A system is a digital systemA system is a collection of

one or more modulesA module consists of

an entity and an architecture


Language Overview : Design Flow

VHDL compiler analyzes VHDL code for syntax errors and checks for compatibility with other modulesSynthesizer converts VHDL program to a circuit with components Place and route fits the circuit to a die


VHDL Details : Entity SyntaxThe entity describes the black-box view

The entity declares portsInputs and outputs

Digital circuit input signalsDigital circuit output signals

Syntax :entity entity-name is

port (signal-names : mode signal-type ;signal-names : mode signal-type ;

….signal-names : mode signal-type)

end entity-name ;

entity caralarm isport (

engine: in STD_LOGIC;belt: in STD_LOGIC;alarm: out STD_LOGIC

);end caralarm


VHDL Details : Architecture Syntax The architecture describes the internal operations

By means of concurrent statements that useSignals inherited from the entityVariables used in functions, procedures and processes

architecture architecture-name of entity-name istype declarationssignal declarationsconstant declarationsfunction definitionscomponent declarations

beginconcurrent statement….concurrent statement

end architecture-name ;

architecture caralarm_dataflow of caralarm isbeginalarm <= engine and not belt ;



VHDL Details : Full Adder Example

architecture architecture-name of entity-name istype declarationssignal declarationsconstant declarationsfunction definitionscomponent declarations

beginconcurrent statement….concurrent statement

end architecture-name ;

entity entity-name isport (signal-names : mode signal-type ;

signal-names : mode signal-type ;…..

signal-names : mode signal-type) ;end entity-name ;


VHDL Details : TypesTypes are required for every

SignalVariableFunction parameterFunction result

Type specifies a set/range of values for an object and a set of operators associated with it

Predefined typesUser defined types

Types must match in Assignment statementsComparisonsFunction calls

IBM BlueGene/L Supercomputer

IBM dual-core BlueGene/L microprocessor die & its chip

© I

BM


VHDL Details : TypesPredefined types

bitbit_vectorbooleancharacterintegerrealstringtime

User-defined typesMost commonly used one : Enumerated types

Intel dual-core Itanium 2 1.72-billion-transistor die & its wafer


VHDL Details : TypesEnumerated type is defined by listing its values

User defined enumerated type :type type-name is (value-list) ;

type COLOR is (RED, ORANGE, YELLOW, BLUE, INDIGO, VIOLET) ;

Subtypes of a type allowed :subtype subtype-name is type-name start to end ;

subtype LONGWAVE is color RED to YELLOW ;subtype subtype-name is type-name start downto end ;

Constants are allowed :constant constant-name : type-name := value ;

constant BUS_SIZE : integer := 32 ;


VHDL Details : Predefined OperatorsBoolean operations

And ANDOr ORNand NANDnor NORxor Exclusive ORxnor Exclusive NORNot Complement

Intel Xeon E7 wafer

Intel Xeon E7 10-core die at 32 nm process with 2.6 billion transistors

AMD Bulldozer 8-core diewith 1.2 billion transistors


Integer operations + addition- subtraction* multiplication/ divisionmod modulo divisionrem modulo remainderabs absolute value** exponentiation

Cray Titan Supercomputer the 2nd

fastest computer in the world with AMD and TESLA chips

VHDL Details : Predefined Operators

World’s densest chip

7.1 Billion transistors

NVIDIA TESLA GPU chip


VHDL Details : LibrariesLibraries keep information about a project

The collection of libraries maintains the state of the design

Intermediate files used in analysis, simulation and synthesisPreviously analyzed entities and architectures

Entity and architecture definitions for different modules can be in different files

IBM Power 7 8–coredie with 1.2 billion

transistors


VHDL Details : LibraryCompiler maintains a “work” library

VHDL compiler generated information about a project

To keep track of definitions via entity and architecture namesIt also contains analysis resultsNo need to explicitly include in the VHDL program

Library work ;

Resource library contains shared definitionsIEEE standard definitions library must be included in the VHDL program

Library ieee ;


VHDL Details : PackageA package contains definitions of objects

SignalTypeConstantProcedureComponent declarations

Standard logic defined by a “package” IEEE 1164 STD_LOGIC

Must be included in the VHDL program

Keyword “use” needed to specify a packageUse ieee.std.logic.1164.all

Uses all definitions in the ieee library containing package std.logic.1164

Intel 8-Core Poulson (Itanium) die with 3.1 billion transistors


VHDL Details : Standard Logic TypesCommonly used IEEE-1164 types:

STD_LOGIC (one bit)STD_LOGIC_VECTOR(range) (multi-bit vector)INTEGER (built-in integer type)

library IEEE;


entity caralarm is

port (


belt: in STD_LOGIC;

alarm: out STD_LOGIC);

end caralarm;


begin

alarm <= engine and not belt ;


Library name

Compiler knows where to find this (system-dependent)

Package name Use alldefinitions in package


VHDL Details : Design Hierarchy LevelsStructural

Explicit components and the connections between them are defined

It is the same as schematic designThe VHDL programmer does schematic design in text

DataflowMost statements are assigning expressions to signals

The tools are heavily involved in converting the text to hardware

BehavioralAn algorithm that describes the circuit’s output is developed

The tools may not be able to convert the text to hardware



VHDL Details : Structural Level

A structural description is just like the schematicAll components and interconnections are described

It is a replica of the schematic !It is not practical !

2-to4DCD

V2to4decI1I0

EN

Y0Y1Y2Y3

Entity Part :



VHDL Details : Structural Description of a 2-to4 Decoder

Architecture Part :

Built-in librarycomponent

All components and interconnections are described Includes component statements

A component statement is a concurrent statementStructural (very detailed) Dataflow (less detailed)Behavioral (least detailed)

2-to-4 Decoder Schematic

Positionalcorrespondencewith component definition


VHDL Details : Dataflow LevelDataflow Description

The detail is less compared with structuraldescription

Data dependencies described, not the components and connections

Concurrency is used to model parallel operations of interconnected hardware elements

Concurrent statements include assignment and selectstatements

“when-else” “with-select”



VHDL Details : Dataflow Description of a 3-to-8 Decoder

Entity Part :3-to-8DCD

A0

G1

Y_L0

A1A2

Y_L1Y_L2Y_L3Y_L4Y_L5Y_L6Y_L7

G2A_L

G2B_L



VHDL Details : Dataflow Description of a 3-to-8 Decoder

All assignment statements operate concurrently

Architecture Part :

3-to-8DCD

A0

G1

Y_L0

A1A2

Y_L1Y_L2Y_L3Y_L4Y_L5Y_L6Y_L7

G2A_L

G2B_L



VHDL Details : 3-to-8 Decoder Translation to Hardware


VHDL Details : Behavioral LevelBehavioral description

May not be synthesizable

May lead to a very large circuit

Primarily used for simulation

Normally uses VHDL “processes”Each VHDL process executes in parallel with other VHDL processes and concurrent statementsBut “sequential” statements can be used within a process



VHDL Details : ProcessSensitivity List

A sequence of sequential statements

Activated when any signal in the sensitivity list changes

Primarily a simulation concept, but can be synthesized



VHDL Details : Behavioral Description of a 3-to-8 Decoder

3-to-8DCD

A0

G1

Y0

A1A2

Y1Y2Y3Y4Y5Y6Y7

G2

G3



VHDL Details : Another Behavioral Description of a 3-to-8 Decoder

May not be synthesizable

May have a slow or inefficient realization

But fine for simulation and verification

3-to-8DCD

A0

G1

Y0

A1A2

Y1Y2Y3Y4Y5Y6Y7

G2

G3



VHDL Details : Is it always VHDL-only System Description ?

One can mix schematic and VHDLXilinx example

1. Start a schematic project2. Write a VHDL program3. Convert the VHDL program to a Xilinx

macro (Custom Design Block, CDB)4. The macro is appended to the component

library list5. Place the CDB in the schematic just like

any other Xilinx component


ConclusionsVHDL simplifies design of complex digital circuits

VHDL allows core-based, top-down, team-based design

VHDL and other HDLs will be used in foreseeablefuture as chip densities increase

Sophomores will learn more VHDL/Verilog HDL in the future

Eventually, C/C++/Matlab/LabVIEW/Java/… programs will be converted to hardware

We will use C/C++/Matlab/LabVIEW/Java/… to design chips

The key is developing powerful CAD tools


Future Directions : Moore’s Law will Continue to HoldPerhaps at a slower rate of doubling every three years

www.

ieee

.org


Future Directions : Intel ‘s Past Roadmap

Intel 62-core Xeon Phi processor 2012 5,000,000,000

AMD Tahiti GPU chip with 4.313 Billion transistors


Future Directions : Power Density a Major Concern !W

atts

/cm

2

1

10

100

1000

i386i486

Pentium® Pentium® Pro

Pentium® IIPentium® IIIHot plate

RocketNozzleRocketNozzleNuclear Reactor

Courtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro32 conference key note - 1999. Courtesy Avi Mendelson, Intel.

Pentium® 4

Power was doubling every 4 years

Power Density was Increasing Exponentially !


Power Density was Increasing Exponentially !

Future Directions : Power Density a Major Concern !ww

w.na

nowe

rk.c

om


Future Directions : Microprocessor speedThe microprocessor speed was doubling every two years until multi-core processors emerged

The processor speed was increasing 50% a year !But, memory speed has been increasing 10 % a year !

Microprocessor speed for an application depends onNumber of operations in the application (lower better)

The quality of the codeNumber of parallel operations performed (higher better)

Do more operations in parallelPerform each operation faster

Because of Moore’s Law : transistors are smaller and wires are shorterHigher clock frequencies

Until 2005 increasing the clock frequency was the main way to increase the speed

Power consumption (heat generation) increases with the frequencyHeat generation increases with the power consumption

The chip has to be cooled byA heat sink or a fan or a liquid

Since 2005 power consumption changed way to increase speed


Future Directions : Multi-Core MicroprocessorsSince 2005 microprocessor speed increase depends on

Number of operations in the code (the quality of the code)Number of parallel operations performed

Multi-core microprocessors with reduced frequency consume less power (generate less heat)

Two/Four/Eight cores perform more operations in parallelThe speed increase continues into the future with more cores on chip

Clock frequencyNumber of cores per chip doubles every two years

The memory can become a bottleneckThe memory speed increases 10% a yearMore cores increase the demand on the memoryThe memory wall problem

Parallel Programming has to be improved dramaticallyParallel programming wall


Future Directions : Multi-Core Microprocessors Double number of cores every two years

Parallel programming Wall

Make sure to handle

Memory Wall

Power Wall

Make sure to handleerrors due to

Alpha particles, neutrons

Defective transistors


Future Directions : Intel & IBM Vision for Next 5-8 Years

From

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IBM

Intel


Future Directions : Next 5-8 YearsApplications

Intel : Recognition, Mining, Synthesis as platform 2015Workload Model (on massively parallel core chips)IBM : Presence information, knowing where and things are and how to best match them, people are sensorizedMicrosoft : Intention machine, computer predicts user intentions and delivers useful informationCMU : Computational thinking, computer science based approach to solving problems, designing systems, understanding human behavior

Traditional computing will continueA C/C++/Java/.. program for an application becomes Software

A compiler generates the machine language program fileA new type of computing

A C/C++/Java/.. program for an application becomes HardwareA hardware compiler generates the GDS II file (the chip layout)

The result is a custom chip


Future Directions : New Computing Types ?Any other new possibility ?

A C/C++/Java/.. program for an application becomes HardwareA CAD tool generates the bit file to reconfigure the FPGA

There can be more opportunities with FPGA chips !They are increasingly used in commercial products !

FPGAs are becoming cost competitive with microprocessorsFPGAs are becoming speed competitive with custom chips

FPGAs are used for applications whereSpeed and programmability matter

Latest FPGAs also have microprocessor coresThey can run software as well

The application is divided into software and hardwareA machine code that is run by the cores andA bit file to program the reconfigurable areas

These cores can be hard or soft coresHard means the manufacturer places a specific core on the dieSoft means the user places any core any where on the die

Hybrid computing


Future Directions : New Computing TypesA C/C++/Java/.. program becomes

Part software and part hardwareFPGA with cores and reconfigurable areas runs applications

Software is run by processor cores andHardware is in the reconfigurable area

When such an FPGA runs an application, some operations are in hardware and simultaneously some operations in software

Software tools (compilers) and CAD tools must mergeReconfigurable areas & cores can allow recovering from errors due to

Alpha particles, neutronsDefective transistors

Processor coreto run softwareReconfigurable area

to do operations inhardware These FPGAs are available

now but we need much better tools

Hybrid computing


Future Directions : New Computing TypesIn summary, in the future a C/C++/Java/.. program that will be converted to

Software (like today)C++ programs become software, the machine codeAll operations happen in software !

HardwareC++ programs become custom chipsAll operations happen in hardware !

Hardware (better than what we have today) C++ programs become hardware, the bit file for an FPGAAll operations happen in hardware !

Part hardware and part softwareC++ programs run on FPGA chips with processors and configurable areasSome operations are in hardware and simultaneously some operations in software

Software is run by processor coresA machine code that is run by processors

Hardware is in the reconfigurable areaA bit file to program the reconfigurable areas


Future Directions : MemcomputingProcessing and memory on the same chip

Passive electronic components that have the memory capabilityBoth processing and nonvolatile memory capability !

Brain like, analog and self-healing computing on a chipMemristors : Components relating electric charge and magnetic flux

The missing fourth electronic componentResistors, capacitors and inductors

They have storage capabilityFPGAs can be implemented with memristors !

MemcapacitorsThey have storage capability

MeminductorsThey have storage capability


Future Directions : Hybrid Switching Elements

CMOL : A circuitry composed of CMOS and molecular nanodevicesA closer look at FPGA-like reconfigurable logic circuits

Interface between CMOS and nanodevices

Two CMOS cells and a nanodevice

A larger view of FPGA-like reconfigurable logic circuits

Figures from :Konstantin K. Likharev


Future Directions : Possible New StructuresMicroelectromechanical systems, MEMS, with computing elements

Microembedded systemsSmart Dust at UC BerkeleyBio MEMS

Micro bio/chemistry lab on a chip ≡ Bio chipCamera pill to make diagnosis in the bodySugar level detector in bloodstreamOptical sensor in the retina to restore vision

The BiochipGroup at Mesa+

IBM lab-on-a-chip to test diseases and viruses

UC Berkeley Sensor & Actuator Center


Future Directions : Possible New StructuresMicroelectromechanical systems, MEMS, with computing elements

Other structures that can be used for a number of different applications withor without computing elements

MicromotorsMicrocamerasMicromirrorsMicrolensesMicrosensorsMicromachines

www.microfabrica.com

An all-optical computing chip with micromirrors and microlenses ?


Future Directions : Possible New StructuresNanotechnology

Programmable materialsNEMSBio NEMS

Nano medicineDrug deliverySmart diagnosis

Nanocomputing1 Watt supercomputer

Quantum computingMolecular computing

Molecular self assemblyTesting of molecular structuresAdaptive molecular structures

Merger of bio and non-bio structuresSynthetic biology

www.

ibm

.com

IBM Blue Gene/L molecular dynamics demo


Future Directions : New Devices

Only carbon nanotube transistors used

From : Nature, September 25, 2013

The first carbon nanotube computer has been built

IBM’s A brain-inspired computer powered by what it calls “electronic blood”BBC News, October 18, 2013


Future Directions : Possible New Structures

NYU-Poly Research on Protein nanofibers

Jin Montclare of Chemical & Biological Sciences with her colleagues

Protein nanofibers can • Improve drug delivery to treat cancers, heart disorders and Alzheimer's • Aid in the regeneration of human tissue, bone and cartilage

Protein nanofibers could point way to tinier and more powerful microprocessors

Protein-based microprocessors

Bio-degradable microprocessors

• Nanotechnology• Bio NEMS

• Nano medicine• Smart drugs


Future Directions : Year 2020SEMATECH : consortium of semiconductor manufacturers from America, Asia and Europe

SEMATECH predictions for year 2020 (from its 2012 International Technology Roadmap for Semiconductors (ITRS) study)

Clock speed : 5.3 GHzNumber of transistors on a microprocessor chip : 35 Billion32Gbit DRAM chipsProcess length : 11.9 nm

http://www.sematech.orgMake sure to handle errors due to

Alpha particles, neutronsDefective transistors


Future Directions : 2020 and BeyondMany interconnected varying-size computing elements using each other’s results autonomously

Ubiquitous computing with little human interventionCloud computing to nano computing

Personal agentsIntelligent spacesNano medicine

Smart drugsSmart diagnosis

We needSelf-healing, adaptive, self managing, trustworthy, dependablehardware and software

Efficient parallel processingNew computational modelsNew programming languages

Hardware and software reliability

www.

uky.

edu


Future Directions : 2020 and BeyondWill hardware and software be developed separatelylike today ?

How will software be developed for nano systems ?Quantum software ?Molecular software ?

Biosoftware ?How will hardware be developed for nano systems ?

VHDL or Verilog HDL or C or C++ or ?

Iron atomson copper with electronmovement

Developing tools is critical

Simulation of protein molecules folding on a supercomputer


Future Directions : 2020 and Beyond

Thinking ?

IBM Deep Blue 1997Electronic with chips

30 cores + 480 special chips

IBM Watson 2011

Electronic with chips2880 cores & 0.08 PFLOPS

+ 16 TB RAM

A PC in 2020 ?

Electronic with chips

Same rawprocessing poweras human brain20 PFLOPS +

2.5 Peta (1015) -33 Exa (1018)

Bytes


Future Directions : 2020 and BeyondBy 2019 a $1000 computer will match the processing power of the human brain

Raymond Kurzweil, KurzweilAI.net, 9/1/1999His keynote speech at the Supercomputing Conference (SC06) in November 2006

The title of his talk is “The Coming Merger of Biological and Non-Biological Intelligence” Singularity point ?

Brain downloads possible by 2050 Ian Pearson, Head of British Telecom’s futurology unit, CNN.com, 5/23/2005

Computers will be used as virtual brain extensions ?Direct brain - Internet link ?


Future Directions : Longer Term Predictions

Hans Moravec, 1998

Many ethical issues will be facing you ! Being prepared will help !


Future Directions : Science and Engineering for Digital Evolution

Digital Logic evolution will continue :Faster, cheaper, smaller, lighter, less power consuming, higher reliability digital products

Due to converging research in various areas :MathematicsComputer ScienceComputer EngineeringElectrical EngineeringMechanical EngineeringPhysicsChemistryMaterial ScienceBiology ?

There will be many ethical issuesTry to prepare ! Try to be informed !

digital logic and state machine designcis.poly.edu/cs2204/vhdlint.pdf · synthesis simulation of...

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