digital system design (2015)

Digital System Design

Spring in 2015

Short Course for Indonesian Scholars

Presenter by Ying-Shieh Kung

Nguyen Phan Thanh

Risfendra

2

Content

1. Introduction to digital system design (Mar. 11) (by Ying-Shieh Kung)

● Introduction to FPGA

● Introduction to VHDL

● Case study in controller and filter design using VHDL

2. ModelSim/Simulink co-simulation (Mar. 18) (by Nguyen Phan Thanh )

● Introduction to ModelSim Simulation

● Introduction to ModelSim/Simulink co-simulation

● Case study

3. FPGA implementation (Mar. 25) (by Risfendra)

●●●

3

A. Introduction to Case Study

of ModelSim SimulationFor ModelSim 5.7d

Refer from:

• Prof. Ying-Shieh Kung, Teaching Material, 2014.

• Volnei A. Pedroni, Circuit Design and Simulation with VHDL,

Second Edition, The MIT Press, 2010.

Arranged by Nguyen Phan Thanh

Spring 2015 in STUST, Taiwan

4

1. Open a project

(project file)

testbench file

original VHDL code

5

1. Create a new project

6

2. Add vhd file and testbench file

7

3. Compile

8

library ieee;

use ieee.std_logic_1164.all;

use Ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

------------------------------------------

ENTITY counter IS

PORT(

clk, count_ena : IN BIT;

clear, load, direction : IN BIT;

p : IN INTEGER RANGE 0 TO

255;

max_min : OUT BIT;

qd : OUT INTEGER RANGE 0 TO

255);

END counter;

------------------------------------------

ARCHITECTURE a OF counter IS

BEGIN

PROCESS (clk, clear, load)

VARIABLE cnt : INTEGER RANGE 0 TO 255;

BEGIN

IF (clear = '0') THEN -- Asynchrnous clear

cnt := 0;

ELSIF (load = '1' and clear = '1') THEN -- Asynchronous

load

cnt := p;

ELSE

IF (clk'EVENT AND clk = '1') THEN

IF (count_ena = '1' and direction = '0') THEN

cnt := cnt - 1;

ELSIF (count_ena = '1' and direction = '1') THEN

cnt := cnt + 1;

END IF;

END IF;

END IF;

qd <= cnt;

-- Terminal count decoder

IF (cnt = 0 and direction = '0') THEN

max_min <= '1';

ELSIF (cnt = 255 and direction = '1') THEN

max_min <= '1';

ELSE

max_min <= '0';

END IF;

END PROCESS;

END a;

Counter.vhd

9

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-----------------------------------

ENTITY counter_tb IS

END counter_tb;

-----------------------------------------

ARCHITECTURE testbench of counter_tb IS

----- counter declaration ---------------

COMPONENT counter

PORT ( clk, count_ena : IN BIT;

clear, load, direction : IN BIT;

p : IN INTEGER RANGE 0 TO 255;

max_min : OUT BIT;

qd : OUT INTEGER RANGE 0 TO 255);

END COMPONENT;

----- signal declaration -----------

SIGNAL clk: BIT := '0';

SIGNAL counter_ena: BIT := '0';

SIGNAL clear: BIT := '0';

SIGNAL load: BIT := '0';

SIGNAL direction: BIT := '0';

SIGNAL P : INTEGER :=0;

SIGNAL max_min : BIT;

SIGNAL qd: INTEGER;

BEGIN

----- counter_1 instantiation ---------------

Counter_1: counter PORT MAP (clk, counter_ena,

clear, load, direction, P, max_min, qd);

----- Stimuli generation --------------

clk <= NOT clk AFTER 40ns;

clear <= '1' AFTER 0ns;

counter_ena <= '1' AFTER 0ns;

load <= '0' AFTER 0ns;

direction <= '1' AFTER 0ns;

P <= 20 AFTER 0ns;

END testbench;

Counter_tb.vhd

10

4. Simulation

Choose Library tab

Right click “counter_tb => Simulate

Compilation result

11

5. Add waveform

Choose Sim tab

Right click “counter_tb => Add => Add to Wave

12

Setting the simulation time

Change the running time (this case : 500 ns)

13

6. Running

Simulation results

14

7. End Simulation

15

B. Introduction to

ModelSim/Simulink Co-simulation

For ModelSim 5.7d

Matlab 8.0

Arranged by Nguyen Phan Thanh

Spring 2015 in STUST, Taiwan

16

• Chip design using HDL

(Hardware Description Languages)

• High-level tool for designing

high-performance DSP systems

using FPGAs

Matlab Simulink

y=f(x) Co-simulate ModelSim/Simulink

• To verify the functionality

of the HDL correctly match the

system specifications

• Environment for multidomain

simulation and Model-Based

Design for dynamic and

embedded systems

ModelSim

Introduction to ModelSim/Simulink Co-simulation

17

MATLAB AND MODELSIM LINKING

(For the link to work, Modelsim has to be invoked from the command prompt of MATLAB.

For this purpose, MATLAB needs to know the location of MODELSIM)

>> configuremodelsim

Identify the ModelSim installation to be configured for MATLAB and Simulink

Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y

Select a ModelSim installation to be configured:

[1] C:\Modeltech_5.7d\win32 ModelSim SE 5.7d

[0] None

Select ModelSim installation to be configured: 1

Previous MATLAB startup file found in this installation of ModelSim:

C:\Modeltech_5.7d\win32\..\tcl\ModelSimTclFunctionsForMATLAB.tcl

Do you want to replace this file [y]/n? y

ModelSim successfully configured to be used with MATLAB and Simulink

(Step 1)

(Step 2)

(Step 3)

(Step 4)

18

1. Open ModelSim in Matlab main window to make the communication

>> configuremodelsim

Identify the ModelSim installation to be configured for MATLAB and Simulink

Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y

Select a ModelSim installation to be configured:

[1] C:\Modeltech_5.7d\win32 ModelSim SE 5.7d

[0] None

Select ModelSim installation to be configured: 1

Previous MATLAB startup file found in this installation of ModelSim:

C:\Modeltech_5.7d\win32\..\tcl\ModelSimTclFunctionsForMATLAB.tcl

Do you want to replace this file [y]/n? y

ModelSim successfully configured to be used with MATLAB and Simulink

>> vsim('socketsimulink',4449) (Open ModelSim)

MODELSIM/MATLAB SIMULINK CO-SIMULATION

19

2. ModelSim2.1. Create new project

- File => New => Project

- Type “counter” (any project name)

20

2.2. Add vhd file

Co-simulation & Library files

Original VHDL code

(Step 1)

(Step 2: Choose all files)

21

2.3. Add new library- File => New => Library

- Choose “a new library and a logical mapping to it

- At the library name, type “lpm”

22

2.4. Setting file properties- Choose all files

- Right click and choose Properties

- Click tab VHDL, choose “Use 1993 Language Syntax”

23

2.4. Setting file properties (cont.)- Choose 2 files “220models” and “220pack”

- Right click and choose Properties

- At tab VHDL, choose “lpm” in ‘Compile to library’ index

24

2.5. Compile program- Choose all files

- Right click and choose Compile => Compile All

25

# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl

# do {D:/Softwares/MATLAB/R2008a/bin/tp2eb1637e_fa87_4651_9eb1_209b9189e1d8}

# Loading project counter

# Compile of 220model.vhd was successful.

# Compile of 220pack.vhd was successful.

# Compile of counter.vhd was successful.

# 3 compiles, 0 failed with no errors.

ModelSim> vsimu work.counter# vsim -foreign {simlinkserver

{D:/Softwares/MATLAB/R2008a/toolbox/modelsim/windows32/liblfmhdls_vs05.dll} ; -socket

4449 } work.counter

# Loading C:/Modeltech_5.7d/win32/../std.standard

# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_1164(body)

# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_arith(body)

# Loading C:/Modeltech_5.7d/win32/../ieee.std_logic_unsigned(body)

# Loading work.counter(a)

# Loading D:/Softwares/MATLAB/R2008a/toolbox/modelsim/windows32/liblfmhdls_vs05.dll

2.6. Simulation- At main window, type “vsimu work.counter”

(Command’s structure: vsimu work.name_of_entity1 work. name_of_entity2)

26

3. Matlab3.1. Create new model

- At main window, type “Simulink”

- At Simulink Library Browser, choose EDA Simulator Link MQ

27

3.2. Setting HDL block parameters

- At tab Ports, add inputs, outputs and their parameters

28

3.2. Setting HDL block parameters (cont.)

- At tab ‘Clock’, add clock and timing period

29


30


31

HDL Cosimulation

clear

load

direction

count _ena

P

qd

max_min

Display 6

bin 0

Display 3

(SI) bin 0001 0100

Display 2

bin 0001 0100

Display 1

bin 1

int 8

Convert

Convert

Convert

Convert

Constant 5

1

Constant 4

20

Constant 3

1

Constant 2

1

Constant 1

0

HDL Cosimulation

clear

load

direction

count _ena

P

qd

max_min

3.3. Create Model and start Co-simulation

32

3.3. Create Model and start Co-simulation (cont.)

33


34


35


36


37

ModelSim/Simulink Co-simulationCase study

- Sum of Product (SoP)

- Filter Design

40

Example-1 Sum of Product

41


42


error

5.9814453125015 e-005

Sum of Product

x1

x2

x3

a1

a2

a3

y

Subtract

OutputGain 1

-K-

Embedded

MATLAB Function

x1

x2

x3

a1

a2

a3

yfcn

bin 0000 1100 0010 0111

Display 1

0.095

0.094940185546875

Convert

Convert

Convert

Convert

Convert

Convert

0.5

0.15

0.5

-0.1

0.3

0.2

fixdt(1,16,0)

0: unsigned

1: signed

data length (16bits)

Q format (Q0)

function y = fcn(x1,x2,x3,a1,a2,a3)

y=a1*x1+a2*x2+a3*x3

43


error

5.9814453125015 e-005

Sum of Product

x1

x2

x3

a1

a2

a3

y

Subtract

OutputGain 1

-K-

Embedded

MATLAB Function

x1

x2

x3

a1

a2

a3

yfcn

bin 0000 1100 0010 0111

Display 1

0.095

0.094940185546875

Convert

Convert

Convert

Convert

Convert

Convert

0.5

0.15

0.5

-0.1

0.3

0.2

44

Example-2 Filter Design

• Its fourth order low pass filter:

A second-order low-pass filter is designed with

bandwidth 5Hz and damping ratio 1.0

• The continuous transfer function of the second order low

pass filter is:

45


After the bilinear transform with sampling time 0.01,

its discrete transfer function is

Difference equation after Q15 format: (y(n)*32768, or x(n)*32768)

Y(n)= 95486*Y(n-1) – 104366*Y(n-2) + 50692*Y(n-3) - 9234*Y(n-4) +

11*X(n) + 44*X(n-1) + 67*X(n-2) + 44*X(n-3) + 11*X(n-4)

Where x(n) are inputs and y(n) are outputs

46


I. Technique description

47

Example-2 Filter DesignII. VHDL Code

48


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50


51


III. Simulation Result (ModelSim/Simulink Co-simulation)

52


53


54


55

Thank you for your attention

digital system design (2015)

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