digital system design lab manual

Sri Venkateswara College of Engineering & Technology

R.V.S Nagar, Chittoor

M.Tech. I SEMESTER (DECS)

DIGITAL SYSTEM DESIGN LAB

List of Experiments

1. Simulation and Verification of Logic Gates.

2. Design and Simulation of

(a) Half adder (b) Full adder (c) Serial Binary adder

(d) Carry Look Ahead adder (e) Ripple Carry adder

3. Simulation and Verification of

(a) Decoder (b) Mux (c) Encoder

4 Modeling of Flip-Flops

(a) SR Flip-Flops (b) D Flip-Flops

(c) JK Flip-Flops (d) T Flip-Flops

5. Design and Simulation of Counters

(a) Ring Counters (b) Johnson Counters

(c) Up-Down Counters (d) Ripple Counters (Asynchronous)

6. Design of a N- bit Register

(a) Serial-in Serial-out (b) Serial in Parallel out

(c) Parallel in Serial out (d) Parallel in Parallel out

7. Design of Sequence detector.

8. 4-Bit Multiplier (Array)

9. Design of ALU.

10. RAM (Read and Write Operations)

11. Stack and Queue Implementation.

Lab-In-charge HOD, ECE

LOGIC GATES

Ex. No : 01

AIM :- To write a VHDL Code for realizing Gates

• AND, OR, NOT, NAND, NOR, XOR, XNOR

And verify the results.

AND GATE

PROGRAM:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and2 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);

end and2;

architecture data_flow of and2 is

begin

c<=a and b;

end data_flow;

architecture behavioral of and2 is

begin

process(a,b)

begin

if a='1' and b='1'

then c<='1';

else c<='0';

end if;

end process;

end behavioral;

architecture structural of and2 is

component andx is

Port ( x : in STD_LOGIC;

y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

A1:andx port map(a,b,c);

end structural;

library IEEE;




entity andx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end andx;

architecture andx of andx is

begin

z<=x and y;

end andx;

OR GATE

PROGRAM:-

library IEEE;




entity or2 is


b : in STD_LOGIC;

c : out STD_LOGIC);

end or2;

architecture data_flow of or2 is

begin

c<=a or b;

end data_flow;

architecture behavioral of or2 is

begin

process(a,b)

begin

if a='0' and b='0'

then c<='0';

else c<='1';

end if;

end process;

end behavioral;

architecture structural of or2 is

component orx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

A1:orx port map(a,b,c);

end structural;

library IEEE;




entity orx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end orx;

architecture orx of orx is

begin

z<=x or y;

end orx;

NOT GATE

PROGRAM:-

library IEEE;




entity not1 is Port ( a : in STD_LOGIC;

b : out STD_LOGIC);

end not1;

architecture data_flow of not1 is

begin

b<=not a;

end data_flow;

architecture behavioral of not1 is

begin

process(a)

begin

if a='0'

then b<='1';

else b<='0';

end if;

end process;

end behavioral;

architecture structural of not1 is

component notx is


y : out STD_LOGIC);

end component;

begin

A1:notx port map(a,b);

end structural;

library IEEE;




entity notx is


y : out STD_LOGIC);

end notx;

architecture notx of notx is

begin y<=not x;

end notx;

NAND GATE

PROGRAM:-

library IEEE;




entity nand2 is


b : in STD_LOGIC;

c : out STD_LOGIC);

end nand2;

architecture data_flow of nand2 is

begin

c<=a nand b;

end data_flow;

architecture behavioral of nand2 is

begin

process(a,b)

begin

if a='1' and b='1'

then c<='0';

else c<='1';

end if;

end process;

end behavioral;

architecture structural of nand2 is

component nandx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

A1:nandx port map(a,b,c);

end structural;

library IEEE;




entity nandx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end nandx;

architecture nandx of nandx is

begin

z<=x nand y;

end nandx;

NOR GATE

PROGRAM:-

library IEEE;




entity nor2 is


b : in STD_LOGIC;

c : out STD_LOGIC);

end nor2;

architecture data_flow of nor2 is

begin

c<=a nor b;

end data_flow;

architecture behavioral of nor2 is

begin

process(a,b)

begin

if a='0' and b='0'

then c<='1';

else c<='0';

end if;

end process;

end behavioral;

architecture structural of nor2 is

component norx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

A1:norx port map(a,b,c);

end structural;

library IEEE;




entity norx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end norx;

architecture norx of norx is

begin

z<=x nor y;

end norx;

XOR GATE

PROGRAM:-

library IEEE;




entity xor2 is


b : in STD_LOGIC;

c : out STD_LOGIC);

end xor2;

architecture data_flow of xor2 is

begin

c<=a xor b;

end data_flow;

architecture behavioral of xor2 is

begin

process(a,b)

begin

if a=b

then c<='0';

else c<='1';

end if;

end process;

end behavioral;

architecture structural of xor2 is

component xorx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

A1:xorx port map(a,b,c);

end structural;

library IEEE;




entity xorx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end xorx;

architecture xorx of xorx is

begin

z<=x xor y;

end xorx;

XNOR GATE

PROGRAM:-

library IEEE;




entity xnor2 is


b : in STD_LOGIC;

c : out STD_LOGIC);

end xnor2;

architecture data_flow of xnor2 is

begin

c<=a xnor b;

end data_flow;

architecture behavioral of xnor2 is

begin

process(a,b)

begin

if a=b

then c<='1';

else c<='0';

end if;

end process;

end behavioral;

architecture structural of xnor2 is

component xnorx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

A1:xnorx port map(a,b,c);

end structural;

library IEEE;




entity xnorx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end xnorx;

architecture xnorx of xnorx is

begin

z<=x xnor y;

end xnorx;

MODELING OF ADDERS

Ex. No : 02

AIM :- To write a VHDL Code for

• Half adder

• Full adder

• ripple carry adder

• carry look ahead adder

• serial adder


HALF ADDER

PROGRAM:-

library IEEE;




entity ha is


b : in STD_LOGIC;

sum: out STD_LOGIC;

carry: out STD_LOGIC);

end ha;

architecture data_flow of ha is

begin

sum<=a xor b;

carry<= a and b;

end data_flow;

architecture behavioral of ha is

begin

process(a,b)

begin

if a=b

then sum<='0';

else sum<='1';

end if;

if a='1' and b='1'

then carry<='1';

else carry<='0';

end if;

end process;

end behavioral;

architecture structural of ha is

component xorx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

component andx is


y : in STD_LOGIC;

z : out STD_LOGIC);

end component;

begin

x1:xorx port map(a,b,sum);

A1:andx port map(a,b,carry);

end structural;

FULL ADDER

PROGRAM:-

library IEEE;

use IEEE.std_logic_1164.all;

entity adder is

port (a : in std_logic;

b : in std_logic;

cin : in std_logic;

sum : out std_logic;

cout : out std_logic);

end adder;

-- description of adder using concurrent signal assignments

architecture rtl of adder is

begin

sum <= (a xor b) xor cin;

cout <= (a and b) or (cin and a) or (cin and b);

end rtl;

-- description of adder using component instantiation statements

use work.gates.all;

architecture structural of adder is

signal xor1_out,

and1_out,

and2_out,

or1_out : std_logic;

begin

xor1: xorg port map(

in1 => a,

in2 => b,

out1 => xor1_out);

xor2: xorg port map(

in1 => xor1_out,

in2 => cin,

out1 => sum);

and1: andg port map(

in1 => a,

in2 => b,

out1 => and1_out);

or1: org port map(

in1 => a,

in2 => b,

out1 => or1_out);

and2: andg port map(

in1 => cin,

in2 => or1_out,

out1 => and2_out);

or2: org port map(

in1 => and1_out,

in2 => and2_out,

out1 => cout);

end structural;

------------------------------------------------------------------------

-- N-bit adder

-- The width of the adder is determined by generic N

------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

entity adderN is

generic(N : integer := 16);

port (a : in std_logic_vector(N downto 1);

b : in std_logic_vector(N downto 1);

cin : in std_logic;

sum : out std_logic_vector(N downto 1);


end adderN;

-- structural implementation of the N-bit adder

architecture structural of adderN is

component adder

port (a : in std_logic;

b : in std_logic;

cin : in std_logic;

sum : out std_logic;


end component;

signal carry : std_logic_vector(0 to N);

begin

carry(0) <= cin;

cout <= carry(N);

-- instantiate a single-bit adder N times

gen: for I in 1 to N generate

add: adder port map(

a => a(I),

b => b(I),

cin => carry(I - 1),

sum => sum(I),

cout => carry(I));

end generate;

end structural;

-- behavioral implementation of the N-bit adder

architecture behavioral of adderN is

begin

p1: process(a, b, cin)

variable vsum : std_logic_vector(N downto 1);

variable carry : std_logic;

begin

carry := cin;

for i in 1 to N loop

vsum(i) := (a(i) xor b(i)) xor carry;

carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));

end loop;

sum <= vsum;

cout <= carry;

end process p1;

end behavioral;

RIPPLE CARRY ADDER

PROGRAM:-

library IEEE;

Use IEEE.STD_LOGIC_1164.All;

Use IEEE.STD_LOGIC_ARITH.All;

Use IEEE.STD_LOGIC_UNSIGNED.All;

entity rea is

Port (a: in std_logic _vector (3 downto 0);

b: in std_logic _vector (3 downto 0);

ci:in std_logic;

s: out std_logic _vector (3 downto 0);

co:in out std_logic);

end rea;

architecture structural of rea is

signal c:std_ logic vector(3 downto 1);

component fa is

port (a,b,cin: in std_logic;

s : out std_logic;

cout: in out std_logic);

end component;

begin

f1: fa port map( a(0), b(0), ci, s(0),c(1));

f2: fa port map(a(1), b(1), c(1), s(1),c(2));

f3: fa port map(a(2), b(2), c(2), s(2),c(3));

f4: fa port map(1)p(a(3), b(3), c(3), s(3),c(0));

end structural;

CARRY LOOK AHEAD ADDER

PROGRAM:-

library IEEE;




entity carry_look_ahead is

Port (a: in std_logic _vector(3 downto 0);

b : in std_logic _vector(3 downto 0);

co : out std_logic;

c : inout std_logic _vector(4 downto 0);

s : out std_logic _vector(3 downto 0);

end carry_look_ahead;

architecture structural of carry_look_ahead is

signal p,g:std_ logic _vector(3 downto 0);

signal r : std_ logic_ vector(6 downto 0);

signal i : integer;

begin

processor(a,b,c,p,g,r)

begin

l1 : for i in 0 to 3 loop

p(i)<=a(i) xor b(i);

g(i)<=a(i) and b(i);

c(0)<=’0’;

end loop l1;

r(0)<=p(2)and g(1);

r(1)<=p(2)and p(1)and g(0);

r(2)<=p(2)and p(1)and p(0)and c(0);

r(3)<=p(3)and g(2);

r(4)<=p(3)and p(2)and g(1);

r(5)<=p(3)and p(2)and p(1)and g(0);

r(6)<=p(3)and p(2)and p(1)and p(0) and c(0);

c(1)<=g(0)or ( p(0) and c(0));

c(2)<=g(1)or ( p(1) and g(0)) or( p(1)and ( p(0) and c(0));

c(3)<=g(2)or r(0) or r(1) or r(2);

c(4)<=g(3)or r(3) or r(4) or r(5) or r(6);

l2: for i in 0 to 3 loop

s(i)<=p(i) xor c(i);

end loop l2;

c(0)<=c(4);

end process;

end Behavioral;

SERIAL ADDER

PROGRAM:-

library IEEE;




entity serial_adder is

Port (x: in std_logic _vector(3 downto 0);

y : in std_logic _vector(3 downto 0);

clk : in std_logic;

ce:in std_logic;

cout : inout std_logic

s : out std_logic

end serial_adder;

architecture structural of serial_adder is

signal c:std_ logic_ vector(4 downto 0);

signal i : integer;

begin

processor(clk,x,y)

begin

if (ce’event and ce =’1’)then

c(0)<=’0’;

s<=’0’;

i<=’0’;

end if;

if (ce’event and clk =’1’)then

s<=(x(i)xor y(i) xor c(i);

c(i+1)<=(x(i)and y(i))or (y(i)and c(i))or (c(i)and x(i));

i<=i+1;

end if;

else

i<=0;

end if;

cout<=c(4);

end process;

end Behavioral;

EX.No:- 03

3:8 DECODER

AIM: To write and simulate a vhdl program for a 3 to 8 decoder and verify the

results

PROGRAM:-

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity dc_counter is

port(clk:in std_logic;

q:inout std_logic_vector(3 downto 0):="0000");

end dc_counter;

architecture behave of dc_counter is

begin

process(clk)

begin

if(clk'event and clk='1')then

if(q="1001")then

q<="0000";

else

q<=q+1;

end if;

end if;

end process;

end behave;

8x1 MULTIPLEXER

AIM:- To write and simulate aModelsim( VHDL) program for 8x1 Multiplexer.

PROGRAM:-

library ieee;


entity mx is

port(i:in std_logic_vector(7 downto 0);

s:in std_logic_vector(2 downto 0);

y:out std_logic);

end mx;

architecture archi of mx is

begin

process(i,s)

begin

if(s="000") then y<=i(0);

elsif(s="001") then y<=i(1);







end if;

end process;

end archi;

MODELING OF FLIP - FLOPS

Ex. No : 04

AIM : - To write a VHDL Code for

• SR Flip-Flop

• D Flip-Flop

• JK Flip-Flop

• T Flip-Flop And verify the results.

SR - FLIP - FLOP

PROGRAM:-

library IEEE;




entity srff is

Port (s : in std_logic;

r : in std_logic;

clk : in std_logic;

q : in out std_logic;

qbar : in out std_logic);

end srff;

architecture Behavioral of srff is

begin

Process (s,clk,r)

begin

if (clk’event and clk =’1’)then

if(s=’0’and r=’0’)then

q<=q;

qbar<=qbar;

elsif(s=’1’and r=’0’)then

q<=’1’;

qbar<=’0’;

elsif(s=’0’and r=’1’)then

q<=’0’;

qbar<=’1’;

else

q<=not q ;

qbar<=not qbar;

end if:

else

q<=q;

qbar<=qbar;

end if:

end process;

end Behavioral;

architecture data_flow of sr_ff is

signal s1,s2:std_ logic; begin

s1<=s nand clk;

s2<=r nand clk;

q<=s1 nand qbar;

qbar<=s2 nand q;

end data_flow;

architecture structural of srff is

signal s1,s2:std_ logic;

component nand2 is

port (a,b: in std_logic;

c : out std_logic);

end component;

begin

n1: nand2 port map(s,clk,s1);

n2: nand2 port map(r,clk,s2);

n3: nand2 port map(s1,qbar,q);

n4: nand2 port map(s2,q,qbar);

end structural;

D - FLIP - FLOP

PROGRAM:-

library IEEE;




entity dff is

Port (d : in std_logic;

clk : in std_logic;



end dff;

architecture Behavioral of dff is

begin

Process (d,clk)

Begin


if(d=’0’)then

q<=’0’;

qbar<=’1’;

else

q<=’1’;

qbar<=’0’;

end if:

else

q<=q;

qbar<= qbar;

end if:

end process;

end Behavioral;

architecture data_flow of d_ff is


s1<=d nand clk;

s2<=not d nand clk;

q<=s1 nand qbar;

qbar<=s2 nand q;

end data_flow;

architecture structural of d_ff is

signal s1,s2,s3:std_ logic;

component nand2 is


c : out std_logic);

end component;

component not1 is

port (a: in std_logic;

c : out std_logic);

end component;

begin

x1: not1 port map(d,s3);

n1: nand2 port map(d,clk,s1);

n2: nand2 port map(s3,clk,s2);

n3: nand2 port map(s1,qbar,q);

n4: nand2 port map(s2,q,qbar);

end structural;

JK - FLIP - FLOP

PROGRAM:-

library IEEE;




entity jkff is

Port (j : in std_logic;

k : in std_logic;

clk : in std_logic;



end jkff;

architecture Behavioral of jkff is

begin

Process (j,clk,k)

begin


if(j=’0’and k=’0’)then

q<=q;

qbar<=qbar;

elsif(j=’0’and k=’1’)then

q<=’0’;

qbar<=’1’;

elsif(j=’1’and k=’0’)then

q<=’1’;

qbar<=’0’;

else

q<=not q ;

qbar<=not qbar;

end if:

else

q<=q;

qbar<=qbar;

end if:

end process;

end Behavioral;

architecture data_flow of jk_ff is


s1<=k and clk and q;

s2<=j and clk and qbar;

q<=s1 nor qbar;

qbar<=s2 nor q;

end data_flow;

architecture structural of jk_ff is

signal s1,s2:std_ logic;

component nor2 is


c : out std_logic);

end component;

begin

component and3 is

port (a,b,c: in std_logic;

d : out std_logic);

end component;

begin

x1: and3 port map(k,clk,q,s1);

x2: and3 port map(j,clk,qbar,s2);

x3: nor2 port map(s1,qbar,q);

x4: and2 port map(s2,q,qbar);

end structural;

T - FLIP - FLOP

PROGRAM:-

library IEEE;




entity tff is

Port (t : in std_logic;

clk : in std_logic;



end tff;

architecture Behavioral of tff is

begin

Process (t,clk,)

begin


if(t=’0’)then

q<=q;

qbar<=qbar;

else

q<=not q ;

qbar<=not qbar;

end if:

else

q<=q;

qbar<=qbar;

end if:

end process;

end Behavioral;

architecture data_flow of t_ff is


s1<=t and clk and q;

s2<=t and clk and qbar;

q<=s1 nor qbar;

qbar<=s2 nor q;

end data_flow;

architecture structural of t_ff is

signal s1,s2 : std_ logic;

component nor2 is


c : out std_logic);

end component;

begin

component and3 is

port (a,b,c: in std_logic;

d : out std_logic);

end component;

begin

x1: and3 port map(t,clk,q,s1);

x2: and3 port map(t,clk,qbar,s2);

x3: nor2 port map(s1,qbar,q);

x4: and2 port map(s2,q,qbar);

end structural;

DESIGN AND SIMULATION OF COUNTERS

Ex. No : 05

AIM :-

To write a VHDL Code for

• Ring Counters

• Johnson Counters

• Up-Down Counters

• Ripple Counters (Asynchronous)


BCD COUNTER

PROGRAM:

library IEEE;




entity mod_n_coun is

Port (ce: in std_logic ;

clk: in std_logic;

q:in out std_logic _vector (3 downto 0));

end mod_n_coun ;

architecture Behavioral of mod_n_coun is

begin

Process (ce,clk);

begin


q<=”0000”;

end if:


if (ce=’1’)then

q<=q+1;

end if;

if (q>=”1001”)then

q<=”0000”;

end if;

end if;

end process;

end Behavioral;

BINARY UP DOWN COUNTER

PROGRAM:-

library IEEE;




entity bin_up_down is

Port (up: in std_logic ;

down: in std_logic;

ce: in std_logic ;

clk: in std_logic;


end bin_up_down;

architecture Behavioral of bin_up_down is

begin

Process (up, down, ce, clk);

begin


q<=”0000”;

end if:


if (up=’1’)then

q<=q+1;

else if(down=’1’)then

q<=q-1;

end if;

end if;

end process;

end Behavioral;

ASYNCHRONOUS COUNTER

PROGRAM:-

library IEEE;




entity asy_count is

Port (ce: in std_logic;

clk: in std_logic;

n:in std_logic _vector (3 downto 0);


end asy_count;

architecture Behavioral of asy_count is

begin

Process (ce, clk,q);

begin


q<=”0000”;

end if:

if(q<n)then


q(0)<=not q(0);

if (q(0) =’1’)then

q(1)<=not q(1);

if (q(1) =’1’)then

q(2)<=not q(2);

if (q(2) =’1’)then

q(3)<=not q(3);

end if;

end if;

end if;

end if;

else

q<=”0000”;

end if;

end process;

end Behavioral;

MODELING OF SHIFT REGISTERS COUNTERS

Ex. No : 06

AIM :-

To write VHDL Program for realizing Shift Registers

• Serial-in Serial-out

• Serial in Parallel out

• Parallel in Serial out

• Parallel in Parallel out


SHIFT REGISTERS

Serial in serial out (SISO)

PROGRAM:

library IEEE;




Entity siso is

Port (si: in std_logic;

clk: in std_logic;

so:in out std_logic);

end siso;

architecture structural of siso is

component d_ff is

Port( d,clk: in std_logic;

q,qbar :in out std_logic);

end component;

Signal a1, a2, a3, d1, d2, d3, d4:std_logic;

begin

11:d_ff port map (si, clk, a1, d1);

12:d_ff port map (a1, clk, a2, d2);

13:d_ff port map (a2, clk, a3, d3);

14:d_ff port map (a3, clk, so, d4);

end structural;

SIPO

PROGRAM:-

library IEEE;




Entity sipo is

Port (si: in std_logic;

clk: in std_logic;

po:in out std_logic_vector(3 downto 0));

end sipo;

architecture structural of sipo is

signal d:std _logic_ vector(4 downto 0);

component d_ff

Port (d,clk: in std_logic;


end component;

begin

a1:d_ff port map (si, clk, po(3),d(3));

a2:d_ff port map( po(3), clk, po(2),d(2));

a3:d_ff port map (po(2), clk, po(1),d(1));

a4:d_ff port map (po(1), clk, po(0),d(0));

end structural;

PISO

PROGRAM:-

library IEEE;




entity piso is

Port (pi: in std_logic _vector (3 downto 0);

c: in std_logic;

clk: in std_logic;

so:in out std_logic);

end piso;

architecture structural of piso is

signal d:std_ logic vector(3 downto 0);

signal q:std _logic vector(3 downto 1);

signal a:std_ logic vector(3 downto 1);

signal r:std _logic;

component d_ff is



end component;

component aoi is

Port (a,b,c,d: in std_logic;

c: out std_logic);

end component;

begin

a1:aio port map (q (3),r,c,pi(2)a(3));

a2:aio port map( q (2),r,c,pi(1)a(2));

a3:aio port map (q (1),r,c,pi(0)a(1));

11:d_ff port map( pi(3), clk, q(3),d(3));

12:d_ff port map(a(3), clk, q(2),d(2));

13:d_ff port map(a(2), clk, q(1),d(1));

14:d_ff port map(a(1), clk, so,d(0));

end structural;

PIPO

PROGRAM:-

library IEEE;




entity pipo is

Port (pi: in std_logic _vector (3 downto 0);

clk: in std_logic;

po:in out std_logic _vector (3 downto 0));

end pipo;

architecture structural of pipo is

signal d:std_ logic vector(4 downto 0);

component d_ff is



end component;

begin

11:d_ff port map( pi(3), clk, po(3),d(3));




end structural;

Serial in serial out (SISO)

Serial Input

Clk

Serial Out

Serial in Parallel out (SIPO)

Serial Input

Clk

Parallel Out

Q(n-2)

Q(n-3)

Q(0)

Q(n-1)

Q(n-2)

Q(n-3)

Q(0)

Q(n-1)

Parallel in out Serial (PISO)

Parallel In

Clk

Serial Out

Parallel in Parallel out(PIPO)

Parallel In

Clk

Load

Parallel Out

SISO PIPO

SIN CLK SOUT

1 U

0 1

0 0

1 0

1 1

1 1

0 1

INPUT OUTPUT

SIN CLK Q0 Q1 Q2 Q3

1 U U U U

0 1 U U U

0 0 1 U U

1 0 0 1 U

1 1 0 0 1

1 1 1 0 0

Q(n-2)

Q(n-3)

Q(0)

Q(n-1)

Q(n-2)

Q(n-3)

Q(0)

Q(n-1)

PISO

PIPO

MOD-N BCD Counter

Q0

Q1

Clk

Q2

Q3

INPUT

OUTPUT

LOAD CLK IN0 IN1 IN1 IN1 SOUT

1 0 0 1 U

X 1 1 0 0 1

X 1 1 1 0 0

X 1 1 1 1 0

X 1 1 1 1 1

INPUT OUTPUT

LOAD CLK 10 11 I2 I3 Q0 Q1 Q2 Q3

X 1 0 0 1 U U U U

X 1 0 0 1 1 0 0 1

X 1 1 0 1 1 0 0 1

0 1 0 0 1 1 0 1

X 0 1 0 0 0 1 0 0

INPUT OUTPUT

SIN CLK Q0 Q1 Q2 Q3

1 U U U U

0 1 U U U

0 0 1 U U

1 0 0 1 U

1 1 0 0 1

1 1 1 0 0

MOD-N

BCD

Counter

BINARY UP DOWN COUNTER

Q0

UP

DN Q1

Clk Q2

Q3

ASYNCHRONOUS COUNTER

Q0

Clk

Q1

Q0

Q2

Q1

Q3

Q2

CLR

BINARY

UP

DOWN

COUNTER

Asynchronous

Counter

MODELLING OF MULTIPLIERS

Ex. No : 08

AIM :- To write VHDL Program for realizing multipliers like Array

Multiplier and verify the results.

PROGRAM:-

library IEEE;




entity unsign_mul is

Port (x: in std_logic _vector(3 downto 0);

y : in std_logic _vector(3 downto 0);

l : in std_logic;

p : inout std_logic _vector(7 downto 0);

end unsign_mul;

architecture Behavioral of unsign_mul is

signal m : std_ logic_ vector(7 downto 0);

signal i : integer;

begin

processor(x,y,i)

begin

if (l’event and l =’1’)then

q<=”00000000”;

m<=”0000”&x;

i<=0;

else

qbar<=qbar;

if(i<4)then

if(y(i)=’1’)then

q<=p+m;

else

p<=p;

i<=i+1 after 50 ps;

m<=m(6 downto 0)&’0’;

end if;

end if;

end process;

end Behavioral;

RAM

Ex. No : 09

AIM :- To write VHDL Program for RAM and verify the results.

PROGRAM:-

library ieee;


entity ram is

port(din:in std_logic_vector(7 downto 0);

rd,wr,clk:in std_logic;

locn:in integer range 0 to 7;

dout:out std_logic_vector(7 downto 0));

end ram;

architecture behav of ram is

type mem is array(integer range 0 to 7) of std_logic_vector(7 downto 0);

signal sram:mem;

begin

process(clk,rd,wr)

begin

if((rd and wr)/='1')then

if(clk'event and clk='1')then

if(rd='1')then

dout<=sram(locn);

else if(wr='1')then

sram(locn)<=din;

end if;

end if;

end if;

end if;

end process;

end behav;

STACK AND QUEUE IMPLEMENTATIONS

Ex. No : 10

AIM :- To write VHDL Program for Stack and Queue Implementations

and verify the results.

PROGRAM:- library ieee;


entity stack is

port ( rd,wr,clk,clr:in std_logic;

data: inout std_logic_vector(7 downto 0);

ful:out std_logic);

end stack;

architecture que of stack is

type store is array(natural range <>)of std_logic_vector(7 downto 0);

signal address: integer range 0 to 15;

signal memory:store(0 to 15);

begin

process (data ,rd ,wr,clr,clk)

begin

if clr='1' then

memory<=(others=>(others=>'0'));

ful<='0';

address<=0;

elsif(clk='1'and clk'event)then

if address=15 then

ful<='1';

else

memory(address)<=data;

address<=address+1;

end if;

elsif (rd='1')then

if (address=0)then

ful<='0';

else

data<=memory(address);

address<=address-1;

end if;

end if;

end process;

end que;