DRC 20091

0.37 mS/m In0.53Ga0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain

Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Ashish K. Baraskar, Joel Cagnon, B. J. Thibeault, S. Stemmer, A.C. Gossard, and M.J.W. Rodwell

ECE and Materials DepartmentsUniversity of California, Santa Barbara, CA

Eun Ji Kim, Byungha Shin, and Paul C McIntyreMaterials Science and Engineering, Stanford University, Stanford, CA

Yong-ju LeeIntel Corporation, Santa Clara, CA

2009 Device Research ConferencePennsylvania State University, State College, PA

*uttam@ece.ucsb.edu

DRC 20092

Outline

• Motivation: III-V MOSFETs

• Approach: Self-aligned source/drain by MBE regrowth

• FET and contacts Results

• Conclusion and future work

DRC 20093

Why III-V MOSFETs

Silicon MOSFETs:

Gate oxide may limit <16 nm scaling

IBM 45nm NMOS Narayan et al, VLSI 2006

* Enoki et al , EDL 1990

Alternative: In0.53Ga0.47As channel MOSFETs

low m* (0.041 mo) → high injection velocity (~ 2×107 cm/s)*

→ increase drive current, decreased CV/I

Id / Wg ~ cox(Vg-Vth)vinj

Id / Qtransit ~ vinj / Lg

DRC 20094

Target device structure

Target 22 nm gate length

Control of short-channel effects vertical scaling1 nm EOT: thin gate dielectric, surface-channel device5 nm quantum well thickness<5 nm deep source / drain regions

~3 mA/m target drive current low access resistanceself-aligned, low resisitivity source / drain contactsself-aligned N+ source / drain regions with high doping

-4

-3

-2

-1

0

1

2

3

0 50 100 150 200 250

En

erg

y (

eV

)

Y (Ang.)

Al2O

3

InGaAs InAlAs

DRC 20095

22 nm InGaAs MOSFET: source resistance

IBM High-k Metal gate transistorImage Source:EE Times

smi

did Rg

II

1 g

DSsheet

DSg

cs W

L

LWR

2/

/

LgLS/D

• Source access resistance degrades Id and gm

• IC Package density : LS/D ~ Lg =22 nm c must be low

• Need low sheet resistance in thin ~5 nm N+ layer

• Design targets: c ~1 m2, sheet ~ 400

DRC 20096

22nm ion implanted InGaAs MOSFET

• Shallow junctions ( ~ 5 nm), high (~5×1019 cm-3) doping

• Doping abruptness ( ~ 1 nm/decade)

• Lateral Straggle ( ~ 5 nm)

• Deep junctions would lead to degraded short channel effects

Key Technological Challenges

DRC 20097

InGaAs MOSFET with raised source/drain by regrowth

1Wistey, EMC 20082Baraskar, EMC 2009

Interface

HAADF-STEM1*

2 nm

InGaAs

InGaAsregrowth

Self-aligned source/drain defined by MBE regrowth1

Self-aligned in-situ Mo contacts2

Process flow & dimensions selected for 22 nm Lg design; present devices @ 200 nm gate length

* TEM by J. Cagnon, Susanne Stemmer Group, UCSB

DRC 20098

Regrown S/D process: key features

Vertical S/D doping profile set by MBEabrupt on ~ 1 nm scale

Self-aligned & low resistivity...source / drain N+ regions...source / drain metal contacts

Gate-firstgate dielectric formed after MBE growth

uncontaminated / undamaged surface

DRC 20099

Process flow*

* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009

DRC 200910

SiO2

W

Cr

FIB Cross-section

Damage free channel

Process scalable to sub-100 nm gate lengths

Key challenge in S/D process: gate stack etch

Requirement: avoid damaging semiconductor surface:Approach: Gate stack with multiple selective etches*

* Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009

DRC 200911

Key challenge in S/D process: dielectric sidewall

Sidewall must be kept thin: avoid carrier depletion, source starvation.

• Target < 15 nm sidewall in 22 nm Lg device

• 20-25 nm SiNx thick sidewalls in present devices

• Pulse doping in the barrier: compensate for carrier depletion from Dit

DRC 200912

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

W/Cr gate Pad

Ti/Au Pad

Mo+InGaAs

W/Cr gate Pad

Ti/Au Pad

Mo+InGaAs

MOSFET SEMs

Cross-section after regrowth, but before Mo deposition

Top view of completed device

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

W/Cr gate Pad

Ti/Au Pad

Mo+InGaAs

W/Cr gate Pad

Ti/Au Pad

Mo+InGaAs

Cross-section after regrowth, but before Mo deposition

Top view of completed device

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

W/Cr gate Pad

Ti/Au Pad

Mo+InGaAs

W/Cr gate Pad

Ti/Au Pad

Mo+InGaAs

Cross-section after regrowth, but before Mo deposition

DRC 200913

MOSFET characteristics

0

0.2

0.4

0.6

0.8

1

0 0.5 1 1.5 2

Lg=0.8m, W

g,eff=9m

Vgs

= -1 V to 3.5, Vgs_step

=0.5 V

I ds(m

A/

m)

Vds

(V)

• Maximum Drive current (Id): 0.95 mA/m

• Peak transconductance (gm): 0.37 mSm

4.7 nm Al203 , 1×1013 cm-2 pulse doping

Id and gm below expected values

0

0.2

0.4

0.6

0.8

1

0 0.5 1 1.5 2

I ds(m

A/

m)

Lg=1.0m, W

g,eff=12m

Vgs

= -1 V to 3.5, Vgs_step

=0.5 V

Vds

(V)

DRC 200914

SEM

FET source resistance

InGaAs regrowth on unprocessed thin InP*

• Series resistance estimated by extrapolating Ron to zero gate length

• Source access resistance ~ 500 m

0

1000

2000

3000

4000

5000

6000

7000

0 2 4 6 8 10Gate Length (m)

Vgs

=3.0 V

RS+R

D

= 1.0 k m

Ro

n (

m

)

DRC 200915

Source resistance : regrowth TLMs

W / Cr / SiO2

gate

SEM

No regrowth

SEMInGaAs regrowth

• TLMs fabricated on the regrowth far away from the gate

• Regrowth sheet resistance ~ 29

• Mo/InGaAs contact resistance ~ 5.5 m2 (12.6 m)

TLM data does not explain 500 m observed FET source resistance

FETRegrowth TLMs

0

5

10

15

20

25

30

35

40

0 5 10 15 20 25 30

Res

ista

nc

e (

)

Contact Separation ( m)

Rsh

~ 29

Rc ~ 5.5 m2 (12.6 m)

W~ 20 m

DRC 200916

Source resistance: electron depletion near gate

• Electron depletion in regrowth shadow region (R1 )

• Electron depletion in the channel under SiNx sidewalls (R2 )

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

SiO2

WCr

Originalinterface

InGaAsregrowth

SiNx

R1

R2

DRC 200917

InAs source/drain regrowth

1 Wistey et al, EMC 2009 Wistey et al NAMBE 2009. 2Bhargava et al , APL 1997

InAsregrowth

Gate

side of gate

top of gate

Mo S/D metal with N+ InAs underneath

Improved InAs regrowth with low As flux for uniform filling1

InAs less susceptible to electron depletion: Fermi pinning above Ec2

DRC 200918

InAs S/D E-FET DC characteristics

4.7 nm Al203, InAs S/D E-FET

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 0.2 0.4 0.6 0.8 1

dra

in c

urre

nt,

I D (m

A/

m)

VDS

(V)

Lg = 200 nm W

g = 8 m

Vgs

: 0 to 4 V in 0.5 V steps

DRC 200919

Subthreshold characteristics

• Ion/Ioff~ 104:1

-1 0 1 2 3 4 5

Vds

=0.1V

Vds

=1.0 V

325 mV/decade

Vgs

(V)

Lg=0.35 m

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

-1 0 1 2 3 4 5

Vds

=0.1V

Vds

=1.0V

290 mV/decadeI d(A)

Vgs

(V)

Lg=1.0 m

DRC 200920

Drive current and transconductance

0.95 mA/m peak Id , ~0.45 mS/m peak gm

0

0.2

0.4

0.6

0.8

1

0

0.1

0.2

0.3

0.4

0.5

0 0.5 1 1.5 2 2.5 3 3.5 4

dra

in c

urre

nt,

I D (

mA

/m

)

transcon

ductran

ce, g

m (mS

/m

)

Vgs

(V)

Vds

=2 V

Lg=200 nm

DRC 200921

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Ro

n (k

m

)

gate length (m)

600 m

Source-drain access resistance*

• Ron = 600 -m for Lg=0.2 m so Rs< 300 m

• Rs is too small to explain observed gm or Id*Wistey et al, NAMBE 2009

DRC 200922

• Self-aligned raised source/drain for scaled channel ( 5nm)

• D-FETs: peak Id = 0.95 mA/m, and peak gm =0.37 mS/m

• InAs Source/Drain E-FETs: peak Id= 0.95 mA/m and peak gm= 0.45 mS/m

• Next: scale to ~50 nm Lg

gate dielectric quality

Conclusion

This work was supported by Semiconductor Research Corporation under theNon-classical CMOS Research Program