dsp56857, 56857 - data sheet - farnell element14 · 2015. 4. 28. · sc02 (gpioc5) miso (gpiof0)...

56800E16-bit Digital Signal Controllers

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56857Data SheetTechnical Data

DSP56857Rev. 601/2007

56857 Technical Data, Rev. 6

Freescale Semiconductor 3

56857 Block Diagram

JTAG/Enhanced

OnCE

Program Controllerand

Hardware Looping Unit

Data ALU16 x 16 + 36 Æ 36-Bit MAC

Three 16-bit Input RegistersFour 36-bit Accumulators

Address Generation Unit

Bit Manipulation

Unit

16-BitDSP56800E Core

XTAL

EXTALInterrupt

Controller Quad Timer

orGPIOG

4

CLKO

4

RESET

IRQAIRQB

VDD VSSIO VDDA VSSA

CS0-CS3[3:0]

MODEA-C or

6

Program Memory40,960 x 16 SRAM

Boot ROM1024 x 16 ROM

Data Memory24,576 x 16 SRAM

PDB

PDB

XAB1

XAB2

XDB2

CDBR

SPI or

GPIOF

2 SCI or

GPIOE

IPBus Bridge (IPBB)

3

(GPIOH0-H2)

8 12

VDDIO12

DecodingPeripherals

4

System Bus

Control

Memory

PAB

PAB

CDBW

CDBR

CDBW

VSS5

6

ESSI0 or

GPIOC

6

ESSI1 or

GPIOD

Host Interface

or GPIOB

16

RSTO

DMA6 channel

POR

Integration Module

System

COP/Watch-

dog

Timeof

Day

ClockGenerator

OSC PLL

2

IPBus CLK

COP/TOD CLK

Core CLK

used as GPIOA0-A3

IPA

B

IPW

DB

IPR

DB D

MA

Req

uest

s

GPIO Contol

56857 General Description

• 120 MIPS at 120MHz• 40K x 16-bit Program SRAM• 24K x 16-bit Data SRAM• 1K x 16-bit Boot ROM• Six (6) independent channels of DMA• Two (2) Enhanced Synchronous Serial Interfaces

(ESSI)• Two (2) Serial Communication Interfaces (SCI)• Serial Port Interface (SPI)

• Four (4) dedicated GPIO• 8-bit Parallel Host Interface• General Purpose 16-bit Quad Timer• JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging• Computer Operating Properly (COP)/Watchdog Timer• Time-of-Day (TOD)• 100 LQFP package• Up to 47 GPIO


4 Freescale Semiconductor

Part 1 Overview

1.1 56857 Features

1.1.1 Digital Signal Processing Core• Efficient 16-bit engine with dual Harvard architecture• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)• Four (4) 36-bit accumulators including extension bits• 16-bit bidirectional shifter• Parallel instruction set with unique DSP addressing modes• Hardware DO and REP loops• Three (3) internal address buses• Four (4) internal data buses• Instruction set supports both DSP and controller functions• Four (4) hardware interrupt levels• Five (5) software interrupt levels• Controller-style addressing modes and instructions for compact code• Efficient C Compiler and local variable support• Software subroutine and interrupt stack with depth limited only by memory• JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory• Harvard architecture permits up to three (3) simultaneous accesses to program and data memory• On-Chip Memory

— 40K × 16-bit Program RAM— 24K × 16-bit Data RAM— 1K × 16-bit Boot ROM— Chip Select Logic used as dedicated GPIO

1.1.3 Peripheral Circuits for 56857• General Purpose 16-bit Quad Timer*• Two Serial Communication Interfaces (SCI)*• Serial Peripheral Interface (SPI) Port*• Two (2) Enhanced Synchronous Serial Interface (ESSI) modules*• Computer Operating Properly (COP)/Watchdog Timer• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging • Six (6) independent channels of DMA

56857 Description



• 8-bit Parallel Host Interface*• Time of Day• Up to 47 GPIO* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4 Energy Information• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs • Wait and Stop modes available

1.2 56857 DescriptionThe 56857 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56857 is well-suited for many applications. The 56857 includes many peripherals that are especially useful for low-end Internet appliance applications and low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote metering; sonic alarms.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating inparallel, allowing as many as six operations per instruction cycle. The microprocessor-style programmingmodel and optimized instruction set allow straightforward generation of efficient, compact DSP andcontrol code. The instruction set is also highly efficient for C Compilers, enabling rapid development ofoptimized control applications.

The 56857 supports program execution from either internal or external memories. Two data operands canbe accessed from the on-chip Data RAM per instruction cycle. The 56857 also provides two externaldedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending onperipheral configuration.

The 56857 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of BootROM.

This controller also provides a full set of standard programmable peripherals that include 8-bit parallelHost Interface, Two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI),two Serial Communications Interfaces (SCI), and one Quad Timer. The ESSIs, SPI, SCIs IO and QuadTimer can be used as General Purpose Input/Outputs when its primary function is not required.



1.3 State of the Art Development Environment• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Product DocumentationThe four documents listed in Table 1-1 are required for a complete description of and proper design withthe 56857. Documentation is available from local Freescale distributors, Freescale Semiconductor salesoffices, Freescale Literature Distribution Centers, or online at www.freescale.com.

1.5 Data Sheet ConventionsThis data sheet uses the following conventions:

Table 1-1 56857 Chip Documentation

Topic Description Order Number

56800EReference Manual

Detailed description of the 56800E architecture, 16-bit core processor and the instruction set

56800ERM

DSP56857User’s Manual

Detailed description of memory, peripherals, and interfaces of the 56857

DSP5685xUM

DSP56857Technical Data Sheet

Electrical and timing specifications, pin descriptions, and package descriptions (this document)

DSP56857

DSP56857Errata

Details any chip issues that might be present DSP56857E

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Examples: Signal/Symbol Logic State Signal State Voltage1

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

Introduction



Part 2 Signal/Connection Descriptions

2.1 IntroductionThe input and output signals of the 56857 are organized into functional groups, as shown in Table 2-1 andas illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signalspresent.

1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA2. MODE A, MODE B and MODE C can be used as GPIO after the bootstrap process has completed.

3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.

Table 2-1 Functional Group Pin Allocations

Functional Group Number of Pins

Power (VDD, VDDIO, or VDDA) (8, 12, 1)1

Ground (VSS, VSSIO,or VSSA) (5, 12, 2)1

PLL and Clock 3

Chip Select Logic used as dedicated GPIO 4

Interrupt and Program Control 72

Host Interface (HI)* 163

Enhanced Synchronous Serial Interface (ESSI0) Port* 6

Enhanced Synchronous Serial Interface (ESSI1) Port* 6

Serial Communications Interface (SCI0) Ports* 2

Serial Communications Interface (SCI1) Ports* 2

Serial Peripheral Interface (SPI) Port* 4

Quad Timer Module Port* 4

JTAG/Enhanced On-Chip Emulation (EOnCE) 6

*Alternately, GPIO pins



Figure 2-1 56857 Signals Identified by Functional Group2

1. Specifically for PLL, OSC, and POR.2. Alternate pin functions are shown in parentheses.

56857

LogicPower

I/OPower

SCI 0

JTAG /EnhancedOnCE

TimerModule

ESSI 0

SPI

ChipSelect

AnalogPower1

PLL / Clock

SCI 2

ESSI 1

Interrupt /Program

Control

VDDVSS

VDDIOVSSIO

VDDAVSSA

CS0 - CS3 (GPIOA0 - A3)

HD0 - HD7 (GPIOB0 - B7)

HA0 - HA2 (GPIOB8 - B10)

HRWB (HRD) (GPIOB11)

HDS (HWR) (GPIOB12)

HCS (GPIOB13)

HREQ (HTRQ) (GPIOB14)

HACK (HRRQ) (GPIOB15)

TIO0 - TIO3 (GPIOG0 - G3)

IRQA

IRQB

MODE A, MODE B, MODE C(GPIOH0 - H2)

RESET

RSTO

HostInterface

XTAL

RXDO (GPIOE0)

TXDO (GPIOE1)

RXD1 (GPIOE2)

TXD1 (GPIOE3)

STD0 (GPIOC0)

SRD0 (GPIOC1)SCK0 (GPIOC2)

SC00 (GPIOC3)

SC01 (GPIOC4)

SC02 (GPIOC5)

MISO (GPIOF0)

MOSI (GPIOF1)SCK (GPIOF2)

SS (GPIOF3)

STD1 (GPIOD0)

SRD1 (GPIOD1)SCK1 (GPIOD2)

SC10 (GPIOD3)

SC11 (GPIOD4)

SC12 (GPIOD5)

EXTAL

CLKO

TCK

TDI

TDO

TMS

TRST

DE

1

1

1

1

1

11

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

11

1

3

1

1

4

1

11

1

1

3

8

4

2

1

12

12

5

8

Introduction



Part 3 Signals and Package InformationAll digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits areenabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. MODE A, MODE B, and MODE C pins have no pull-up.3. TCK has a weak pull-down circuit always active.4. Bidirectional I/O pullups automatically disable when the output is enabled.

This table is presented consistently with the Signals Identified by Functional Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Output(Z) means an output in a High-Z condition.

Table 3-1 56857 Signal and Package Information for the 100-pin LQFP

Pin No. Signal Name Type Description

8 VDD VDD Power (VDD)—These pins provide power to the internal structures of the chip, and should all be attached to VDD.

25 VDD

36 VDD

50 VDD

59 VDD

60 VDD

76 VDD

87 VDD

9 VSS VSS Ground (VSS)—These pins provide grounding for the internal structures of the chip and should all be attached to VSS.

37 VSS

38 VSS

61 VSS

88 VSS



5 VDDIO VDDIO Power (VDDIO)—These pins provide power for all I/O and ESD structures of the chip, and should all be attached to VDDIO (3.3V).

6 VDDIO

13 VDDIO

34 VDDIO

45 VDDIO

47 VDDIO

48 VDDIO VDDIO Power (VDDIO)—These pins provide power for all I/O and ESD structures of the chip, and should all be attached to VDDIO (3.3V).

53 VDDIO

72 VDDIO

80 VDDIO

90 VDDIO

98 VDDIO

7 VSSIO VSSIO Ground (VSSIO)—These pins provide grounding for all I/O and ESD structures of the chip and should all be attached to VSS.

14 VSSIO

35 VSSIO

46 VSSIO

49 VSSIO

54 VSSIO

73 VSSIO

82 VSSIO

89 VSSIO

91 VSSIO

99 VSSIO

100 VSSIO

17 VDDA VDDA Analog Power (VDDA)—These pins supply an analog power source.

Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)


Introduction



18 VSSA VSSA Analog Ground (VSSA)—This pin supplies an analog ground.

19 VSSA

55 CS0

GPIOA0

Output

Input/Output

External Chip Select (CS0)—This pin is used as a dedicated GPIO.

Port A GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.

56 CS1

GPIOA1

Output

Input/Output



57 CS2

GPIOA2

Output

Input/Output



58 CS3

GPIOA3

Output

Input/Output



22 HD0

GPIOB0

Input

Input/Output

Host Address (HD0)—This input provides the address selection for HI registers.

This pin is disconnected internally.

Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.

23 HD1

GPIOB1

Input

Input/Output



Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pins when not configured for host port usage.

24 HD2

GPIOB2

Input

Input/Output








29 HD3

GPIOB3

Input

Input/Output




30 HD4

GPIOB4

Input

Input/Output




31 HD5

GPIOB5

Input

Input/Output




32 HD6

GPIOB6

Input

Input/Output




33 HD7

GPIOB7

Input

Input/Output




62 HA0

GPIOB8

Input

Input/Output

Host Address (HA0)—This input provides the address selection for HI registers.





Introduction



63 HA1

GPIOB9

Input

Input/Output




64 HA2

GPIOB10

Input

Input/Output




65 HRWB

HRD

GPIOB11

Input

Input

Input/Output

Host Read/Write (HRWB)—When the HI08 is programmed to interface to a single-data-strobe host bus and the HI function is selected, this signal is the Read/Write input.

These pins are disconnected internally.

Host Read Data (HRD)—This signal is the Read Data input when the HI08 is programmed to interface to a double-data-strobe host bus and the HI function is selected.

Port B GPIO (11) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.

83 HDS

HWR

GPIOB12

Input

Input

Input/Output

Host Data Strobe (HDS)—When the HI08 is programmed to interface to a single-data-strobe host bus and the HI function is selected, this input enables a data transfer on the HI when HCS is asserted.


Host Write Enable (HWR)—This signal is the Write Data input when the HI08 is programmed to interface to a double-data-strobe host bus and the HI function is selected.


84 HCS

GPIOB13

Input

Input/Output

Host Chip Select (HCS)—This input is the chip select input for the Host Interface.







85 HREQ

HTRQ

GPIOB14

Open Drain Output

Open Drain Output

Input/Output

Host Request (HREQ)—When the HI08 is programmed for HRMS=0 functionality (typically used on a single-data- strobe bus), this open drain output is used by the HI to request service from the host processor. The HREQ may be connected to an interrupt request pin of a host processor, a transfer request of a DMA controller, or a control input of external circuitry.


Transmit Host Request (HTRQ)—This signal is the Transmit Host Request output when the HI08 is programmed for HRMS=1 functionality and is typically used on a double-data-strobe bus.

Port B GPIO (14) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage.

86 HACK

HRRQ

GPIOB15

Input

Open Drain Output

Input/Output

Host Acknowledge (HACK)—When the HI08 is programmed for HRMS=0 functionality (typically used on a single-data-strobe bus), this input has two functions: (1) provide a Host Acknowledge signal for DMA transfers or (2) to control handshaking and provide a Host Interrupt Acknowledge compatible with the MC68000 family processors.

These pins are disconnected internally during reset.

Receive Host Request (HRRQ)—This signal is the Receive Host Request output when the HI08 is programmed for HRMS=1 functionality and is typically used on a double-data-strobe bus.


81 TIO0

GPIOG0

Input/Output

Input/Output

Timer Input/Output (TIO0)—This pin can be independently configured to be either a timer input source or an output flag.

Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin.

79 TIO1

GPIOG1

Input/Output

Input/Output



78 TIO2

GPIOG2

Input/Output

Input/Output





Introduction



77 TIO3

GPIOG3

Input/Output

Input/Output



15 IRQA Input External Interrupt Request A and B—The IRQA and IRQB inputs are asynchronous external interrupt requests that indicate that an external device is requesting service. A Schmitt trigger input is used for noise immunity. They can be programmed to be level-sensitive or negative-edge- triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for Wired-OR operation.

16 IRQB

10 MODE A

GPIOH0

Input

Input/Output

Mode Select (MODE A)—During the bootstrap process MODE A selects one of the eight bootstrap modes.

Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed.

11 MODE B

GPIOH1

Input

Input/Output

Mode Select (MODE B)—During the bootstrap process MODE B selects one of the eight bootstrap modes.

Port H GPIOH1—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed.

12 MODE C

GPIOH2

Input

Input/Output

Mode Select (MODE C)—During the bootstrap process MODE C selects one of the eight bootstrap modes.

Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed.

28 RESET Input Reset (RESET)—This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the MODE A, MODE B, and MODE C pins.

To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but do not assert TRST.

27 RSTO Output Reset Output (RSTO)—This output is asserted on any reset condition (external reset, low voltage, software or COP).

51 RXD0

GPIOE0

Input

Input/Output

Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial data and transfers it to the SCI 0 receive shift register.

Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin.





52 TXD0

GPIOE1

Output(Z)

Input/Output

Serial Transmit Data 0 (TXD0)—This signal transmits data from the SCI 0 transmit data register.


74 RXD1

GPIOE2

Input

Input/Output

Serial Receive Data 1 (RXD1)—This input receives byte-oriented serial data and transfers it to the SCI 1 receive shift register.


75 TXD1

GPIOE3

Output(Z)

Input/Output

Serial Transmit Data 1 (TXD1)—This signal transmits data from the SCI 1 transmit data register.


92 STD0

GPIOC0

Output

Input/Output

ESSI Transmit Data (STD0)—This output pin transmits serial data from the ESSI Transmitter Shift Register.

Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use.

93 SRD0

GPIOC1

Input

Input/Output

ESSI Receive Data (SRD0)—This input pin receives serial data and transfers the data to the ESSI Receive Shift Register.


94 SCK0

GPIOC2

Input/Output

Input/Output

ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode.


95 SC00

GPIOC3

Input/Output

Input/Output

ESSI Serial Control Pin 0 (SC00)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0.




Introduction



96 SC01

GPIOC4

Input/Output

Input/Output

ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1.


97 SC02

GPIOC5

Input/Output

Input/Output

ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation).


66 STD1

GPIOD0

Output

Input/Output

ESSI Transmit Data (STD1)—This output pin transmits serial data from the ESSI Transmitter Shift Register.

Port D GPIOD0—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use.

67 SRD1

GPIOD1

Input

Input/Output

ESSI Receive Data (SRD1)—This input pin receives serial data and transfers the data to the ESSI Receive Shift Register.

Port D GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use.

68 SCK1

GPIOD2

Input/Output

Input/Output

ESSI Serial Clock (SCK1)—This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode.


69 SC10

GPIOD3

Input/Output

Input/Output

ESSI Serial Control Pin 0 (SC10)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0.






70 SC11

GPIOD4

Input/Output

Input/Output

ESSI Serial Control Pin 1 (SC11)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1.


71 SC12

GPIOD5

Input/Output

Input/Output

ESSI Serial Control Pin 2 (SC12)—This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation).


1 MISO

GPIOF0

Input/Output

Input/Output

SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The driver on this pin can be configured as an open-drain driver by the SPI’s Wired-OR mode (WOM) bit when this pin is configured for SPI operation.

Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin.

2 MOSI

GPIOF1

Input/Output (Z)

Input/Output

SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. The driver on this pin can be configured as an open-drain driver by the SPI’s WOM bit when this pin is configured for SPI operation.

Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin.



Introduction



3 SCK

GPIOF2

Input/Output

Input/Output

SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit rate clock for the SPI. This gated clock signal is an input to a slave device and is generated as an output by a master device. Slave devices ignore the SCK signal unless the SS pin is active low. In both master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. The driver on this pin can be configured as an open-drain driver by the SPI’s WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device.


4 SS

GPIOF3

Input

Input/Output

SPI Slave Select (SS)—This input pin selects a slave device before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high.


20 XTAL Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal crystal oscillator output to an external crystal. If an external clock source other than a crystal oscillator is used, XTAL must be used as the input.

21 EXTAL Input External Crystal Oscillator Input (EXTAL)—This input should be connected to an external crystal. If an external clock source other than a crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2

26 CLKO Output Clock Output (CLKO)—This pin outputs a buffered clock signal. When enabled, this signal is the system clock divided by four.

44 TCK Input Test Clock Input (TCK)—This input pin provides a gated clock to synchronize the test logic and to shift serial data to the JTAG/Enhanced OnCE port. The pin is connected internally to a pull-down resistor.

42 TDI Input Test Data Input (TDI)—This input pin provides a serial input data stream to the JTAG/Enhanced OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

41 TDO Output(Z) Test Data Output (TDO)—This tri-statable output pin provides a serial output data stream from the JTAG/Enhanced OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK.

43 TMS Input Test Mode Select Input (TMS)—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.





40 TRST Input Test Reset (TRST)—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the Enhanced OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET. Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the Enhanced OnCE/JTAG module on the device.

Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor.

39 DE Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low signal. As an input, it is a means of entering debug mode of operation from an external command controller. As an output, it is a means of acknowledging that the chip has entered debug mode.

This pin is connected internally to a weak pull-up resistor.



General Characteristics



Part 4 Specifications

4.1 General CharacteristicsThe 56857 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. Theterm “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible processtechnology, to withstand a voltage up to 5.5V without damaging the device. Many systems have amixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3Vand 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability thereforeoffers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at themaximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanentdamage to the device.

The 56857 DC/AC electrical specifications are preliminary and are from design simulations. Thesespecifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalizedspecifications will be published after complete characterization and device qualifications have beencompleted.

CAUTION

This device contains protective circuitry to guardagainst damage due to high static voltage orelectrical fields. However, normal precautions areadvised to avoid application of any voltages higherthan maximum rated voltages to this high-impedancecircuit. Reliability of operation is enhanced if unusedinputs are tied to an appropriate voltage level.



Table 4-1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage, core VDD1

1. VDD must not exceed VDDIO

VSS – 0.3 VSS + 2.0 V

Supply voltage, IOSupply voltage, analog

VDDIO2

VDDIO2

2. VDDIO and VDDA must not differ by more that 0.5V

VSSIO – 0.3VSSA – 0.3

VSSIO + 4.0VDDA + 4.0

V

Digital input voltagesAnalog input voltages (XTAL, EXTAL)

VINVINA

VSSIO – 0.3VSSA – 0.3

VSSIO + 5.5VDDA + 0.3

V

Current drain per pin excluding VDD, GND I — 8 mA

Junction temperature TJ -40 120 °C

Storage temperature range TSTG -55 150 °C

Table 4-2 Recommended Operating Conditions


Supply voltage for Logic Power VDD 1.62 1.98 V

Supply voltage for I/O Power VDDIO 3.0 3.6 V

Supply voltage for Analog Power VDDA 3.0 3.6 V

Ambient operating temperature TA -40 85 °C

PLL clock frequency1

1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, andselected. The actual frequency depends on the source clock frequency and programming of the CGM module.

fpll — 240 MHz

Operating Frequency2

2. Master clock is derived from on of the following four sources:fclk = fxtal when the source clock is the direct clock to EXTALfclk = fpll when PLL is selectedfclk = fosc when the source clock is the crystal oscillator and PLL is not selectedfclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected

fop — 120 MHz

Frequency of peripheral bus fipb — 60 MHz

Frequency of external clock fclk — 240 MHz

Frequency of oscillator fosc 2 4 MHz

Frequency of clock via XTAL fxtal — 240 MHz

Frequency of clock via EXTAL fextal 2 4 MHz

DC Electrical Characteristics



4.2 DC Electrical Characteristics

Table 4-3 Thermal Characteristics1

1. See Section 6.1 for more detail.

Characteristic100-pin LQFP

Symbol Value Unit

Thermal resistance junction-to-ambient (estimated)

θJA 41.2 °C/W

I/O pin power dissipation PI/O User Determined W

Power dissipation PD PD = (IDD × VDD) + PI/O W

Maximum allowed PD PDMAX (TJ – TA) / RθJA 2

2. TJ = Junction TemperatureTA = Ambient Temperature

W

Table 4-4 DC Electrical Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Typ Max Unit

Input high voltage (XTAL/EXTAL) VIHC VDDA – 0.8 VDDA VDDA + 0.3 V

Input low voltage (XTAL/EXTAL) VILC -0.3 — 0.5 V

Input high voltage VIH 2.0 — 5.5 V

Input low voltage VIL -0.3 — 0.8 V

Input current low (pullups disabled) IIL -1 — 1 μA

Input current high (pullups disabled) IIH -1 — 1 μA

Output tri-state current low IOZL -10 — 10 μA

Output tri-state current high IOZH -10 — 10 μA

Output High Voltage VOH VDDIO – 0.7 — — V

Output Low Voltage VOL — — 0.4 V

Output High Current IOH 8 — 16 mA

Output Low Current IOL 8 — 16 mA

Input capacitance CIN — 8 — pF

Output capacitance COUT — 12 — pF

VDD supply current (Core logic, memories, peripherals)

Run 1

Deep Stop2

Light Stop3

IDD4

———

700.05

5

1101014

mAmAmA



Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)

VDDIO supply current (I/O circuity)

Run5

Deep Stop2

IDDIO— 40

0501.5

mAmA

VDDA supply current (analog circuity)

Deep Stop2IDDA

— 60 120 μA

Low Voltage Interrupt6 VEI — 2.5 2.85 V

Low Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV

Power on Reset7 POR — 1.5 2.0 V

Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.

1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.5. Running core and performing external memory access. Clock at 120 MHz.6. When VDD drops below VEI max value, an interrupt is generated.7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains activefor as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.

Table 4-4 DC Electrical Characteristics (Continued)Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


0

30

60

120

150

20 40 60 80 100 120

IDD

(mA

)

90

EMI Mode5 MAC Mode1

Supply Voltage Sequencing and Separation Cautions



4.3 Supply Voltage Sequencing and Separation CautionsFigure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.

Note: 1. VDD rising before VDDIO, VDDA2. VDDIO, VDDA rising much faster than VDD

Figure 4-2 Supply Voltage Sequencing and Separation Cautions

VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDDsupply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD fromrising faster than VDDIO.

VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).Typically this situation is avoided by using external discrete diodes in series between supplies, as shownin Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reachesapproximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins properoperation, the difference between supplies will typically be 0.8V and conduction through the diode chainreduces to essentially leakage current. During supply sequencing, the following general relationshipshould be adhered to: VDDIO > VDD > (VDDIO - 2.1V)

In practice, VDDA is typically connected directly to VDDIO with some filtering.

Figure 4-3 Example Circuit to Control Supply Sequencing

3.3V

1.8V

Time0

2

1

Supplies Stable

VDD

VDDIO, VDDA

DC

Pow

er S

uppl

y Vo

ltage

3.3VRegulator

1.8VRegulator

Supply

VDD

VDDIO, VDDA



4.4 AC Electrical CharacteristicsTiming waveforms in Section 4.4 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V forall pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of VIHand VIL for an input signal are shown.

Figure 4-4 Input Signal Measurement References

Figure 4-5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state• Tri-stated, when a bus or signal is placed in a high impedance state• Data Valid state, when a signal level has reached VOL or VOH• Data Invalid state, when a signal level is in transition between VOL and VOH

Figure 4-5 Signal States

VIH

VILFall Time

Input Signal

Note: The midpoint is VIL + (VIH – VIL)/2.

Midpoint1

Low High90%50%10%

Rise Time

Data Invalid State

Data1

Data2 Valid

DataTri-stated

Data3 Valid

Data2 Data3

Data1 Valid

Data Active Data Active

External Clock Operation



4.5 External Clock OperationThe 56857 system clock can be derived from a crystal or an external system clock signal. To generate areference frequency using the internal oscillator, a reference crystal must be connected between theEXTAL and XTAL pins.

4.5.1 Crystal OscillatorThe internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequencyrange specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit isshown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystalparameters determine the component values required to provide maximum stability and reliable start-up.The crystal and associated components should be mounted as close as possible to the EXTAL and XTALpins to minimize output distortion and start-up stabilization time.

Figure 4-6 Crystal Oscillator

4.5.2 High Speed External Clock Source (> 4MHz)The recommended method of connecting an external clock is given in Figure 4-7. The external clocksource is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL bitin CGM must be set to 0.

Figure 4-7 Connecting a High Speed External Clock Signal using XTAL

4.5.3 Low Speed External Clock Source (2-4MHz)The recommended method of connecting an external clock is given in Figure 4-8. The external clocksource is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must beset to 0.

Sample External Crystal Parameters:Rz = 10MΩTOD_SEL bit in CGM must be set to 0

Crystal Frequency = 2–4MHz (optimized for 4MHz)

EXTAL XTALRz

56857XTAL EXTAL

External GND,VDDA, Clock

(up to 240MHz)or VDDA/2



Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL

Figure 4-9 External Clock Timing

Table 4-5 External Clock Operation Timing Requirements4Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


Frequency of operation (external clock driver)1

1. See Figure 4-7 for details on using the recommended connection of an external clock driver.

fosc 0 — 240 MHz

Clock Pulse Width4 tPW 6.25 — — ns

External clock input rise time2, 4

2. External clock input rise time is measured from 10% to 90%.

trise — — TBD ns

External clock input fall time3, 4

3. External clock input fall time is measured from 90% to 10%.4. Parameters listed are guaranteed by design.

tfall — — TBD ns

56857XTAL EXTAL

External Clock

(2-4MHz)

VDDA/2

ExternalClock

VIH

VIL

Note: The midpoint is VIL + (VIH – VIL)/2.

90%50%10%

90%50%10% tPW tPW

tfall trise

Reset, Stop, Wait, Mode Select, and Interrupt Timing



4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 4-6 PLL TimingOperating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


External reference crystal frequency for the PLL1

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.The PLL is optimized for 4MHz input crystal.

fosc 2 4 4 MHz

PLL output frequency fclk 40 — 240 MHz

PLL stabilization time 2

2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

tplls — 1 10 ms

Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.

2. Parameters listed are guaranteed by design.

Characteristic Symbol Typ Min Typ Max Unit See Figure

Minimum RESET Assertion Duration3

3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock, txtal, textal or tosc.

tRA 30 — ns 4-10

Edge-sensitive Interrupt Request Width tIRW 1T + 3 — ns 4-11

IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine

tIG 18T — ns 4-12

IRQA Width Assertion to Recover from Stop State tIW 2T — ns 4-13

Delay from IRQA Assertion to Fetch of first instruction (exiting Stop)4 Fast5

Normal6, 7

4. This interrupt instruction fetch is visible on the pins only in Mode 3.

5. Fast stop mode: Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is request-

ed (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one lesscycle and tclk will continue with the same value it had before stop mode was entered.

6. Normal stop mode:As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,

recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.

tIF

——

13T25ET

nsns

4-13

RSTO pulse width7normal operationinternal reset mode

7. ET = External Clock period; for an external crystal frequency of 4MHz, ET=250ns.

tRSTO128ET

8ET——

——

4-14



Figure 4-10 Asynchronous Reset Timing

Figure 4-11 External Interrupt Timing (Negative-Edge-Sensitive)

Figure 4-12 External Level-Sensitive Interrupt Timing

Figure 4-13 Recovery from Stop State Using Asynchronous Interrupt Timing

Figure 4-14 Reset Output Timing

RESETtRA

IRQAIRQB tIRW

PurposeI/O Pin

IRQA,IRQB

b) General Purpose I/O

tIG

General

IRQA

tIW

RESETtRSTO

Host Interface Port



4.7 Host Interface Port

Table 4-8 Host Interface Port Timing1Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.

Characteristic Symbol Min Max Unit See Figure

Access time TACKDV — 13 ns 4-19

Disable time TACKDZ 3 — ns 4-19

Time to disassert TACKREQH 3.5 9 ns 4-194-22

Lead time TREQACKL 0 — ns 4-19 4-22

Access time TRADV — 13 ns 4-204-21

Disable time TRADX 5 — ns 4-204-21

Disable time TRADZ 3 — ns 4-204-21

Setup time TDACKS 3 — ns 4-22

Hold time TACKDH 1 — ns 4-22

Setup time TADSS 3 — ns 4-234-24

Hold time TDSAH 1 — ns 4-234-24

Pulse width TWDS 5 — ns 4-234-24

Time to re-assert1. After second write in 16-bit mode 2. After first write in 16-bit mode or after write in 8-bit mode

TACKREQL 4T + 55

5T + 913

nsns

4-194-22



Figure 4-15 Controller-to-Host DMA Read Model

Figure 4-16 Single Strobe Read Mode

Figure 4-17 Dual Strobe Read Mode

HACK

HD

HREQ

TACKDVTACKDZ

TREQACKL TACKREQLTACKREQH

TRADVTRADZ

TRADX

HA

HCS

HDS

HD

HRW

TRADV

TRADZ

TRADX

HA

HCS

HWR

HD

HRD

Host Interface Port



Figure 4-18 Host-to-Controller DMA Write Mode

Figure 4-19 Single Strobe Write Mode

Figure 4-20 Dual Strobe Write Mode

HACK

HREQ

HD

TDACKS TACKDH

TREQACKL TACKREQLTACKREQH

HA

HCS

HDS

HD

HRWTADSS

TADSS TDSAH

TDSAH

TWDS

TDSAH

HA

HCS

HWR

HD

HRD

TWDS

TADSS

TADSS

TDSAH



4.8 Serial Peripheral Interface (SPI) Timing


Table 4-9 SPI Timing 1Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit See Figure

Cycle timeMasterSlave

tC2525

——

nsns

4-21, 4-22, 4-23, 4-24

Enable lead timeMasterSlave

tELD—

12.5——

nsns

4-24

Enable lag timeMasterSlave

tELG—

12.5——

nsns

4-24

Clock (SCLK) high timeMaster Slave

tCH9

12.5——

nsns

4-21, 4-22, 4-23, 4-24

Clock (SCLK) low timeMaster Slave

tCL12

12.5——

nsns

4-24

Data set-up time required for inputsMaster Slave

tDS102

——

nsns

4-21, 4-22, 4-23, 4-24

Data hold time required for inputsMaster Slave

tDH02

——

nsns

4-21, 4-22, 4-23, 4-24

Access time (time to data active from high-impedance state)Slave

tA5 15

nsns

4-24

Disable time (hold time to high-impedance state)Slave

tD2 9

nsns

4-24

Data valid for outputsMasterSlave (after enable edge)

tDV——

214

nsns

4-21, 4-22, 4-23, 4-24

Data invalid MasterSlave

tDI00

——

nsns

4-21, 4-22, 4-23, 4-24

Rise timeMaster Slave

tR——

11.510.0

nsns

4-21, 4-22, 4-23, 4-24

Fall time Master Slave

tF——

9.79.0

nsns

4-21, 4-22, 4-23, 4-24

Serial Peripheral Interface (SPI) Timing



Figure 4-21 SPI Master Timing (CPHA = 0)

Figure 4-22 SPI Master Timing (CPHA = 1)

SCLK (CPOL = 0)(Output)


MISO(Input)

MOSI(Output)

MSB in Bits 14–1 LSB in

Master MSB out Bits 14–1 Master LSB out

SS(Input) SS is held High on master

tCtR

tF

tCH

tCL

tFtR

tCHtCH

tDV

tDHtDS

tDI tDI(ref)

tF tR

tCL



MISO(Input)

MOSI(Output)


Master MSB out Bits 14– 1 Master LSB out

SS(Input) SS is held High on master

tRtF

tC

tCH

tCL

tCH

tCL

tF

tDStDH

tR

tDItDV(ref) tDV

tF tR



Figure 4-23 SPI Slave Timing (CPHA = 0)

Figure 4-24 SPI Slave Timing (CPHA = 1)

SCLK (CPOL = 0)(Input)


MISO(Output)

MOSI(Input)

Slave MSB out Bits 14–1


SS(Input)

Slave LSB outtDS

tCL

tCL

tDI tDI

tCH

tCH

tR

tR

tELG

tDH

tELD

tC tF

tFtD

tA

tDV



MISO(Output)

MOSI(Input)

Slave MSB out Bits 14–1


SS(Input)

Slave LSB out

tELG

tDItDS

tDH

tELD

tC

tCLtCH

tR

tF

tF

tCL

tCH

tDV

tA

tDV

tRtD

Quad Timer Timing



4.9 Quad Timer Timing

Figure 4-25 Timer Timing

4.10 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 4-10 Quad Timer Timing1, 2Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.



Timer input period PIN 2T + 3 — ns

Timer input high/low period PINHL 1T + 3 — ns

Timer output period POUT 2T - 3 — ns

Timer output high/low period POUTHL 1T - 3 — ns

Table 4-11 ESSI Master Mode1 Switching CharacteristicsOperating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter Symbol Min Typ Max Units

SCK frequency fs — — 152 MHz

SCK period3 tSCKW 66.7 — — ns

SCK high time tSCKH 33.44 — — ns

SCK low time tSCKL 33.44 — — ns

Output clock rise/fall time — — 4 — ns

Timer Inputs

Timer Outputs

PINHL PINHLPIN

POUTHLPOUTHLPOUT



Delay from SCK high to SC2 (bl) high - Master5 tTFSBHM -1.0 — 1.0 ns

Delay from SCK high to SC2 (wl) high - Master5 tTFSWHM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (bl) high - Master5 tRFSBHM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (wl) high - Master5 tRFSWHM -1.0 — 1.0 ns

Delay from SCK high to SC2 (bl) low - Master5 tTFSBLM -1.0 — 1.0 ns

Delay from SCK high to SC2 (wl) low - Master5 tTFSWLM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (bl) low - Master5 tRFSBLM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (wl) low - Master5 tRFSWLM -1.0 — 1.0 ns

SCK high to STD enable from high impedance - Master tTXEM -0.1 — 2 ns

SCK high to STD valid - Master tTXVM -0.1 — 2 ns

SCK high to STD not valid - Master tTXNVM -0.1 — — ns

SCK high to STD high impedance - Master tTXHIM -4 — 0 ns

SRD Setup time before SC0 low - Master tSM 4 — — ns

SRD Hold time after SC0 low - Master tHM 4 — — ns

Synchronous Operation (in addition to standard internal clock parameters)

SRD Setup time before SCK low - Master tTSM 4 — — ns

SRD Hold time after SCK low - Master tTHM 4 — — ns

1. Master mode is internally generated clocks and frame syncs2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures.

4. 50 percent duty cycle5. bl = bit length; wl = word length

Table 4-11 ESSI Master Mode1 Switching Characteristics (Continued)Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


Enhanced Synchronous Serial Interface (ESSI) Timing



Figure 4-26 Master Mode Timing Diagram

Table 4-12 ESSI Slave Mode1 Switching CharacteristicsOperating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


SCK frequency fs — — 152 MHz

SCK period3 tSCKW 66.7 — — ns

SCK high time tSCKH 33.44 — — ns

SCK low time tSCKL 33.44 — — ns

Output clock rise/fall time — — 4 — ns

Delay from SCK high to SC2 (bl) high - Slave5 tTFSBHS -1 — 29 ns

Delay from SCK high to SC2 (wl) high - Slave5 tTFSWHS -1 — 29 ns

tTHMtTSM

tHMtSM

tRFSWLMtRFSWHM

tRFBLMtRFSBHM

tTXHIMtTXNVMtTXVM

tTXEM

tTFSWLMtTFSWHM

tTFSBLMtTFSBHM

tSCKL

tSCKWtSCKH

First Bit Last Bit

SCK output

SC2 (bl) output

SC2 (wl) output

STD

SC0 output

SC1 (bl) output

SC1 (wl) output

SRD



Delay from SC0 high to SC1 (bl) high - Slave5 tRFSBHS -1 — 29 ns

Delay from SC0 high to SC1 (wl) high - Slave5 tRFSWHS -1 — 29 ns

Delay from SCK high to SC2 (bl) low - Slave5 tTFSBLS -29 — 29 ns

Delay from SCK high to SC2 (wl) low - Slave5 tTFSWLS -29 — 29 ns

Delay from SC0 high to SC1 (bl) low - Slave5 tRFSBLS -29 — 29 ns

Delay from SC0 high to SC1 (wl) low - Slave5 tRFSWLS -29 — 29 ns

SCK high to STD enable from high impedance - Slave tTXES — — 15 ns

SCK high to STD valid - Slave tTXVS 4 — 15 ns

SC2 high to STD enable from high impedance (first bit) - Slave tFTXES 4 — 15 ns

SC2 high to STD valid (first bit) - Slave tFTXVS 4 — 15 ns

SCK high to STD not valid - Slave tTXNVS 4 — 15 ns

SCK high to STD high impedance - Slave tTXHIS 4 — 15 ns

SRD Setup time before SC0 low - Slave tSS 4 — — ns

SRD Hold time after SC0 low - Slave tHS 4 — — ns

Synchronous Operation (in addition to standard external clock parameters)

SRD Setup time before SCK low - Slave tTSS 4 — — ns

SRD Hold time after SCK low - Slave tTHS 4 — — ns

1. Slave mode is externally generated clocks and frame syncs2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures.

4. 50 percent duty cycle5. bl = bit length; wl = word length

Table 4-12 ESSI Slave Mode1 Switching Characteristics (Continued)Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


Serial Communication Interface (SCI) Timing



Figure 4-27 Slave Mode Clock Timing

4.11 Serial Communication Interface (SCI) Timing

Table 4-13 SCI Timing4Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz


Baud Rate1

1. fMAX is the frequency of operation of the system clock in MHz.

BR — (fMAX)/(32) Mbps

RXD2 Pulse Width

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXDPW 0.965/BR 1.04/BR ns

TXD3 Pulse Width

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.


TXDPW 0.965/BR 1.04/BR ns

tTHStTSS

tHStSS

tRFSWLStRFSWHS

tRFBLStRFSBHS

tTXHIS

tTXNVS

tFTXVS

tTXVS

tFTXES

tTXES

tTFSWLStTFSWHS

tTFSBLStTFSBHS

tSCKL

tSCKW

tSCKH

First Bit Last Bit

SCK input

SC2 (bl) input

SC2 (wl) input

STD

SC0 input

SC1 (bl) input

SC1 (wl) input

SRD



Figure 4-28 RXD Pulse Width

Figure 4-29 TXD Pulse Width

4.12 JTAG Timing

Table 4-14 JTAG Timing1, 3Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation, T = 8.33ns.


TCK frequency of operation2

2. TCK frequency of operation must be less than 1/4 the processor rate.3. Parameters listed are guaranteed by design.

fOP DC 30 MHz

TCK cycle time tCY 33.3 — ns

TCK clock pulse width tPW 16.6 — ns

TMS, TDI data setup time tDS 3 — ns

TMS, TDI data hold time tDH 3 — ns

TCK low to TDO data valid tDV — 12 ns

TCK low to TDO tri-state tTS — 10 ns

TRST assertion time tTRST 35 — ns

DE assertion time tDE 4T — ns

RXD SCI receive

data pin(Input) RXDPW

TXD SCI receive

data pin(Input) TXDPW

JTAG Timing



Figure 4-30 Test Clock Input Timing Diagram

Figure 4-31 Test Access Port Timing Diagram

Figure 4-32 TRST Timing Diagram

Figure 4-33 Enhanced OnCE—Debug Event

TCK(Input)

VM

VILVM = VIL + (VIH – VIL)/2

VM

VIH

tPWtPW

tCY

Input Data Valid

Output Data Valid

Output Data Valid

TCK(Input)

TDI

(Input)

TDO(Output)

TDO(Output)

TDO(Output)

TMS

tDV

tTS

tDV

tDS tDH

TRST(Input)

tTRST

DEtDE



4.13 GPIO Timing

Figure 4-34 GPIO Timing

Table 4-15 GPIO Timing1, 2Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns



GPIO input period PIN 2T + 3 — ns

GPIO input high/low period PINHL 1T + 3 — ns

GPIO output period POUT 2T - 3 — ns

GPIO output high/low period POUTHL 1T - 3 — ns

GPIO Inputs

GPIO Outputs

PINHL PINHLPIN

POUTHLPOUTHLPOUT

Package and Pin-Out Information 56857



Part 5 Packaging

5.1 Package and Pin-Out Information 56857This section contains package and pin-out information for the 100-pin LQFP configuration of the 56857.

Figure 5-1 Top View, 56857 100-pin LQFP Package

PIN 1

PIN 26PIN 51

PIN 76MISOMOSISCK

SSVDDIOVDDIOVSSIO

VDDVSS

MODAMODBMODCVDDIOVSSIOIRQAIRQBVDDAVSSAVSSAXTAL

EXTALHD0HD1HD2VDD

CLK

OR

STO

RE

SE

TH

D3

HD

4H

D5

HD

6H

D7

VD

DIO

VS

SIO

V DD

VS

SV

SS

DE

TRS

TTD

OTD

ITM

STC

K

VD

DIO

VD

DIO

TXD1RXD1VSSIOVDDIOSC12SC11SC10SCK1SRD1STD1HRWBHA2HA1HA0VSSVDDVDDCS3CS2CS1CS0VSSIOVDDIOTXDORXD0

VS

SIO

ES

DV

DD

IOS

C02

SC

01S

C00

SC

K0

SRD

0S

TD0

VS

SIO

VD

DIO

ES

DV

SS

VD

DH

ACK

HR

EQH

CS

HD

SV

SS

IOTI

O0

VD

DIO

TIO

1TI

O2

TIO

3E

SD

ORIENTATION MARK

VD

DIO

VS

SIO

VS

SIO

V DD



Table 5-1 56857 Pin Identification By Pin Number

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 MISO 26 CLKO 51 RXD0 76 VDD

2 MOSI 27 RSTO 52 TXD0 77 TIO3

3 SCK 28 RESET 53 VDDIO 78 TIO2

4 SS 29 HD3 54 VSSIO 79 TIO1

5 VDDIO 30 HD4 55 CS0 80 VDDIO

6 VDDIO 31 HD5 56 CS1 81 TIO0

7 VSSIO 32 HD6 57 CS2 82 VSSIO

8 VDD 33 HD7 58 CS3 83 HDS

9 VSS 34 VDDIO 59 VDD 84 HCS

10 MODA 35 VSSIO 60 VDD 85 HREQ

11 MODB 36 VDD 61 VSS 86 HACK

12 MODC 37 VSS 62 HA0 87 VDD

13 VDDIO 38 VSS 63 HA1 88 VSS

14 VSSIO 39 DE 64 HA2 89 VSSIO

15 IRQA 40 TRST 65 HRWB 90 VDDIO

16 IRQB 41 TDO 66 STD1 91 VSSIO

17 VDDA 42 TDI 67 SRD1 92 STD0

18 VSSA 43 TMS 68 SCK1 93 SRD0

19 VSSA 44 TCK 69 SC10 94 SCK0

20 XTAL 45 VDDIO 70 SC11 95 SC00

21 EXTAL 46 VSSIO 71 SC12 96 SC01

22 HD0 47 VDDIO 72 VDDIO 97 SC02

23 HD1 48 VDDIO 73 VSSIO 98 VDDIO

24 HD2 49 VSSIO 74 RXD1 99 VSSIO

25 VDD 50 VDD 75 TXD1 100 VSSIO

Package and Pin-Out Information 56857



Figure 5-2 100-pin LQPF Mechanical Information

Please see www.freescale.com for the most current case outline.

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DATUM PLANE -AB- IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-.

5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.070 (0.003).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.003).

9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.

AE

AE

AD

SEATING(24X PER SIDE)

R

GAUGE PLANE

DETAIL ADSECTION AE-AE

SV B

A

96X

X

EC

KH W

D

F

JN

9

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 13.950 14.050 0.549 0.553B 13.950 14.050 0.549 0.553C 1.400 1.600 0.055 0.063D 0.170 0.270 0.007 0.011E 1.350 1.450 0.053 0.057F 0.170 0.230 0.007 0.009G 0.500 BSC 0.020 BSCH 0.050 0.150 0.002 0.006J 0.090 0.200 0.004 0.008K 0.500 0.700 0.020 0.028M 12 REF 12 REFN 0.090 0.160 0.004 0.006Q 1 5 1 5 R 0.150 0.250 0.006 0.010S 15.950 16.050 0.628 0.632V 15.950 16.050 0.628 0.632W 0.200 REF 0.008 REFX 1.000 REF 0.039 REF

° °

° °° °

-T-

ST-US0.15 (0.006) Z SACS

T-U

S0.

15 (0

.006

)Z

SA

C

ST-

US

0.15

(0.0

06)

ZS

AC

-U-

ST-US0.15 (0.006) Z SAB

-Z-

-AC-G

PLANE

-AB-

ST-UM0.20 (0.008) Z SAC

0.100 (0.004) AC

Q°

M°

0.25 (0.010)



Part 6 Design Considerations

6.1 Thermal Design ConsiderationsAn estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

Equation 1: TJ = TA + (PD x RθJA)

Where:

TA = ambient temperature °CRθJA = package junction-to-ambient thermal resistance °C/WPD = power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance anda case-to-ambient thermal resistance:

Equation 2: RθJA = RθJC + RθCA

Where:

RθJA = package junction-to-ambient thermal resistance °C/WRθJC = package junction-to-case thermal resistance °C/WRθCA = package case-to-ambient thermal resistance °C/W

RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment tochange the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow aroundthe device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), orotherwise change the thermal dissipation capability of the area surrounding the device on the PCB. Thismodel is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated throughthe case to the heat sink and out to the ambient environment. For ceramic packages, in situations wherethe heat flow is split between a path to the case and an alternate path through the PCB, analysis of thedevice thermal performance may need the additional modeling capability of a system level thermalsimulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to whichthe package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whetherthe thermal performance is adequate, a system level model may be appropriate.

A complicating factor is the existence of three common definitions for determining the junction-to-casethermal resistance in plastic packages:

• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface.

• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance.

• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple.

Electrical Design Considerations



As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using thefirst definition. From a practical standpoint, that value is also suitable for determining the junctiontemperature from a case thermocouple reading in forced convection environments. In natural convection,using the junction-to-case thermal resistance to estimate junction temperature from a thermocouplereading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence,the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD.This value gives a better estimate of the junction temperature in natural convection when using the surfacetemperature of the package. Remember that surface temperature readings of packages are subject tosignificant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heatloss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to thetop center of the package with thermally conductive epoxy.

6.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the board ground to each VSS (GND) pin.

• The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead.

• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.

• Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade capacitor such as a tantalum capacitor.

• Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits.

• All inputs must be terminated (i.e., not allowed to float) using CMOS levels.

CAUTION

This device contains protective circuitry to guard againstdamage due to high static voltage or electrical fields.However, normal precautions are advised to avoidapplication of any voltages higher than maximum ratedvoltages to this high-impedance circuit. Reliability ofoperation is enhanced if unused inputs are tied to anappropriate voltage level.



• Take special care to minimize noise levels on the VDDA and VSSA pins.• When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.• Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as

development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together.

• The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on.

Electrical Design Considerations



Part 7 Ordering InformationTable 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductorsales office or authorized distributor to determine availability and to order parts.

*This package is RoHS compliant.

Table 7-1 56857 Ordering Information

Part SupplyVoltage Package TypePin

CountFrequency

(MHz) Order Number

DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 100 120 DSP56857BU120

DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 100 120 DSP56857BUE *

How to Reach Us:

Home Page:www.freescale.com

E-mail:[email protected]

USA/Europe or Locations Not Listed:Freescale SemiconductorTechnical Information Center, CH3701300 N. Alma School RoadChandler, Arizona 85224+1-800-521-6274 or [email protected]

Europe, Middle East, and Africa:Freescale Halbleiter Deutschland GmbHTechnical Information CenterSchatzbogen 781829 Muenchen, Germany+44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)[email protected]

Japan:Freescale Semiconductor Japan Ltd.HeadquartersARCO Tower 15F1-8-1, Shimo-Meguro, Meguro-ku,Tokyo 153-0064, Japan0120 191014 or +81 3 5437 [email protected]

Asia/Pacific:Freescale Semiconductor Hong Kong Ltd.Technical Information Center2 Dai King StreetTai Po Industrial EstateTai Po, N.T., Hong Kong+800 2666 [email protected]

For Literature Requests Only:Freescale Semiconductor Literature Distribution CenterP.O. Box 5405Denver, Colorado 802171-800-441-2447 or 303-675-2140Fax: [email protected]

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.This product incorporates SuperFlash® technology licensed from SST.© Freescale Semiconductor, Inc. 2005. All rights reserved.

DSP56857Rev. 601/2007

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Part 1 Overview1.1 56857 Features1.1.1 Digital Signal Processing Core1.1.2 Memory1.1.3 Peripheral Circuits for 568571.1.4 Energy Information

1.2 56857 Description1.3 State of the Art Development Environment1.4 Product Documentation1.5 Data Sheet Conventions

Part 2 Signal/Connection Descriptions2.1 Introduction

Part 3 Signals and Package InformationPart 4 Specifications4.1 General Characteristics4.2 DC Electrical Characteristics4.3 Supply Voltage Sequencing and Separation Cautions4.4 AC Electrical Characteristics4.5 External Clock Operation4.5.1 Crystal Oscillator4.5.2 High Speed External Clock Source (> 4MHz)4.5.3 Low Speed External Clock Source (2-4MHz)

4.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing4.7 Host Interface Port4.8 Serial Peripheral Interface (SPI) Timing4.9 Quad Timer Timing4.10 Enhanced Synchronous Serial Interface (ESSI) Timing4.11 Serial Communication Interface (SCI) Timing4.12 JTAG Timing4.13 GPIO Timing

Part 5 Packaging5.1 Package and Pin-Out Information 56857

Part 6 Design Considerations6.1 Thermal Design Considerations6.2 Electrical Design Considerations

Part 7 Ordering Information

/ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 300 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages true /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 1200 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None

dsp56857, 56857 - data sheet - farnell element14 · 2015. 4. 28. · sc02 (gpioc5) miso (gpiof0)...

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