EE4340 Homework 7 Solution

Spring 2020

Contents

1 Question 1 11.1 Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Part 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.5 Part 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Note: You don’t need this much detail in your submission. It is included for your reference.

1 Question 1

In the following feedback diagram, replace the main and dummy amplifiers by the two-stage Miller-compensated gain stage you designed in Assignment 6. Use the same device sizes and biasing conditionsyou obtained before. Also, use ideal VCVS to implement the feedback network β = 1

2 and the subtractionfunctions. Since the amplifier you designed does not have a pair of differential inputs, the purpose of thedummy amp is to properly handle the DC bias conditions in the feedback connection, i.e., only the ACpart of the output signal is fed back to the summing node. Perform simulations in SPICE or Spectre.

Figure 1: Problem #1 Circuit

In order to keep the work organized, we can reproduce the amplifier designed in homework 6 in its ownschematic. This is not required, but it looks neater.

To do this, place an output pin on the output, and replace the input with an input pin. You can place pinsin Create > Pin or by using the hotkey p.

1

Also, make sure to make the value of CC a parameter so that it can be varied later, and do not include anyvoltage sources (VDD or Vin) in the schematic.

Figure 2: Homework 6 Amplifier Schematic

Next, we can create a symbol in Create > Cellview > From Cellview by clicking OK through thewindows that pop up.

Then in a separate schematic, we can place the amplifier in the usual insert window by setting the library as

EE4340 (or whatever you called your project library) instead of analogLib . Adding the other components

from analogLib as usual, the circuit looks like:

2

Figure 3: Overall SPICE Schematic

Where the node labeled Voac is the AC output voltage.

1.1 Part 1

Perform .op to verify that your circuit is properly biased. You should expect the inputs of the twoamplifiers be biased at VDD/2 and the two outputs should also be close to that voltage.

By saving the DC operating point, we can check the voltages at each of the points that should be at VDD/2.In the results browser, you will need to go down another level to see voltages within the dummy or mainamplifier.

Voltage Name in Simulation Main Amp Dummy AmpVi M1/vgs 1.250V 1.250VVx M2/vgs 1.250V 1.250VVo M2/vds 1.271V 1.271V

These are all close to VDD/2.

1.2 Part 2

Replace the voltage source Vi by an AC source (no DC) and perform an AC simulation. Extract theloop-gain and produce its Bode plot (think about how to accomplish this). Vary the value of Cc andproduce a family of the Bode plots. Measure the gain margin (GM) and phase margin (PM) from theBode plots and compare with your results from Assignment 6.

To get the Bode plot of the loop gain T (s) = βAOL(s), we can run an AC simulation with an AC input and

then plot the gain and phase of the output of Ebeta , the ideal feedback β. With CC = 0, we get:

3

Figure 4: Loop Gain Bode Plot, CC = 0

The DC magnitude is 6dB less than Av as expected, since β = 12 . We can see that the phase margin is 12

degrees. By sweeping CC from 0 to 1pF :

Figure 5: Loop Gain Bode Plot, CC Swept

From this plot and from the same simulation from homework 6, we can find the gain margin (0dB − |T (s)|when the phase is −180◦) and the phase margin (∠T (s) when the gain is 0dB) for each value of CC . Thiscould be done manually using markers on the Bode plots themselves.

4

To do this automatically, you can evaluate the following expression in the calculator (Tools > Calculator):

gainMargin(VF(”/betaVout”)/VF(”Vin”))

Where betaVout and Vin should be the names you gave the output net of the feedback amplifier β andthe input net of the main amplifier, respectively. The phase margin is calculated in a similar way:

phaseMargin(VF(”/betaVout”)/VF(”Vin”))

And for the AOL values, you can replace betaVout with Vo , or whatever you named the output net ofthe main amplifier. Doing all of this, we get:

T (s) = βAOL(s) AOL(s)CC Gain Margin Phase Margin Gain Margin Phase Margin0pF 19.56 dB 12.07◦ 13.54 dB 7.55◦

0.1pF 18.68 dB 39.73◦ 12.66 dB 25.25◦

0.2pF 18.59 dB 53.35◦ 12.57 dB 35.49◦

0.3pF 18.56 dB 61.13◦ 12.54 dB 42.60◦

0.4pF 18.55 dB 65.94◦ 12.52dB 47.85◦

0.5pF 18.54 dB 69.13◦ 12.51 dB 51.83◦

0.6pF 18.53 dB 71.38◦ 12.51 dB 54.94◦

0.7pF 18.52 dB 73.03◦ 12.50 dB 57.40◦

0.8pF 18.52 dB 74.29◦ 12.50 dB 59.39◦

0.9pF 18.52 dB 75.28◦ 12.50 dB 61.02◦

1pF 18.51 dB 76.08◦ 12.49 dB 62.39◦

We can see that the loop gain has a better gain margin and phase margin than the open loop gain, since βis not 1 (i.e. not unity feedback). We see that the gain margin improves by about 6dB, which is 1/β.

1.3 Part 3

In 2), produce the Nyquist diagram of the loop-gain with the same set of Cc values. Measure the GMand PM from the ND and compare with those obtained in 2).

In the calculator from the same simulation as part 2, you can generate a table of loop gain magnitudes by

entering mag(VF(”/betaVout”)/VF(”Vin”)) and hitting the evaluate into table button (table with green

arrow). By using File > Save as CSV, you can have a CSV of the data to be plotted in another program,such as MATLAB.

Similarly, for the phases you can evaluate phase(VF(”/betaVout”)/VF(”Vin”)) in the same way. Plotting

the magnitude versus the phase on a polar plot in MATLAB, we get:

5

Figure 6: Nyquist Plot

Zooming in, we can see where the plots cross the unit circle. The phase margins are the angle between thatpoint and −180◦:

Figure 7: Nyquist Plot, zoomed to show phase margins

Zooming in further, we can see where the plots cross the −180◦ line. The gain margins are the differencebetween the gain at −180◦ in dB and 0dB:

6

Figure 8: Nyquist Plot, zoomed to show gain margins

Using the margin function in MATLAB, we can also get the measured gain margins and phase margins for

the loop gain:

CC Gain Margin Phase Margin0pF 19.51 dB 12.03◦

0.1pF 18.66 dB 39.72◦

0.2pF 18.60 dB 53.37◦

0.3pF 18.56 dB 61.16◦

0.4pF 18.55 dB 65.94◦

0.5pF 18.53 dB 69.12◦

0.6pF 18.53 dB 71.39◦

0.7pF 18.51 dB 73.03◦

0.8pF 18.52 dB 74.26◦

0.9pF 18.52 dB 75.30◦

1pF 18.51 dB 76.05◦

Which match our results from part 2.

1.4 Part 4

Now replace Vi by a step function with a zero mean (why?). Perform .tran simulation with the various Ccvalues in 2) and 3) and check the settling behavior of the closed-loop amplifier. Record the relationshipbetween the PM from 3) and the settling behavior. In this step, you may choose a small input step of,say, 100 mV.

We want the step to have zero mean so that it steps around the operating point, and we want the magnitudeto be small so that it does not change that point by very much. In order to implement this, we can replace

the AC input voltage Viac with an instance of Vpulse that steps from -50mV to 50mV, setting a delay

so that we can see the step occur and setting the period and pulse width larger than the simulation time:

7

Figure 9: Vi Step Input Setup

By performing the same parametic sweep of CC as before, we get the following transient responses:

Figure 10: Transient Response, CC Swept

8

We see that the differential output changes by about 200mV, which makes sense since β = 12 , so the closed

loop gain is ideally 2. We also see that the response has less ringing as we increase CC , corresponding toincreasing the phase margin.

To accurately find the settling time, we need to plot the normalized settling error, which we can compute inthe as:

ε(t) =Vo(t)− Vof

Vof(1)

Where Vof = 1βVi is the final value to which the voltage settles. In the calculator, this would be

dB20((getData(”/Voac” ?result ”tran”)-100m)/100m) for this particular problem, since the differential Vosettles to 100mV. The resulting plot is:

Figure 11: Normalized Settling Error, CC Swept

For the sake of seeing how the settling time corresponds to the phase margin, let’s say we want the amplifierto settle to 6-bit accuracy, which means we need an error of −(6.02 ∗ 6 + 1.76)dB = −37.88dB. If we findthe point at which the error is always lower than this, we find the following results. The loop gain phasemargin from part 3 is included for reference.

CC Settling Time Phase Margin0pF 5.05 ns 12.03◦

0.1pF 2.48 ns 39.72◦

0.2pF 1.96 ns 53.37◦

0.3pF 2.18 ns 61.16◦

0.4pF 1.91 ns 65.94◦

0.5pF 1.44 ns 69.12◦

0.6pF 2.05 ns 71.39◦

0.7pF 2.71 ns 73.03◦

0.8pF 3.36 ns 74.26◦

0.9pF 3.95 ns 75.30◦

1pF 4.51 ns 76.05◦

So we see that increasing CC to improve the phase margin can improve the settling time some by decreasingringing, but if the pole is made too slow, then the increasing CC will increase the settling time. Note thatin the underdamped cases, it is hard to tell exactly when the output has settled.

9

1.5 Part 5

Increase the step size from 0.1 V gradually to 0.5 V (or even more) in 0.1-V steps. Repeat the transientsimulations and observe whether your amplifier experiences slewing (think about how to show this inthe simulation). Also, reverse the direction of the step function – if you used a rising step, now use afalling step, and vice versa – and repeat the simulations. In which direction do you observe slewing witha smaller step size? Why? You may fix the Cc value such that you have, say, a 60-degree PM in thisstep.

For these simulations, let’s select CC = 0.3fF so that our loop gain phase margin is at least 60◦. In order

to sweep the step size ∆V , we can use a parameter for Voltage 1 and Voltage 2 to make the step from−∆V

2 to ∆V2 . Doing this for steps up to 1V in size so we can see more slewing, we get the following outputs:

Figure 12: Transient Response, Rising Step, Step Size Swept

If there is slewing, then we will see that at some point, the speed at which the output changes will no longerbe proportional to the size of the step. This means we can see slewing by taking the slope of the output,

done using the deriv function in the calculator:

10

Figure 13: Slope of Transient Response, Rising Step, Step Size Swept

We can see once ∆V2 reaches 0.3V (meaning the step size is 0.6 V), we start seeing some significant slewing.

This can be seen more clearly by plotting the maximum slope versus the step size:

Figure 14: Maximum Slope vs Step Size, Rising Step

To test with the opposite step direction, a falling step, we can make our sweep parameter negative so thatthe voltage starts high and drops low. Doing the same transient simulation, we see the following outputs:

11

Figure 15: Transient Response, Falling Step, Step Size Swept

Again, we take the derivative to see the rate of change:

Figure 16: Slope of Transient Response, Falling Step, Step Size Swept

And by plotting the maximum slope, we can see that more slewing happens at a lower step size with thefalling step:

12

Figure 17: Maximum Slope vs Step Size, Falling Step

The falling step has more slewing because when rising, the load is charged by an ideal current source (thebiasing current source in our amplifier), while when discharging, it is discharged by a transistor.

13