eem 486 eem 486: computer architecture lecture 2 mips instruction set architecture
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EEM 486
EEM 486: Computer Architecture
Lecture 2
MIPS Instruction Set Architecture
Lec 2.2
Assembly Language
Basic job of a CPU: execute lots of instructions
Instructions are the primitive operations that the CPU may execute
Different CPUs implement different sets of instructions
The set of instructions a particular CPU implements is an Instruction Set Architecture (ISA)
• Examples: Intel 80x86 (Pentium 4), IBM/Motorola PowerPC (Macintosh), MIPS, Intel IA64, ...
Lec 2.3
Instruction Set Architecture (ISA)
“... the attributes of a [computing] system as seen by the
programmer, i.e., the conceptual structure and functional
behavior, as distinct from the organization of the data
flows and controls the logic design, and the physical
implementation.”
Amdahl, Blaaw, and Brooks, 1964
Lec 2.4
ISA
instruction set
software
hardware
Lec 2.5
ISA
swap(int v[], int k){int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp;}
swap: muli $2, $5,4 add $2, $4,$2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31
00000000101000010000000000011000000000001000111000011000001000011000110001100010000000000000000010001100111100100000000000000100101011001111001000000000000000001010110001100010000000000000010000000011111000000000000000001000
Binary machinelanguageprogram(for MIPS)
C compiler
Assembler
Assemblylanguageprogram(for MIPS)
High-levellanguageprogram(in C)
Lec 2.6
Instruction Set Architectures
Early trend was to add more and more instructions to new CPUs to do elaborate operations
• VAX architecture had an instruction to multiply polynomials!
RISC philosophy – Reduced Instruction Set Computing
• Keep the instruction set small and simple, makes it easier to build fast hardware.
• Let software do complicated operations by composing simpler ones.
Lec 2.7
MIPS Architecture
MIPS – semiconductor company that built one of the first commercial RISC architectures
We will study the MIPS architecture in some detail in this class
Why MIPS instead of Intel 80x86?• MIPS is simple, elegant. Don’t want to get bogged down in
gritty details.
• MIPS widely used in embedded apps, x86 little used in embedded, and more embedded computers than PCs
Lec 2.8
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
01998 2000 2001 20021999
Other
SPARC
Hitachi SH
PowerPC
Motorola 68K
MIPS
IA-32
ARM
Lec 2.9
Assembly Variables: Registers
Unlike HLL like C or Java, assembly cannot use variables
• Why not? Keep hardware simple
Assembly operands are registers• limited number of special locations built directly into the
hardware
• operations can only be performed on these!
Benefit: Since registers are directly in hardware, they are very fast (faster than 1 billionth of a second)
Lec 2.10
Assembly Variables: Registers
Drawback: Since registers are in hardware, there are a predetermined number of them
• Solution: MIPS code must be very carefully put together to efficiently use registers
How many registers?
Lec 2.11
Determining the number of registers?
Design principle: Smaller is faster
- A large number of registers would increase the clock cycle time
- Balance the craving of programs for more registers with the
desire to keep the clock cycle fast
32 registers in MIPS
Each MIPS register is 32 bits wide• Groups of 32 bits called a word in MIPS
Lec 2.12
Assembly Variables: Registers
MIPS registers are numbered from 0 to 31
Each register can be referred to by number or name
Number references: $0, $1, $2, … $30, $31
Lec 2.13
Assembly Variables: Registers
By convention, each register also has a name to make it easier to code
For now:$16 - $23 $s0 - $s7
(correspond to C variables)
$8 - $15 $t0 - $t7
(correspond to temporary variables)
In general, use names to make your code more readable
Lec 2.14
C variables vs. registers
In C (and most High Level Languages) variables declared first and given a type
int fahr, celsius; char a, b, c, d, e;
Each variable can ONLY represent a value of the type it was declared as (cannot mix and match int and char variables).
In Assembly Language, the registers have no type; operation determines how register contents are treated
Lec 2.15
MIPS Addition and Subtraction
Syntax of Instructions: opopd1, opd2, opd3
where:
op) operation by name
opd1) operand getting result (destination)
opd2) 1st operand for operation (source1)
opd3) 2nd operand for operation (source2)
Syntax is rigid:• 1 operator, 3 operands
• Why?
Lec 2.16
MIPS Addition and Subtraction
“The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple”
Design Principle: Keep hardware simple by regularity
Lec 2.17
Addition and Subtraction of Integers
Addition in Assembly• Example: add $s0, $s1, $s2 (in MIPS)
Equivalent to: a = b + c (in C)
• where MIPS registers $s0, $s1, $s2 are associated with C variables a, b, c
Subtraction in Assembly• Example: sub $s3, $s4, $s5 (in MIPS)
Equivalent to: d = e - f (in C)
where MIPS registers $s3, $s4, $s5 are associated with C variables d, e, f
Lec 2.18
Addition and Subtraction of Integers How do the following C statement?
a = b + c + d - e;
Break into multiple instructionsadd $t0, $s1, $s2 # temp = b + c
add $t0, $t0, $s3 # temp = temp + d
sub $s0, $t0, $s4 # a = temp - e
Notice: A single line of C may break up into several lines of MIPS.
Notice: Everything after the hash mark on each line is ignored (comments)
Lec 2.19
Addition and Subtraction of Integers
How do we do this?
f = (g + h) - (i + j);
Use intermediate temporary registeradd $t0,$s1,$s2 # temp = g + h
add $t1,$s3,$s4 # temp = i + j
sub $s0,$t0,$t1 # f=(g+h)-(i+j)
Lec 2.20
Register Zero
One particular immediate, the number zero (0), appears very often in code.
So, we define register zero ($0 or $zero) to always have the value 0; eg add $s0, $s1, $zero (in MIPS)
f = g (in C)
• where MIPS registers $s0, $s1 are associated with C variables f, g
Defined in hardware, so an instruction add $zero, $zero, $s0
will not do anything!
Lec 2.21
Immediates
Immediates are numerical constants
They appear often in code, so there are special instructions for them
Add Immediate:addi $s0,$s1,10 (in MIPS)
f = g + 10 (in C)
• where MIPS registers $s0, $s1 are associated with C variables f, g
Syntax similar to add instruction, except that last argument is a number instead of a register.
Lec 2.22
Immediates
There is no Subtract Immediate in MIPS. Why?
Limit types of operations that can be done to absolute minimum
• if an operation can be decomposed into a simpler operation, don’t include it
•addi …, -X = subi …, X => so no subi
addi $s0,$s1,-10 (in MIPS)
f = g - 10 (in C)• where MIPS registers $s0, $s1 are associated with C
variables f, g
Lec 2.23
Overflow in Arithmetic
Reminder: Overflow occurs when there is a mistake in arithmetic due to the limited precision in computers.
Example (4-bit unsigned numbers):+15 1111
+3 0011
+18 10010
• But we don’t have room for 5-bit solution, so the solution would be 0010, which is +2, and wrong.
Lec 2.24
Overflow in Arithmetic
Some languages detect overflow (Ada), some don’t (C)
MIPS solution is 2 kinds of arithmetic instructions to recognize 2 choices:
• add (add), add immediate (addi) and subtract (sub) cause overflow to be detected
• add unsigned (addu), add immediate unsigned (addiu) and subtract unsigned (subu) do not cause overflow detection
Compiler selects appropriate arithmetic• MIPS C compilers produce addu, addiu, subu
Lec 2.25
Assembly Operands: Memory
C variables map onto registers
What about large data structures like arrays?• only 32 registers provided
Memory contains such data structures
But MIPS arithmetic instructions only operate on registers, never directly on memory
Data transfer instructions transfer data between registers and memory:
• Memory to register
• Register to memory
Lec 2.26
Anatomy: 5 components of any Computer
Processor
Computer
Control(“brain”)
DatapathRegisters
Memory Devices
Input
OutputLoad (from)Load (from)
Store (to)Store (to)
These are “data transfer” instructions…
Registers are in the datapath of the processor
If operands are in memory, we must transfer them to the
processor to operate on them, and then transfer back to memory
when done
Lec 2.27
Memory Organization
Viewed as a large, single-dimension array, with an address
A memory address is an index into the array
"Byte addressing" means that the index points to a byte of memory
...
0
1
2
3
4
5
6
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
Lec 2.28
Memory Organization
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
0
4
8
12
...
32 bits of data
32 bits of data
32 bits of data
32 bits of data
Registers hold 32 bits of data
Lec 2.29
Big Endian: address of most significant byte = word address
• (xx00 = Big End of word)
• IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
Little Endian: address of least significant byte = word address
• (xx00 = Little End of word)
• Intel 80x86, DEC Vax, DEC Alpha (Windows NT)
msb lsb
3 2 1 0little endian byte 0
0 1 2 3big endian byte 0
Endianess
How do byte addresses map onto words?
Lec 2.30
0 1 2 3
Aligned
NotAligned
Alignment
Can a word be placed on any byte boundary?
Alignment: objects fall on address that is multiple of their size
MIPS require words to be always aligned, i.e,. start at addresses
that are multiples of four
Lec 2.31
Data Transfer: Memory to Reg
To transfer a word of data, we need to specify two things:
• Register: specify this by # ($0 - $31) or symbolic name ($s0,…, $t0, …)
• Memory address: more difficult
- We can address it simply by supplying a pointer to a memory address
- Other times, we want to be able to offset from this pointer
Remember: Load FROM memory
Lec 2.32
Data Transfer: Memory to Reg
To specify a memory address to copy from, specify two things:
• A register containing a pointer to memory
• A numerical offset (in bytes)
The desired memory address is the sum of these two values.
Example: 8($t0)• specifies the memory address pointed to by the value in $t0, plus 8 bytes
Lec 2.33
Data Transfer: Memory to Reg
Load Instruction Syntax:op opd1, opd2(opd3)
• where
op) operation name
op1) register that will receive value
op2) numerical offset in bytes
op3) register containing pointer to memory
MIPS Instruction Name:•lw (meaning Load Word, so 32 bits or one word are loaded
at a time)
Lec 2.34
Data Transfer: Memory to Reg
Example: lw $t0,12($s0)
This instruction will take the pointer in $s0, add 12 bytes to it, and then load the value from the memory pointed to by this calculated sum into register $t0
Notes:• $s0 is called the base register
• 12 is called the offset
• offset is generally used in accessing elements of array or structure: base reg points to beginning of array or structure
Data flow
Lec 2.35
Data Transfer: Reg to Memory
Also want to store from register into memory
• Store instruction syntax is identical to Load’s
MIPS Instruction Name:
sw (meaning Store Word, so 32 bits or one word are loaded at a time)
Example: sw $t0,12($s0)
This instruction will take the pointer in $s0, add 12 bytes to it, and then store the value from register $t0 into that memory address
Remember: Store INTO memory
Data flow
Lec 2.36
Compilation with Memory
What offset in lw to select A[5] in C?
4x5=20 to select A[5]: byte v. word
Compile by hand using registers:g = h + A[5];
g: $s1, h: $s2, $s3:base address of A
1st transfer from memory to register:
lw $t0,20($s3) # $t0 gets A[5]
add $s1,$s2,$t0 # $s1 = h + A[5]
Lec 2.37
Compilation with Memory
Example:
C code: A[12] = h + A[8];
MIPS code: lw $t0, 32($s3)add $t0, $s2, $t0sw $t0, 48($s3)
Store word has destination last
Remember arithmetic operands are registers, not memory!
Can’t write: add 48($s3), $s2, 32($s3)
Lec 2.38
Notes about Memory
Pitfall: Forgetting that sequential word addresses in machines with byte addressing do not differ by 1
• Remember that for both lw and sw, the sum of the base address and the offset must be a multiple of 4 (to be word aligned)
Lec 2.39
Pointers v. Values
Key Concept: A register can hold any 32-bit value. That value can be a (signed) int, an unsigned int, a pointer (memory address), and so on
If you write add $t2,$t1,$t0 then $t0 and $t1
better contain values
If you write lw $t2,0($t0)
then $t0 better contain a pointer
Don’t mix these up!
Lec 2.40
Role of Registers vs. Memory
What if more variables than registers?• Compiler tries to keep most frequently used variable in
registers
• Less common in memory: spilling
Why not keep all variables in memory?• Smaller is faster:
registers are faster than memory
• Registers more versatile:
- MIPS arithmetic instructions can read 2, operate on them, and write 1 per instruction
- MIPS data transfer only read or write 1 operand per instruction, and no operation
Lec 2.41
So far we’ve learned:
MIPS
- arithmetic on registers and immediates only - loading words but addressing bytes
Instruction Meaning
add $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1, $s2, $s3 $s1 = $s2 – $s3 addi $s1, $s2, 10 $s1 = $s2 + 10 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1
Lec 2.42
Loading, Storing Bytes
In addition to word data transfers (lw, sw), MIPS has byte data transfers:
load byte: lb
store byte: sb
same format as lw, sw
Lec 2.43
x
Loading, Storing Bytes
What do with other 24 bits in the 32 bit register?•lb: sign extends to fill upper 24 bits
byteloaded…is copied to “sign-extend”
This bit
xxxx xxxx xxxx xxxx xxxx xxxx zzz zzzz
• Normally don't want to sign extend chars
• MIPS instruction that doesn’t sign extend when
loading bytes:
load byte unsigned: lbu
Lec 2.44
So Far...
All instructions so far only manipulate data…we’ve built a calculator.
In order to build a computer, we need ability to make decisions…
C (and MIPS) provide labels to support “goto” jumps to places in code.
• C: Horrible style; MIPS: Necessary!
Lec 2.45
C Decisions: if Statements
2 kinds of if statements in C•if (condition) clause
•if (condition) clause1 else clause2
Rearrange 2nd if into following: if (condition) goto L1; clause2; goto L2;L1: clause1;
L2:
Not as elegant as if-else, but same meaning
Lec 2.46
MIPS Decision Instructions
Decision instruction in MIPS:•beq register1, register2, L1
•beq is “Branch if (registers are) equal” Same meaning as (using C): if (register1==register2) goto L1
Complementary MIPS decision instruction•bne register1, register2, L1
•bne is “Branch if (registers are) not equal” Same meaning as (using C): if (register1!=register2) goto L1
Called conditional branches
Lec 2.47
MIPS Goto Instruction
In addition to conditional branches, MIPS has an unconditional branch:
j label
Called a Jump Instruction: jump (or branch) directly to the given label without needing to satisfy any condition
Same meaning as (using C): goto label
Technically, it’s the same as:
beq $0,$0,label
since it always satisfies the condition.
Lec 2.48
Compiling C if into MIPS
Compile by handif (i == j) f=g+h; else f=g-h;
Use this mapping:
f: $s0 g: $s1 h: $s2 i: $s3 j: $s4
Exit
i == j?
f=g+h f=g-h
(false) i != j
(true) i == j
Lec 2.49
Compiling C if into MIPS
Final compiled MIPS code:
beq $s3,$s4,True # branch i==j sub $s0,$s1,$s2 # f=g-h(false) j Fin # goto FinTrue: add $s0,$s1,$s2 # f=g+h (true)Fin:
Compiler automatically creates labels to handle decisions (branches) –
Generally not found in HLL code.
Exit
i == j?
f=g+h f=g-h
(false) i != j
(true) i == j
• Compile by hand
if (i == j) f=g+h; else f=g-h;
Lec 2.50
Example: The C Switch Statement
Choose among four alternatives depending on whether k has the value 0, 1, 2 or 3. Compile this C code:
switch (k) { case 0: f=i+j; break; /* k=0 */ case 1: f=g+h; break; /* k=1 */ case 2: f=g–h; break; /* k=2 */ case 3: f=i–j; break; /* k=3 */}
Lec 2.51
Example: The C Switch Statement
This is complicated, so simplify.
Rewrite it as a chain of if-else statements, which we already know how to compile:if(k==0) f=i+j; else if(k==1) f=g+h; else if(k==2) f=g–h; else if(k==3) f=i–j;
Use this mapping: f:$s0, g:$s1, h:$s2,i:$s3, j:$s4, k:$s5
Lec 2.52
Example: The C Switch Statement
Final compiled MIPS code:
bne $s5,$0,L1 # branch k!=0 add $s0,$s3,$s4 #k==0 so f=i+j j Exit # end of case so ExitL1: addi $t0,$s5,-1 # $t0=k-1 bne $t0,$0,L2 # branch k!=1 add $s0,$s1,$s2 #k==1 so f=g+h j Exit # end of case so ExitL2: addi $t0,$s5,-2 # $t0=k-2 bne $t0,$0,L3 # branch k!=2 sub $s0,$s1,$s2 #k==2 so f=g-h j Exit # end of case so ExitL3: addi $t0,$s5,-3 # $t0=k-3 bne $t0,$0,Exit # branch k!=3 sub $s0,$s3,$s4 #k==3 so f=i-j Exit:
Lec 2.53
Loops in C/Assembly
Simple loop in C; A[] is an array of intsdo {
g = g + A[i];
i = i + j; } while (i != h);
Rewrite this as:Loop: g = g + A[i];
i = i + j;if (i != h) goto Loop;
Use this mapping: g, h, i, j, base of A $s1, $s2, $s3, $s4, $s5
Lec 2.54
Loops in C/Assembly
Final compiled MIPS code:
Loop: add $t1,$s3,$s3 #$t1= 2*i add $t1,$t1,$t1 #$t1= 4*i
add $t1,$t1,$s5 #$t1=addr A lw $t1,0($t1) #$t1=A[i] add $s1,$s1,$t1 #g=g+A[i] add $s3,$s3,$s4 #i=i+j bne $s3,$s2,Loop # goto Loop # if i!=h
Original code:Loop: g = g + A[i];
i = i + j;if (i != h) goto Loop;
Lec 2.55
Compiling a While Loop
C code: while (save[i] == k) i= i+j;
MIPS code:
Loop: add $t1, $s3, $s3 # $t1= 2*i add $t1, $t1, $t1 # $t1= 4*i add $t1, $t1, $s6 # $t1= address of save[i] lw $t0, 0($t1) # $t0= save[i] bne $t0, $s5, Exit # go to Exit if save[i] ≠ k add $s3, $s3, $s4 # i= i+j j Loop # go to Loop
Exit:
Lec 2.56
Inequalities in MIPS
Until now, we’ve only tested equalities (== and != in C)
General programs need to test < and > as well.
Create a MIPS Inequality Instruction:• “Set on Less Than”
• Syntax: slt reg1,reg2,reg3
• Meaning:
if (reg2 < reg3) reg1 = 1; else reg1 = 0;
Lec 2.57
Inequalities in MIPS
How do we use this? Compile by hand:
if (g < h) goto Less; #g:$s0, h:$s1
Answer: compiled MIPS code…
slt $t0,$s0,$s1 # $t0 = 1 if g<hbne $t0,$zero,Less # goto Less # if $t0!=0 # (if (g<h)) Less:
Branch if $t0 != 0 (g < h)
Register $0 always contains the value 0, so bne and beq often use it for comparison after an slt instruction.
A slt bne pair means if(… < …)goto…
Lec 2.58
Inequalities in MIPS
Now, we can implement <, but how do we implement >, ≤ and ≥ ?
We could add 3 more instructions, but:• MIPS goal: Simpler is Better
Can we implement ≤ in one or more instructions using just slt and the branches?
What about >?
What about ≥?
Lec 2.59
Immediates in Inequalities
There is also an immediate version of slt to test against constants: slti
• Helpful in for loops
if (g >= 1) goto Loop
Loop: . . .
slti $t0,$s0,1 # $t0 = 1 if # $s0<1 (g<1)beq $t0,$0,Loop # goto Loop # if $t0==0
# (if (g>=1))
C
MIPS
Lec 2.60
What about unsigned numbers?
Also unsigned inequality instructions:
sltu, sltiu
…which sets result to 1 or 0 depending on unsigned comparisons
What is value of $t0, $t1?
($s0 = FFFF FFFAhex, $s1 = 0000 FFFAhex
slt $t0, $s0, $s1
sltu $t1, $s0, $s1
Lec 2.61
MIPS Signed vs. Unsigned – diff meanings!
MIPS Signed v. Unsigned is an “overloaded” term
•Do/Don't sign extend(lb, lbu)
•Don't overflow (addu, addiu, subu, multu, divu)
•Do signed/unsigned compare(slt, slti/sltu, sltiu)
Lec 2.62
Bitwise Operations
Up until now, we’ve done arithmetic (add, sub,addi ), memory access (lw and sw), and branches and jumps
All of these instructions view contents of register as a single quantity (such as a signed or unsigned integer)
New Perspective: View register as 32 raw bits rather than as a single 32-bit number
Since registers are composed of 32 bits, we may want to access individual bits (or groups of bits) rather than the whole
Introduce two new classes of instructions:• Logical & Shift Ops
Lec 2.63
Logical Operators
Two basic logical operators:• AND: outputs 1 only if both inputs are 1
• OR: outputs 1 if at least one input is 1
Truth Table: standard table listing all possible combinations of inputs and resultant output for each
A B A AND B A OR B
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 1
Lec 2.64
Logical Operators Logical Instruction Syntax:
op opd1, opd2, opd3
• whereop) operation nameopd1) register that will receive valueopd2) first operand (register)opd3) second operand (register) or immediate
Lec 2.65
Logical Operators
Instruction Names:•and, or: Both of these expect the third argument to be a
register
•andi, ori: Both of these expect the third argument to be an immediate
MIPS Logical Operators are all bitwise, meaning that bit 0 of the output is produced by the respective bit 0’s of the inputs, bit 1 by the bit 1’s, etc.
• C: Bitwise AND is & (e.g., z = x & y;)
• C: Bitwise OR is | (e.g., z = x | y;)
Lec 2.66
Uses for Logical Operators
Note that anding a bit with 0 produces a 0 at the output while anding a bit with 1 produces the original bit.
This can be used to create a mask.• Example:
1011 0110 1010 0100 0011 1101 1001 1010
0000 0000 0000 0000 0000 1111 1111 1111
• The result of anding these:
0000 0000 0000 0000 0000 1101 1001 1010
Lec 2.67
Uses for Logical Operators
The second bitstring in the example is called a mask. It is used to isolate the rightmost 12 bits of the first bitstring by masking out the rest of the string (e.g. setting it to all 0s).
Thus, the and operator can be used to set certain portions of a bitstring to 0s, while leaving the rest alone.
• In particular, if the first bitstring in the above example were in $t0, then the following instruction would mask it:
andi $t0,$t0,0xFFF
Lec 2.68
Uses for Logical Operators
Similarly, note that oring a bit with 1 produces a 1 at the output while oring a bit with 0 produces the original bit.
This can be used to force certain bits of a string to 1s.
• For example, if $t0 contains 0x12345678, then after this instruction:
ori $t0, $t0, 0xFFFF
• … $t0 contains 0x1234FFFF (e.g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to 1s).
Lec 2.69
Shift Instructions
Move (shift) all the bits in a word to the left or right by a number of bits.
• Example: shift right by 8 bits
0001 0010 0011 0100 0101 0110 0111 1000
0000 0000 0001 0010 0011 0100 0101 0110
• Example: shift left by 8 bits
0001 0010 0011 0100 0101 0110 0111 1000
0011 0100 0101 0110 0111 1000 0000 0000
Lec 2.70
Shift Instructions
Shift Instruction Syntax:
op opd1, opd2, opd3
• whereop) operation nameopd1) register that will receive valueopd2) first operand (register)opd3) shift amount (constant < 32)
MIPS shift instructions:1. sll (shift left logical): shifts left and fills emptied bits with 0s2. srl (shift right logical): shifts right and fills emptied bits with 0s3. sra (shift right arithmetic): shifts right and fills emptied bits by
sign extending
Lec 2.71
Shift Instructions
Example: shift right arith by 8 bits0001 0010 0011 0100 0101 0110 0111 1000
0000 0000 0001 0010 0011 0100 0101 0110
Example: shift right arith by 8 bits1001 0010 0011 0100 0101 0110 0111 1000
1111 1111 1001 0010 0011 0100 0101 0110
Lec 2.72
Shift Instructions
Since shifting may be faster than multiplication, a good compiler usually notices when C code multiplies by a power of 2 and compiles it to a shift instruction:a *= 8; (in C)
would compile to:
sll $s0,$s0,3 (in MIPS)
Likewise, shift right to divide by powers of 2• remember to use sra