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DEPT OF ECE ELECTRONIC DEVICES AND CIRCUITS LAB

1 MLRIT, HYDERABAD-43

Experiment No:1

PN Junction Diode Characteristics

AIM: 1.a. Plot the Volt-Ampere characteristics of P-N junction diode 1N4007 for R=10 kΩ

Equipment required:

Bread board-----1No.

DC power supply (0-20V) -----1No.

Digital DC Voltmeter (0-20V) -----1No.

Digital DC Ammeters ( 0-200mA, 0-200µA)-----1No.

Components required:

Silicon Diode 1N 4007-----1No.

Resistor 10kΩ-----1 No

Connecting wires

Circuit diagrams:

1.1 Forward bias

Fig.1.1

1. 2 Reverse bias

Fig.1.2

10 kΩ A

+ 1N4007

V

+

(1-20V)

Reverse bias

(0-20V)

(0-200µA)

10 kΩ A

+

1N4007

V +

(1- 20V) (0-20V)

Forwad bias

(0-200mA)



Theory: The essential electrical characteristic of a p-n junction diode is that it constitutes a

diode which permits the easy flow of current in one direction but restrains the flow in the

opposite direction.

The flow of current is controlled by the way of biasing a diode. Depending upon the

polarity of the dc voltage externally applied to it, the biasing is classified as forward biasing and

reverse biasing of a diode.

Forward Bias: When the positive terminal of the battery is connected to the p-type and the

negative terminal to the n-type of the PN – junction diode, then the bias is said to be forward

bias. A p-n junction with forward bias is shown in the figure 1.1.

When the p-n junction is forward biased, as long as the applied voltage is less than the

barrier potential, there cannot be any conduction.

When the applied voltage becomes more than the barrier potential, the depletion region is

completely eliminated and the current flows through the junction called the forward current.

The forward potential at which the potential barrier across the junction is completely

eliminated and allows the current to flow through the junction is called cut-in voltage or

threshold voltage of p-n junction diode.

The cut-in voltage is 0.3V for Ge diode, and 0.7V for Si diode.

Reverse Bias: When the positive terminal of the battery is connected to the n-type and the

negative terminal to the p-type of the PN – junction diode, then the bias is said to be reverse bias.

A p-n junction with reverse bias is shown in the figure 1.2.

When the p-n junction is reverse biased the depletion region widens, the barrier potential

across the junction increases. The polarities of the barrier potential are same as that of the

applied reverse voltage.

In reverse bias condition, there is a flow of minority charge carriers across the junction,

and constitutes a small current called reverse saturation current. Reverse saturation current is

very small of the order of few microamperes for Ge and few nanoamperes for Si p-n junction

diodes.The generation of minority charge carriers depends on the temperature and not on the

applied reverse bias voltage.

The reverse saturation current increases by 7% per degree centigrade change in

temperature for both Si and Ge diodes. The reverse saturation current doubles for every 10˚C rise

in temperature.

Procedure:1. Construct the circuit as shown in the Fig1.1. Use 1N 4007 diode and forward

bias it.

2. Increase the power supply voltage gradually in steps and note the voltmeter and



Ammeter readings in Table -1.

3. Reverse-bias the diode, construct the circuit as shown in Fig:1.2. Use 1N 4007.

4. Icrease the power supply voltage in convenient steps and note down the micro

ammeter

Observations:

1. Forward Bias

VF

(Volts)

0 0.4 0.5 0.55 0.6 0.65 0.7 0.75 0.8

IF

(mA)

0 0 0.2 0.4 1 2 5.2 6.4 13.4

Table -1

2. Reverse Bias

VR

(Volts)

-0.3 -1.36 -1.8 -2.5 -3.5 -5 -6

IR

(μA)

0 -0.9 -1.3 -2 -2.9 -4.6 -5.7

Table -2

Model Graph:

Draw a Graph with volatage on X- axis and Current on Y-axis for both Diodes.

Forward bias is ploted in first Quadrant as in fig 1.3. Reverse bias in thired Quadrant

as shown in fig 1.4.

Fig. 1.3 Forward Bias Characteristics

Fig. 1.4 Reverse Bias Characteristics

Result: The characteristics of PN junction diode are plotted.

Ge Si

VD (V)

ID(mA)

0.3 0.7

Ir(µA)

VD(V)



REVIEW QUESTIONS :

1. What is doping?

2. What is cut-in or knee voltage and specify its value in Germanium and Silicon?

3. What is reverse saturation current of a diode?

4. What is depletion region?

5. What happens to depletion region on forward biasing and reverse biasing?

6. What are the specifications of a diode?

7. What is maximum forward current and maximum reverse voltage? Why is it

required?

8. What is the effect of temperature on diode reverse characteristics?

9. What is an ideal diode and how it differs from a real diode?

10. What is meant by a diode model? Name any two models.

11. What is diode equation?

12. What are the applications of a diode?



AIM: 1.b. Determine the cut-in voltage ,static and dynamic forward resistances of a PN junction

diode(1N4007) for R=1 kΩ

Equipment required:

Components required: same as 1.a

Circuit diagrams:

Theory:

Procedure:

Observations:

1. Forward Bias

VF

(Volts)

0 0.4 0.5 0.56 0.6 0.65 0.67 0.69 0.8

IF

(mA)

0 0 0.1 0.7 1.6 4.5 6.1 8.9 20

Table -1

2. Reverse Bias

VR

(Volts)

-0.18 -0.61 -0.78 -1.25 -1.54 -2.12 -2.32 -4.2

IR

(μA)

0 -0.1 -0.2 -0.7 -1 -1.6 -1.8 -5.8

Table -2

Model Graph: same as 1.a

Calculations:

Cut-in Voltage:

Draw a tangent to the forward bias characteristics curve at the point corresponding to ID =

0.1 ID(max). The point where the tangent cuts the x-axis is the cut-in voltage.

Static forward resistance:

f

f

f

VR

I in Ω=0.6/1.6mA = 375Ω

Dynamic forward resistance:

f

f

f

Vr

I

in Ω =(0.6-0.56)/(1.6-0.7)mA

=44.4Ω



Static reverse resistance:

Rr = Vr / Ir in MΩ= -0.78/-0.2µA =3.9 MΩ

Dynamic reverse resistance:

rr = ∆Vr / ∆Ir in MΩ=-(0.78+0.61)/-(0.2+0.1)µA

=4.63MΩ

Result: Cut in voltage=0.6

Static forward resistance=375Ω

Dynamic forward resistance=44.4Ω

Static reverse resistance=3.9MΩ

Dynamic reverse resistance=4.63MΩ



AIM: 1.c. Plot the V-I characteristics of silicon diode for R=1kΩ

Equipment required:


Circuit diagrams:

Theory:

Procedure:

Model Graph:

Observations: same as 1.b

Result: The characteristics of Silicon diode are plotted



AIM: 1.d. To plot the Volt-Ampere characteristics of P-N junction diode.(OA79-Ge) for

R=10KΩ

Equipment required:


Circuit diagrams: same as 1.a

Theory:

Procedure:

Observations:

1. Forward Bias

VF

(Volts)

0.16 0.17 0.19 0.21 0.22 0.23 0.24 0.3 0.45

IF

(mA)

0.1 0.1 0.2 0.3 0.4 0.5 0.6 1.0 2.1

Table -1

2. Reverse Bias

VR

(Volts)

-0.32 -1.3 -2.4 -3.5 -3.99 -5.29 -6.33 -7.3

IR

(μA)

-1.4 -3.1 -4.8 -6.6 -7.2 -9.2 -10.8 -12.2

Table -2

Model Graph: same as 1.b

Result: The characteristics of PN junction diode (OA79) are plotted



AIM: 1.e. Determine the cut-in voltage ,static and dynamic forward resistances of a germanium

diode(OA79-Ge)

Equipment required:



Theory:

Procedure:

Observations:

Calculations:

Cut-in Voltage:




f

f

f

VR

I in Ω=0.45/2.8 mA=160Ω


f

f

f

Vr

I

in Ω=(0.45-0.4)/(2.8-2.2)mA=83.3Ω

Static reverse resistance:

Rr = Vr / Ir in MΩ= -3.54/ -6.5µA =544KΩ

Dynamic reverse resistance:

rr = ∆Vr / ∆Ir in MΩ =-(3.54+2.67)/-(6.5+5.3)µA

=526KΩ

Result: Cut in voltage=0.35

Static forward resistance=160Ω

Dynamic forward resistance=83.3Ω

Static reverse resistance=544KΩ

Dynamic reverse resistance=526KΩ



Experiment No.2

ZENER DIODE CHARACTERISTICS

AIM: 2.a. Plot the Volt-Ampere characteristics of zener diode BZX5.1 for R=10 kΩ

Equipment required: Bread board-----1No.


Digital DC Voltmeter ( 0-20V)-----1No.

Digital DC Ammeter ( 0-200mA)-----1No.


Zener Diode BZX 5.1----1No.

Resistor 10kΩ-----1No

Circuit diagrams:

1 Forward bias

Fig.2.1

2 Reverse bias

Fig.2.2

Theory:

Zener diode is a heavily doped diode, and is designed with adequate power dissipation

capabilities to operate in the reverse breakdown region.

1 0kΩ A

+

V

+

(1-20V) (0-20V)

Reverse bias

(0-200mA)

1 0kΩ A

+

V +

(1-20V)

(0-20V)

Forwad bias

BZX5.1 (0-200mA)

BZX5.1



The operation of the zener diode is same as that of ordinary p-n diode under forward

biased condition.

In reverse biased condition, the diode carries reverse saturation current till the reverse

voltage applied is less than the reverse breakdown voltage.

When the reverse voltage exceeds the reverse breakdown voltage, the current through it changes

drastically but the voltage across it remains almost constant. Such a breakdown region is a

normal operating region for a zener diode.

The zener diode can be used as a voltage regulator.

Procedure:

1. Construct the circuit as shown in the Fig 2.1.Use BZX 5.1V diode and

forward bias it.

2. Increase the power supply voltage graduvally in steps and note the voltmeter and

Ammeter readings in Table -3.

3. Reverse-bias the diode,construct the circuit as shown in Fig 2.2.

4. Icrease the power supply voltage in convenient steps and note down the ammeter

and voltmeter readings in Table -4.

Observations:

1. Forward Bias

VF

(Volts)

0.4 0.64 0.67 0.69 0.7 0.71 0.72

IF

(mA)

0 0.1 0.2 0.4 0.5 0.9 1.2

Table -3

2. Reverse Bias

VR

(Volts)

-0.7 -4.01 -4.33 -4.42 -4.48 -4.53 -5.1

IR

(mA)

0 -0.1 -0.2 -0.3 -0.4 -0.5 -1.2

Table -4

Model Graph:

Draw a Graph with volatage on X- axis and Current on Y-axis for both

Forward bias and Reverse bias is ploted in first Quadrant and in thired Quadrant

Respectively as shown in Fig 2.3



Fig. 2.3 Forward & Reverse bias Characteristics

Result: The characteristics of zener diode is plotted.



REVIEW QUESTIONS :

1. What is Zener diode? How it is different from an ordinary diode?

2. What is Zener breakdown mechanism?

3. What type of biasing must be used when a Zener diode is used as a regulator?

4. What is the region of operation in which the Zener diode works?

5. Can zener be used as a rectifier?

6. What are the advantages of the zener diode?

7. What is the application of zener diode?

8. What are the factors that affect the stability?

9. Define voltage regulator.

10. Explain how the zener diode acts as a voltage regulator.



AIM: 2.b. Determine the cut-in voltage,dynamic forward resistance and zener break down

voltage of zener diode BZX5.1.for R=1kΩ

Equipment required:


Circuit diagrams:

Theory:

Procedure:

Observations:

1. Forward Bias

VF

(Volts)

0 0.3 0.66 0.68 0.7 0.72 0.74 0.75 0.77 0.8

IF

(mA)

0 0 0.3 0.6 0.9 1.4 2.3 3.8 5.6 7.5

Table -3

2. Reverse Bias

VR

(Volts)

-0.6 -1.29 -4.06 -4.57 -4.65 -4.92 -5.07 -5.1 -5.12

IR

(mA)

0 0 -0.1 -0.3 -0.5 -1.4 -2.8 -3.3 -4.0

Table -4


Calculations:

Cut-in Voltage:


0.1 ID(max). The point where the tangent cuts the x-axis is the cut-in voltage.=


f

f

f

VR

I in Ω=0.7/0.9mA=777Ω




f

f

f

Vr

I

in Ω=0.7-0.68/0.9-0.6mA=66.6Ω

Result: The Characteristics of the Forward and Reverse biased Zener Diode and the Zener Break Down Voltage from the Characteristics are Observed.

Zener Breakdown Voltage = -5Volts



AIM: 2.c. Plot the V-I characteristics of Zener diode.( BZX12.1) for R=10KΩ

Equipment required:



Theory:

Procedure:

Observations:

3. Forward Bias

VF

(Volts)

0 0.63 0.65 0.67 0.68 0.69 0.7 0.74

IF

(mA)

0 0.1 0.2 0.5 0.6 0.7 0.8 2.1

Table -3

4. Reverse Bias

VR

(Volts)

-0.4 -2.9 -12.14 -12.14 -12.15 -12.15 -12.16 -12.16

IR

(mA)

0 0 -0.1 -0.2 -0.3 -0.6 -0.7 -0.9

Table -4


Result: The characteristics of zener diode is plotted.



AIM: 2.d. Determine the cut-in voltage,Dynamic Forward Resistance and Zener break down

Voltage of a zener diode BZX12.1. for R=1KΩ

Equipment required:


Circuit diagrams:

Theory: same as 2.a

Procedure:

Model Graph:

Observations: same as 2.c

Calculations:

Cut-in Voltage: Draw a tangent to the forward bias characteristics curve at the point corresponding to ID =



f

f

f

VR

I in Ω=0.72/1.6mA=450Ω


f

f

f

Vr

I

in Ω= 0.72-0.7/(1.6-1)mA=33.3Ω

Result: The Characteristics of the Forward and Reverse biased Zener Diode and the Zener Break Down Voltage from the Characteristics are Observed.

Cut in voltage=0.72 volts

Zener Breakdown Voltage= - 12.1Volts



AIM: 2e .Plot the Volt-Ampere characteristics of zener diode BZX 9.1.R=1kΩ

Equipment required:


Circuit diagrams:

Theory:

Procedure:

Observations:

5. Forward Bias

VF

(Volts)

0.39 0.53 0.64 0.66 0.67 0.68 0.7 0.73 0.75 0.39

IF

(mA)

0 0 0.2 0.4 0.5 0.6 1.0 1.3 2.9 0

Table -3

6. Reverse Bias

VR

(Volts)

-0.7 -1.5 -4.2 -6.9 -9 -9.12 -9.14 -9.18

IR

(mA)

0 0 0 0 0.2 1.2 -2.5 -3.5

Table -4

\


Result: The characteristics of zener diode are plotted.



Experment No.3

HALF WAVE RECTIFIER WITHOUT & WITH FILTER

AIM: 3.a. Examine the input and out put wave forms of a half wave rectifier without and with

capacitor filter C=10µF, for various loads also find ripple factor.

Equipment required:

Bread board-----1No

C.R.O-----1No

AC Power supply12V-0-12V-----1No

Digital DCVoltmeter ( 0-20V)----- 1No

Digital AC Voltmeter ( 0-20V)-----1No


Diode 1N 4007-----1No

Resistors 390Ω,1kΩ,4.7kΩ,10kΩ-----1No Each.

Circuit diagrams:

Fig 3.1:Half Wave Rectifier Without Filter

Primary

Side

1N4007

RL V

+ Vo

Ch1 + - Ch2 + -

CRO

+

1'

12V

230V,50Hz AC Secondary

Side

0V

1

Step down

Transformer

ansformer



Fig 3.2:Half Wave Rectifier With Filter

THEORY:

During positive half-cycle of the input voltage, the diode D1 is in forward bias and

conducts through the load resistor R1. Hence the current produces an output voltage across the

load resistor R1, which has the same shape as the +ve half cycle of the input voltage. During the

negative half-cycle of the input voltage, the diode is reverse biased and there is no current

through the circuit. i.e., the voltage across R1 is zero.

The net result is that only the +ve half cycle of the input voltage appears across the load.

The average value of the half wave rectified o/p voltage is the value measured on dc voltmeter.

For practical circuits, transformer coupling is usually provided for two reasons.

1. The voltage can be stepped-up or stepped-down, as needed.

2. The ac source is electrically isolated from the rectifier. Thus preventing shock hazards in

the secondary circuit.

Procedure:

1. Construct the circuit as shown in Fig3.1Use the diode 1N 4007 and load

Resistance, RL.

2. Observe the voltage across the secondary of the transformer and across the out put

terminals 1-1’ by using CRO.

3. Remove the Load resistance from 1-1’ and note down no-load voltage,VNL

4. Vary the load RL in convenient steps and note the ac voltage and dc voltage

across the load.

5. Calculate ripple factor and regulation for different loads.

Primary

Side

Secondary

y

Side

1N4007

7

RL V +

Vo Ch1 + - Ch2 + -

CRO +

1

1'

12V

0V

230V, 50Hz AC

10 uF

uF

Step down

Transformer



6.Construct the circuit as shown in fig3.2Use the diode 1N 4007,Capacitor and load

resistance RL.Observe the voltage across the secondary of the transformer and

across the out put terminals 1-1’ by using CRO.



across the load.


10. Tabulate the readings as in Table 5&6.

Observations:

VNL= 5.9Volts

S.NO RL(Ω) VFL=VDC(Volts) VAC(Volts) Ripple

Factor=VAC/VDC

1 390

5.26 6.663 1.26

2 1K

5.45 6.87 1.26

3 4.7K

5.57 6.95 1.24

4 10K

5.67 7.05 1.25

Table3.1 Half Wave Rectifier Without Filter

VNL=18 Volts


Factor=VAC/VDC

1 390

7.27 3.23 0.43

2 1K

9.5

2.3 0.34

3 4.7K

14.15 1.89 0.13

4 10K

15.97 1.03 0.06

Table.3.2 Half Wave Rectifier With Filter



MODEL GRAPHS:

Result:

Ripple factor without filter at 1KΩ =1.26

Ripple factor with capacitor filter at 1KΩ =0.34



REVIEW QUESTIONS:

1. What is a rectifier? 2. How Diode acts as a rectifier? 3. What is the significance of PIV? What is the condition imposed on PIV? 4. Draw the o/p wave form without filter?

5. Draw the o/p wave form with filter? 6. What is meant by ripple factor? For a good filter whether ripple factor should be high

or low? 7. What is meant by regulation? 6. What is meant by time constant? 8. What happens to the o/p wave form if we increase the capacitor value? 9. What happens if we increase the capacitor value?



AIM: 3.b. Examine the input and out put wave forms of a half wave rectifier without and with

capacitor filter C=10µF also find percentage of regulation.

Equipment required:



THEORY:

Procedure:

Observations:

VNL= 5.9 Volts

S.NO RL(Ω) VFL=VDC(Volts) VAC(Volts) %Regulation=

(Vnl-

VFl/VFl)*100

1 390

5.26 6.663 12.1

2 1K

5.45 6.87 8.25

3 4.7K

5.57 6.95 5.9

4 10K

5.67 7.05 4.05

Table.5 Half Wave Rectifier Without Filter

VNL= 18 Volts

S.NO RL(Ω) VFL=VDC(Volts) VAC(Volts) %Regulation

(Vnl-

VFl/VFl)*100

1 390

7.27 3.23

147.5

2 1K

9.5

2.3 89.4

3 4.7K

14.15 1.89 27.2

4 10K

15.97 1.03 12.7

Table. 6 Half Wave Rectifier With Filter

MODEL GRAPHS: same as 3.a

Result:

Regulation without filter at 1KΩ =8.25

Regulation with capacitor filter at 1KΩ =89.4



AIM: 3.c. Examine the input and out put wave forms of a half wave rectifier without and with

capacitor filter C=470µF for various loads also find the ripple factor.

Equipment required:



Theory:

Procedure:

Observations: VNL= 5.9 Volts


Factor=VAC/VDC

1 390

5.26 6.663 1.26

2 1K

5.45 6.87 1.26

3 4.7K

5.57 6.95 1.24

4 10K

5.67 7.05 1.25


VNL= 17.13 Volts


Factor=VAC/VDC

1 390

12.54 0.41 0.032

2 1K

14.8 0.2 0.013

3 10K

17 0.1 0.0058



Result:


Ripple factor with capacitor filter at 1KΩ =0.013



AIM: 3.d. Examine the input and out put wave forms of a half rectifier without and with

capacitor filter C=470µF, for various loads also find percentage of regulation.

Equipment required:



Theory:

Procedure:



(Vnl-VFl/VFl)*100

1 390

5.26 6.663 12.1

2 1K

5.45 6.87 8.25

3 4.7K

5.57 6.95 5.9

4 10K

5.67 7.05 4.05


VNL= 17.13 Volts


(Vnl-

VFl/V36.6Fl)*100

1 390

12.54 0.41 36.6

2 1K

14.8 0.2 15.7

3 10K

17 0.1 0.7


MODEL GRAPH: same as 3.a

Result:





AIM: 3.e. Examine the input and out put wave forms of a half wave rectifier without and with

capacitor filter C=100µF for various loads. Also find percentage of regulation .

Equipment required:


Circuit diagrams

Theory:

Procedure:



Factor=VAC/VDC

%Regulation

(Vnl-

VFl/VFl)*100

1 390

5.26 6.663 1.26 12.1

2 1K

5.45 6.87 1.26 8.25

3 4.7K

5.57 6.95 1.24 5.9

4 10K

5.67 7.05 1.25 4.05


VNL= 17.43 Volts


Factor=VAC/VDC

%Regulation

(Vnl-

VFl/VFl)*100

1 390

11.4 0.53 0.046 52.89

2 1K

13.8 0.4 0.028 26.3

3 10K

16 0.3 0.1875 8.9


Model graph: same as 3.a

Result:


Ripple factor with filter at 1KΩ =0.028





Experment No.4

FULLWAVE RECTIFIER WITHOUT & WITH FILTER

AIM: 4.a.Examine the input and out put wave forms of a full wave rectifier without and with

capacitor filter C=10µF for various loads, also find the ripple factor.

Equipment required:

Bread board-----1No

C.R.O-----1No

AC Power supply12V-0-12V-----1No

Digital DCVoltmeter ( 0-20V)----- 1No

Digital AC Voltmeter ( 0-20V)-----1No


Diode 1N 4007-----2No’s.

Resistors 390Ω,1kΩ,4.7kΩ,10kΩ-----1No Each.

Circuit diagrams:

Fig 4.1:Full wave Rectifier Without Filter

D1 1N4007

RL V

+ Vo

Ch1 + - Ch2 + -

CRO

+ Primary

side

D2 1N4007

1

1' 12V

230V,50Hz AC 0V

12V

Secondary

Side

Center taped

Step down

Transformer



Fig 4.2:Full wave Rectifier With Filter

THEORY:

The circuit of a center-tapped full wave rectifier uses two diodes D1&D2. During

positive half cycle of secondary voltage (input voltage), the diode D1 is forward biased and D2is

reverse biased. The diode D1 conducts and current flows through load resistor RL. During

negative half cycle, diode D2 becomes forward biased and D1 reverse biased. Now, D2 conducts

and current flows through the load resistor RL in the same direction. There is a continuous

current flow through the load resistor RL, during both the half cycles and will get unidirectional

current as show in the model graph. The difference between full wave and half wave rectification

is that a full wave rectifier allows unidirectional (one way) current to the load during the entire

360 degrees of the input signal and half-wave rectifier allows this only during one half cycle

(180 degree).

Procedure:

1. Construct the circuit as shown in Fig 4.1Use the diodes 1N 4007 and load

resistance RL.

2.Observe the voltage across the secondary of the transformer and across the out

put terminals 1-1’ by using CRO.



across the load.


6.Construct the circuit as shown in Fig4.2Use the diodes 1N 4007,Capacitor and

D1 1N4007

RL V +

Vo Ch1 + - Ch2 + -

CRO

+ Primary

Side

Secondary

SIde

D2 1N4007

10uF

1

1'

12V

12V

230V, 50Hz AC

0V

Center taped

Step down

Transformer



load resistance RL.Observe the voltage across the secondary of the transformer

and across the out put terminals 1-1’ by using CRO.



across the load.


10. Tabulate the readings as in Table 7&8.

Observations:

VNL= 14.83 Volts


Factor=VAC/VDC

1 390

10.47 4.97 0.47

2 1K

10.8 5.11 0.473

3 4.7K

11.09 5.17 0.466

4 10K

11.14 5.25 0.4712

Table.1 FULL Wave Rectifier Without Filter

VNL= 17.89 Volts


Factor=VAC/VDC

1 390

11.5 2.2 0.1

2 1K

13.48 1.5 0.11

3 4.7K

16.3 0.84 0.051

4 10K

16.9 0.5 0.029

Table.2 FULL Wave Rectifier With Filter



MODEL GRAPH:

Result: The waveforms of full wave rectifier with & with filter are observed

Ripple factor without filter at 1KΩ = 0.473

Ripple factor with capacitor filter at 1KΩ = 0.11



REVIEW QUESTIONS:

1. What is a full wave rectifier? 2. How Diode acts as a rectifier? 3. What is the significance of PIV requirement of Diode in full-wave rectifier? 4. Compare capacitor filter with an inductor filter?

5. Draw the o/p wave form without filter? Draw the O/P? What is wave form with filter?

6. What is meant by ripple factor? For a good filter whether ripple factor should be high or low? What happens to the ripple factor if we insert the filter?

7. What is meant by regulation? Why regulation is poor in the case of inductor filter? 8. What is meant by time constant?

9. What happens to the o/p wave form if we increase the capacitor value? What happens if we increase the capacitor value?

10. What is the theoretical maximum value of ripple factor for a full wave rectifier?



AIM: 4.b. Examine the input and out put wave forms of a full wave rectifier without and with

capacitor filter C=10µF for various loads, also find regulation.

Equipment required:



Theory:

Procedure:

Observations:

VNL= 14.83 Volts


(Vnl-

VFl/VFl)*100

1 390

10.47 4.97 41.6

2 1K

10.8 5.11 37.3

3 4.7K

11.09 5.17 33.7

4 10K

11.14 5.25 33.12


VNL= 17.8 Volts


(Vnl-

VFl/VFl)*100

1 390

11.5 2.2 57

2 1K

13.48 1.5 32.7

3 4.7K

16.3 0.84 9.8

4 10K

16.9 0.5 5.9



Result: The waveforms of full wave rectifier with & with filter are observed





AIM:4.c. Examine the input and out put wave forms of a full wave rectifier without and with

capacitor filter C=470µF for various loads ,also find the ripple factor.

Equipment required: Components required same as 4.a

Circuit diagrams:

Theory:

Procedure:



Factor=VAC/VDC

1 390

10.47 4.97 0.47

2 1K

10.8 5.11 0.473

3 4.7K

11.09 5.17 0.466

4 10K

11.14 5.25 0.4712


VNL= 17.9 Volts


Factor=VAC/VDC

1 390

14.33 0.4 0.0279

2 1K

15.9 0.1 0.0062

3 4.7K

17.06 0.2 0.0117



Result:

Ripple factor without filter at 1KΩ = 0.473

Ripple factor with capacitor filter at 1KΩ = 0.0062



AIM:4.d. . Examine the input and out put wave forms of a full wave rectifier without and with

capictor filter C=470 µF for various loads,also find regulation.

Equipment required:


Circuit diagrams:

Theory:

Procedure:



(Vnl-

VFl/VFl)*100

1 390

10.47 4.97 41.6

2 1K

10.8 5.11 37.3

3 4.7K

11.09 5.17 33.7

4 10K

11.14 5.25 33.12


VNL= 17.8 Volts


(Vnl-

VFl/VFl)*100

1 390

14.33 0.4 24.2

2 1K

15.9 0.1 11.9

3 4.7K

17.06 0.2 4.3



Result: Regulation without filter at 1KΩ =37.3




AIM:4.e. Examine the input and out put wave forms of a full wave rectifier without and with

capacitor filter C=100µF for various loads, also find percentage of regulation .

Equipment required:


Circuit diagrams:

Theory:

Procedure:



Factor=VAC/VDC

%Regulation=

(Vnl-

VFl/VFl)*100

1 390

10.47 4.97 0.47 41.6

2 1K

10.8 5.11 0.473 37.3

3 4.7K

11.09 5.17 0.466 33.7

4 10K

11.14 5.25 0.4712 33.12


VNL= 18.1 Volts


Factor=VAC/VDC

%Regulation=

(Vnl-

VFl/VFl)*100

1 390

15.33 0.6 0.039 18.06

2 1K

16.1 0.35 0.021 12.4

3 4.7K

17.3 0.2 0.011 4.6



Result:

Ripple factor without filter at 1 KΩ =0.473

Ripple factor with filter at 1 KΩ =0.021





Experiment no:5

TRANSISTOR COMMON BASE CHARACTERISTICS

AIM: 5.a. Plot a family of output and input characteristics of a given transistor BC 107 (NPN)

connected in common base configuration. For input characteristics set VCB = 0V, VCB= 3V, For

Output characteristics IE= 1.2mA, 2.5mA

Equipment required:

Bread board-----1No

DC power supplies (0-20V) -----2No’s.

Digital DC Voltmeters (0-20V) –2No’s

Digital DC Ammeters (0-200mA) –2No’s.


Transistor BC 107 B(NPN) -----1No.

Resistors 1kΩ-----2No’s.

Circuit diagrams:

Fig:5.1 Transistor CB Input characteristics

NPN

(0-20)V) (0-20)V

A +

V +

V +

0-20V (0-20V)

0-200mA

VCB

VEB

IE

RE RC



Fig:5.2 Transistor CB Output characteristics

Theory:

In CB Configuration, the input signal is applied between emitter and base while the

output is taken from collector and base. As the base is common to input and output circuits,

hence the name common-base configuration.

Input Characteristics: To determine the input characteristics, the collector-base voltage VCB is

kept constant at zero volts and the emitter current IE is increased from zero in suitable equal steps

by increasing VEB. A curve is drawn between emitter current IE and emitter-base voltage VEB at

constant collector-base voltage VCB. The input characteristics thus obtained are shown in figure

5.2.

Output Characteristics: To determine the output characteristics, the emitter current IE is kept

constant at a suitable value by adjusting the emitter-base voltage VEB. Then VCB is increased in

suitable equal steps and the collector current IC is noted for each value of IE. This is repeated for

different fixed values of IE. Now the curves of IC versus VCB are plotted for constant values of IE

and the output characteristics thus obtained is shown in figure 5.3.

Procedure:

For plotting input characteristics:

1.To construct the circuit as shown in the Fig5.1.

2.Fix VCB=open=0V,by varying the out put power supply and note that input power

supply should be in minimum during VCB kept constant.

NPN

(0-20)V ( 0-20)V

A +

V +

A +

IC

0-20V

(0-200mA)

VCB

IE 0-200mA

RE RC



3.Now by varying input power supply ,change VEB in convenient steps and note

down the emitter current IE at each step.

4.Repeat steps 2 and 3 for different constant values of VCB=5V and 10V.

5.Tabulate the readings a in the Table-9.

Observations:

VCB =0 VOLTS VCB =3 VOLTS

VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

0.2 0 0.25 0

0.4 0 0.45 0

0.57 0.1 0.57 0.2

0.65 1 0.62 1.5

0.68 1.5 0.66 3.9

0.7 2.1 0.69 4.7

0.72 3 0.72 5.8

0.74 5.1 0.74 7.5

0.77 9.2 0.75 8

0.78 10.8 0.77 10.9

0.8 13.4 0.78 12.2

0.82 17.6 0.8 15.8

0.83 20.3 0.82 18.9

Table-5.1

For plotting output characteristics:

6. Set IE to 1.2 mA by varying the input power supply and note that output power

supply should be in minimum during IE kept constant.

7.Now by varying tout put power supply ,change VCB in convenient steps and note

down the collecter current IC at each voltage step.

8.Repeat steps 6 and 7 for constant values of IE equal to 2.1mA,3.1 mA and 4.1mA.

9.Tabulate the readings as in Table-10.

Observations:

IE =1.2mA IE =2.5mA

VCB

VOLTS

Ic mA VCB

VOLTS

Ic mA



-0.67 -0.69 -0.71 0.73

-0.73 -1.4 -0.69 1.4

-0.84 -1.4 -0.46 -2.76

-1.76 -1.4 0.39 -2.76

-2.07 -1.4 0.61 -2.76

-3 -1.4 1.48 -2.76

-5 -1.45 2.49 -2.8

-6 -1.45 3.5 -2.8

-8 -1.45 4.2 -2.9

9 -2.1 5 -2.9

10 -2.1 8 -3

11 -2.1 10 -3

12 -2.3 12 -3.1

14 -2.3 14 -3.1

Table-5.2

Model Graph:

1. Plot the family of input characteristics by taking emitter voltage VEB on X-

axis and Emitter current IE on Y-axis for constant values of output voltage VCB.

The model set of input characteristic curves are shown below in Fig 5.3.

2. Plot the family of output characteristics by taking collector voltage VCB on X-

axis and Collector current IC on Y-axis for constant values of input current IE .

The model set of output characteristic curves are shown below in Fig 5.4.

Result: The input & output characteristics of transistor in CB configuration are plotted.



AIM: 5.b. Find h-parameters hib, hrb, hob, and hfb of a given transistor BC 107 (NPN) connected

in common base configuration. For input characteristics set VCB = 0V, VCB= 5V, For Output

characteristics IE= 1.2mA, 2.5mA

Equipment required:



Theory:

Procedure:

Observations:


VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

0.2 0 0.3 0

0.4 0 0.45 0

0.57 0.1 0.56 0.2

0.65 1 0.61 1.1

0.68 1.5 0.63 2.1

0.7 2.1 0.65 5.1

0.72 3 0.69 6.2

0.74 5.1 0.72 7.4

0.77 9.2 0.74 8.5

0.78 10.8 0.75 9.8

0.8 13.4 0.77 11.4

0.82 17.6 0.8 16.7

0.83 20.3 0.82 20.7

Table-5.1

Observations:

IE =1.2mA IE =2.5mA

VCB

VOLTS

Ic mA VCB

VOLTS

Ic mA

-0.67 -0.69 -0.71 0.73

-0.73 -1.4 -0.69 1.4

-0.84 -1.4 -0.46 -2.76

-1.76 -1.4 0.39 -2.76

-2.07 -1.4 0.61 -2.76

-3 -1.4 1.48 -2.76

-5 -1.45 2.49 -2.8

-6 -1.45 3.5 -2.8

-8 -1.45 4.2 -2.9



9 -2.1 5 -2.9

10 -2.1 8 -3

11 -2.1 10 -3

12 -2.3 12 -3.1

14 -2.3 14 -3.1

Table-5.2


To find the h – parameters:

hib:

Mark two points on the Input characteristics for constant VCB. Let the coordinates of

these two points be (VEB1, IE1) and (VEB2, IE2).

VEB2 - VEB1

hib = ------- ------------

IE2-IE1

hib= 0.75-0.69/(8-4.7)mA

=18.18Ω

hrb: Draw a horizontal line at some constant IE value on the input characteristics. Find

VCB2, VCB1, VEB2, VEB1

VEB2 - VEB1

hrb = -----------------;

VCB2 - VCB1

=0.75-0.69/5-3=0.03

hfb: Draw a vertical line on the Output characteristics at some constant VCB value. Find

Ic2, Ic1 and IE2, IE1 .

I C2 –

IC1

hfb = ----------

I E2 -

IE1

=(2.76-2.5)mA/(1.45-1.2)mA=1.04

hob:



On the Output characteristics for a constant value of IE mark two points with coordinates

(VCB2 , IC2) and (VCB1 , IC1) .

I C2 -

IC1

hob = ------------

V CB2 -

VCB1

=(2.8-2.6)mA/2.49-1.48=40µὨ

Results:

The Input and Output characteristics are drawn on the graphs and the h parameters are calculated

.

hib=18.18Ω ohms. hrb= 0.03

hob= 40µ mhos. hfb = 1.04



AIM: 5.c. Plot a family of output and input characteristics of a given transistor BC 107 (NPN)

connected in common base configuration. For input characteristics set VCB = 3V, VCB= 5V, For

Output characteristics IE= 1.2mA, 2.5mA

Equipment required:


Circuit diagrams:

Theory:

Procedure:

Observations:


VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

0.25 0 0.3 0

0.45 0 0.45 0

0.57 0.2 0.56 0.2

0.62 1.5 0.61 1.1

0.66 3.9 0.63 2.1

0.69 4.7 0.65 5.1

0.72 5.8 0.69 6.2

0.74 7.5 0.72 7.4

0.75 8 0.74 8.5

0.77 10.9 0.75 9.8

0.78 12.2 0.77 11.4

0.8 15.8 0.8 16.7

0.82 18.9 0.82 20.7

Table-5.1

Observations:

IE =1.2mA IE =2.5mA

VCB

VOLTS

Ic mA VCB

VOLTS

Ic mA

-0.67 -0.69 -0.71 0.73

-0.73 -1.4 -0.69 1.4

-0.84 -1.4 -0.46 -2.76

-1.76 -1.4 0.39 -2.76

-2.07 -1.4 0.61 -2.76

-3 -1.4 1.48 -2.76

-5 -1.45 2.49 -2.8



-6 -1.45 3.5 -2.8

-8 -1.45 4.2 -2.9

9 -2.1 5 -2.9

10 -2.1 8 -3

11 -2.1 10 -3

12 -2.3 12 -3.1

14 -2.3 14 -3.1

Table-5.2


Results:

The Input and Output characteristics are drawn on the graphs and the h parameters are

calculated.



AIM: 5.d. Plot a family of output and input characteristics of a given BC557 (PNP) transistor

connected in common base configuration. . For input characteristics set VCB = 0V, VCB=3V,

VCB=5V. For Output characteristics IE= 1.2mA, 2.1mA and 4.1mA

Equipment required:



Theory:

Procedure:

Observations:

VCB =0 VOLTS VCB =3 VOLTS VCB =5 VOLTS

VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

0.1 0 0.2 0 0.1 0

0.3 0 0.4 0 0.5 0

0.56 0 0.57 0.1 0.56 0.1

0.59 0.3 0.6 0.4 0.6 0.6

0.63 0.6 0.62 1 0.62 1.2

0.68 1 0.63 1.8 0.64 2.9

0.73 1.8 0.65 2.8 0.66 4.6

0.75 2.2 0.66 3.7 0.69 5.7

0.77 2.8 0.72 4.5 0.73 6.3

0.79 3.5 0.77 5.4 0.77 7.4

0.8 4 0.78 5.8 0.82 8.5

Table-5.1

Observations:

IE =1.2mA IE =2.1mA IE =4.1mA

VCB

VOLTS

IE

mA

VCB

VOLTS

IE

mA

VCB

VOLTS

IE

mA

-0.67 -0.7 -0.73 -0.7 -0.74 -0.8

-0.63 -1 -0.69 -1.8 -0.7 -2.4

0.11 -1.3 -0.63 -2.7 -0.66 -3.4

1.36 -1.3 -0.59 -3.1 -0.58 -4.1

2.13 -1.3 -0.27 -3 0.11 -4.2

2.46 -1.3 0.43 -3.3 1.7 -4.2

3.37 -1.3 1.18 -3.3 3.4 -4.2

4.67 -1.3 2.79 -3.3 4.6 -4.2

5.5 -1.3 3.39 -3.3 5.02 -4.2

Table-5.2


Result: The input & output characteristics of transistor in CB configuration are plotted.



AIM: 5.e. Find h-parameters hib, hrb, hob, and hfb of a given transistor given BC557 (PNP)

transistor connected in common base configuration. . For input characteristics set VCB = 0V,

VCB=3V, VCB=5V. For Output characteristics IE= 1.2mA, 2.1mA and 4.1mA

Equipment required:


Circuit diagrams:

Theory:

Procedure:

Observations:

VCB =0 VOLTS VCB =3 VOLTS VCB =5 VOLTS

VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

VEB

VOLTS

IE

mA

0.1 0 0.2 0 0.1 0

0.3 0 0.4 0 0.5 0

0.56 0 0.57 0.1 0.56 0.1

0.59 0.3 0.6 0.4 0.6 0.6

0.63 0.6 0.62 1 0.62 1.2

0.68 1 0.63 1.8 0.64 2.9

0.73 1.8 0.65 2.8 0.66 4.6

0.75 2.2 0.66 3.7 0.69 5.7

0.77 2.8 0.72 4.5 0.73 6.3

0.79 3.5 0.77 5.4 0.77 7.4

0.8 4 0.78 5.8 0.82 8.5

Table-5.1

Observations:

IE =1.2mA IE =2.1mA IE =4.1mA

VCB

VOLTS

Ic

mA

VCB

VOLTS

Ic

mA

VCB

VOLTS

Ic

mA

-0.67 -0.7 -0.73 -0.7 -0.74 -0.8

-0.63 -1 -0.69 -1.8 -0.7 -2.4

0.11 -1.3 -0.63 -2.7 -0.66 -3.4

1.36 -1.3 -0.59 -3.1 -0.58 -4.1

2.13 -1.3 -0.27 -3 0.11 -4.2

2.46 -1.3 0.43 -3.3 1.7 -4.2

3.37 -1.3 1.18 -3.3 3.4 -4.2

4.67 -1.3 2.79 -3.3 4.6 -4.2

5.5 -1.3 3.39 -3.3 5.02 -4.2

Table-5.2




To find the h – parameters:

Calculation of hib:

Mark two points on the Input characteristics for constant VCB. Let the coordinates of

these two points be (VEB1, IE1) and (VEB2, IE2).

VEB2 - VEB1

hib = ------- ------------

IE2-IE1

=0.79-0.63/(3.5-1)mA=44Ω

Calculation of hrb: Draw a horizontal line at some constant IE value on the input characteristics. Find

VCB2, VCB1, VEB2, VEB1

VEB2 - VEB1

hrb = -----------------;

VCB2 - VCB1

0.77-0.63/3-0=0.036

Calculation of hfb: Draw a vertical line on the Output characteristics at some constant VCB value. Find

Ic2, Ic1 and IE2, IE1 .

I C2-

IC1

hfb = ----------

I E2 -

IE1

=4.2-3.3/4.1-2.1=0.45

Calculation of hob:

On the Output characteristics for a constant value of IE mark two points with coordinates

(VCB2 , IC2) and (VCB1 , IC1) .

I C2 -

IC1

hob = ------------

V CB2 -

VCB1



=(4.2-3.4)mA/5.02-0.66=183µὨ

RESULTS:

The Input and Output characteristics are drawn on the graphs and the h parameters are calculated

.

hib=44Ω ohms. hrb= 0.036

hob=

183µὨ - mhos. hfb = 0.45



Experiment No:6

TRANSISTOR COMMON EMMITTER CHARACTERISTICS

AIM: 6.a Plot a family of output and input characteristics of a given transistor BC 107 (NPN)

connected in common emitter configuration. For input characteristics set VCE =5V, VCE =10V.

For Output characteristics IB= 20µA, IB= 40µA.

Equipment required:

Bread board-----1No

DC power supplies (0-20V) -----2No’s.

Digital DC Voltmeters (0-20V) –2No’s

Digital DC Ammeters (0-200mA) –2No’s.


Transistor BC 107 B(NPN) -----1No.

Resistors 1kΩand 10kΩ-----1No each.

Circuit diagrams:

Fig:6.1 Transistor CE Input characteristics

(0-20V)

1k

10k

(0-20V)

A +

V +

VCE

NPN

V +

VBE 0-20V 0-20V

0-200mA

IB



Fig:6.2 Transistor CE Output characteristics

Theory:

In Common Emitter configuration, the input signal is applied between base and emitter

and the output is taken from collector and emitter. As emitter is common to input and output

circuits, hence the name common emitter configuration.

Input Characteristics: To determine the input characteristics, the collector to emitter voltage is

kept constant at zero volts and base current is increased from zero in equal steps by increasing

VBE in the circuit. The value of VBE is noted for each setting of IB. this procedure is repeated for

higher fixed values of VCE, and the curves of IB Vs VBE

are drawn. The input characteristics thus

obtained are shown in figure 6.2

Output Characteristics: To determine the output characteristics, the base current IB is kept

constant at a suitable value by adjusting base-emitter voltage, VBE. The magnitude of collector0-

emitter voltage VCE is increased in suitable equal steps from zero and the collector current IC is

noted for each setting of VCE. Now the curves of IC Vs VCE are plotted for different constant

values of IB. The output characteristics thus obtained are shown in figure 6.3.

Procedure:

For plotting input characteristics:

1.To construct the circuit as shown in the Fig6.1.

2.Fix VCE=open=1V,by varying the out put power supply and note that input power

supply should be in minimum during VCE kept constant.

3.Now by varying input power supply ,change VBE in convenient steps and note

down the base current IB for each step.

4.Repeat steps 2 and 3 for different constant values of VCE=3V .

(0- 20V)

1k

10k

( 0-20V)

A +

V +

VCE

NPN

A + Ic

0-20V

0-200mA

Ib

0-200mA



5.Tabulate the readings a in the Table-6.1.

Observations:

VCE =5 VOLTS VCE =10VOLTS

VBE

VOLTS

IB

µA

VBE

VOLTS

IB

µA

0 0 0 0

0.3 1 0.4 3

0.4 2.1 0.45 4.5

0.44 3 0.5 7.2

0.48 2.1 0.53 14.1

0.5 6 0.55 16.4

0.51 8 0.6 24.5

0.53 10

0.54 12

0.62 20.1

0.72 32.5

Table 6.1

For plotting output characteristics:

6. Set IB to 20µA by varying the input power supply and note that output power

supply should be in minimum during IB kept constant.

7.Now by varying the output power supply ,change VCE in convenient steps and

note down the collecter current IC at each voltage step.

8.Repeat steps 6 and 7 for constant values of IB =40µA .

9.Tabulate the readings as in Table-6.2.

Observations:

IB =20µA IB =40µA

VCE

VOLTS

IC

mA

VCE

VOLTS

IC

mA

1.1 0.5 0.1 0

2 1 0.5 0.47

3.2 1.1 0.86 1.1

4 1.4 1.17 1.15

4.5 1.5 1.5 2

5.25 1.6 2.36 3.1

6 1.7 3.1 4

7 2 4 5

9.6 2.3 5.3 6

10 2.4 5.97 7.1

11 2.6 6.74 8

Table 6.2



Model Graph:

1.Plot the family of input characteristics by taking base voltage VBE on X-axis and base

current IB on Y-axis for constant values of output voltage VCE. The model set of input

characteristic curves are shown below in Fig 6.3.

2. Plot the family of output characteristics by taking collector voltage VCE on X-axis and

Collector current IC on Y-axis for constant values of input current IB . The model set of output

characteristic curves are shown below in Fig 6.4.

Result: The characteristics of CE configuration are plotted and the resistances are calculated.



REVIEW QUESTIONS:

1. Draw the input and output Characteristics of CE Configuration

2. What is base width modulation?

3. Define ―ß”?

4. What is the typical value of ―ß”?

5. How do you increase the value of ―ß “

6. Explain the input Characteristics?

7. Explain the output Characteristics?

8. What is the general expression for collector current?

9. What is ICEO?

10. What do you understand by the observations of output Characteristics?



AIM: 6. b. Find h-parameters hie, hre, hoe, and hfe of a given transistor BC 107 (NPN) connected

in common emitter configuration. For input characteristics set VCE =0V, VCE =5V. For Output

characteristics IB= 20µA, IB= 40µA

Equipment required:



Theory:

Procedure:

Observations:


VBE

VOLTS

IB

µA

VBE

VOLTS

IB

µA

0.02 0.23 0 0

0.15 1 0.3 1

0.25 2 0.4 2.1

0.3 3 0.44 3

0.4 6 0.48 2.1

0.42 7 0.5 6

0.44 8.2 0.51 8

0.48 13 0.53 10

0.51 15.6 0.54 12

0.6 20 0.62 20.1

0.7 31.4 0.72 32.5

Table 6.1

Observations:

IB =20µA IB =40µA

VCE

VOLTS

IC

mA

VCE

VOLTS

IC

mA

1.1 0.5 0.1 0

2 1 0.5 0.47

3.2 1.1 0.86 1.1

4 1.4 1.17 1.15

4.5 1.5 1.5 2

5.25 1.6 2.36 3.1

6 1.7 3.1 4

7 2 4 5

9.6 2.3 5.3 6

10 2.4 5.97 7.1

11 2.6 6.74 8

Table 6.2




Calculations:

1. Input Impedance hie = ΔVBE / ΔIB at VCE constant =10.4KΩ

2. Output impedance hoe = ΔVCE / ΔIC at IB constant =5.7KΩ

3. Reverse Transfer Voltage Gain hre = ΔVBE / ΔVCE at IB constant =0.14

4. Forward Transfer Current Gain hfe = ΔIC / ΔIB at constant VCE =315

Result: The characteristics of CEconfiguration are plotted and the resistances are calculated.



AIM: 6.c. . Find input and out put characteristics of a given transistor BC107 (NPN) connected

in common emitter configuration,for VCE =10V, VCE =15V and IB= 20µA, IB= 40µA.

Equipment required:



Theory:

Procedure:

Observations:

VCE =10 VOLTS VCE =15 VOLTS

VBE

VOLTS

IB

µA

VBE

VOLTS

IB

µA

0 0 0 0

0.4 3 0.3 3.2

0.45 4.5 0.41 4.2

0.5 7.2 0.44 6.2

0.53 14.1 0.5 9.2

0.55 16.4 0.54 20.4

0.6 24.5 0.6 32.5

Table 6.1

Observations:

IB =20µA IB =40µA

VCE

VOLTS

IC

mA

VCE

VOLTS

IC

mA

1.1 0.5 0.1 0

2 1 0.5 0.47

3.2 1.1 0.86 1.1

4 1.4 1.17 1.15

4.5 1.5 1.5 2

5.25 1.6 2.36 3.1

6 1.7 3.1 4

7 2 4 5

9.6 2.3 5.3 6

10 2.4 5.97 7.1

11 2.6 6.74 8

Table 6.2




Calculations:

Input Resistance: BEi

B

Vr

I

, VCE constant=0.6-0.53/(24.5-14.1)µA=148 KΩ

Output Resistance: CEo

C

Vr

I

, IB constant=10-6/(2.4-1.7)mA=5.7KΩ

Inference:

Input resistance, ri = 148 KΩ

Output resistance, ro = 5.7K Ω




AIM: 6.d. Plot a family of output and input characteristics of a given transistor BC557 (PNP)

connected in common emitter configuration. For input characteristics set VCE = 0V, VCE=5V.

For Output characteristics IB= 20µA, 40µA .

Equipment required:



Theory:

Procedure:

Observations:

VCE =0 VOLTS VCE =3 VOLTS

VBE

VOLTS

IB

µA

VBE

VOLTS

IB

µA

0.02 0.23 0 0

0.15 1 0.3 1

0.25 2 0.4 2.1

0.3 3 0.44 3

0.4 6 0.48 2.1

0.44 8.2 0.51 8

0.48 13 0.53 10

0.51 15.6 0.54 12

0.6 20 0.62 20.1

0.7 31 0.72 32.5

Table 6.1

Observations:

IB =20µA IB =40µA

VCE

VOLTS

IC

mA

VCE

VOLTS

IC

mA

1.1 0.5 0.1 0

2 1 0.5 0.47

3.2 1.1 0.86 1.1

4 1.4 1.17 1.15

4.5 1.5 1.5 2

5.25 1.6 2.36 3.1

6 1.7 3.1 4

7 2 4 5

9.6 2.3 5.3 6

10 2.4 5.97 7.1

11 2.6 6.74 8

Table 6.2


Result: The characteristics of CE configuration are plotted and the resistances are

calculated.



AIM: 6. e. Find h-parameters hie, hre, hoe, and hfe of a given transistor BC557 (PNP) connected

in common emitter configuration. For input characteristics set VCE = 0V, VCE=5V. For Output

characteristics IB= 20µA, 40 µA

Equipment required:



Theory:

Procedure:

Observations:


VBE

VOLTS

IB

µA

VBE

VOLTS

IB

µA

0.02 0.23 0 0

0.15 1 0.3 1

0.25 2 0.4 2.1

0.3 3 0.44 3

0.4 6 0.48 2.1

0.42 7 0.5 6

0.44 8.2 0.51 8

0.48 13 0.53 10

0.51 15.6 0.54 12

0.6 20 0.62 20.1

0.7 31.4 0.72 32.5

Table 6.1

Observations:

IB =20µA IB =40µA

VCE

VOLTS

IC

mA

VCE

VOLTS

IC

mA

1.1 0.5 0.1 0

2 1 0.5 0.47

3.2 1.1 0.86 1.1

4 1.4 1.17 1.15

4.5 1.5 1.5 2

5.25 1.6 2.36 3.1

6 1.7 3.1 4

7 2 4 5

9.6 2.3 5.3 6

10 2.4 5.97 7.1

11 2.6 6.74 8

Table 6.2




Calculations:

Input Resistance: BEi

B

Vr

I

, VCE constant=0.51-0.42/(15.6-7)µA=10.4KΩ

Output Resistance: CEo

C

Vr

I

, IB constant=10-6/(2.4-1.7)mA=5.7KΩ

Inference:

Input resistance, ri = 10.4K Ω

Output resistance, ro = 5.7K Ω

1. Input Impedance hie = ΔVBE / ΔIB at VCE constant =10.4KΩ

2. Output impedance hoe = ΔVCE / ΔIC at IB constant =5.7KΩ

3. Reverse Transfer Voltage Gain hre = ΔVBE / ΔVCE at IB constant =0.14

4. Forward Transfer Current Gain hfe = ΔIC / ΔIB at constant VCE =315




Experiment No: 7

JUNCTION FIELD EFFECT TRANSISTOR CHARACTERISTICS

AIM:7.a Plot the family of drain characteristics of the given n-Channel JFET with gate

resistance 100Ω and a drain resistance of 560Ω

Equipment required:

Bread board-----1No

DC power supplies (0-20V) -----2No’s

Digital DC Voltmeters -----2No’s.

Digital DC Ammeter ----1No.


Transistor BFW10-----1No

Resistors 100Ω,560 Ω -----1No each

Circuit diagram:

Fig:7.1 JFET

Theory:

A FET is a three terminal device, having the characteristics of high input impedance and

less noise, the Gate to Source junction of the FET s always reverse biased. In response to small

applied voltage from drain to source, the n-type bar acts as sample resistor, and the drain current

increases linearly with VDS. With increase in ID the ohmic voltage drop between the source and

the channel region reverse biases the junction and the conducting position of the channel begins

to remain constant. The VDS at this instant is called ―pinch of voltage‖.

If the gate to source voltage (VGS) is applied in the direction to provide additional reverse

BFW10 100

560

(0- 20V)

VGG

(0-20V)

V +

VGS

V +

VDS

A +

IC

0-20V

0-20mA

0-20V

VDD



bias, the pinch off voltage ill is decreased. In amplifier application, the FET is always used in the

region beyond the pinch-off.

FDS = IDSS(1-VGS/VP)^2

FET Paramters:

i) Transconductance gm: It is the slope of transfer characteristics curve. It is defined by

,

DS

D Dm DS

GS GSV

I Ig V

V V

held constant.

ii) Drain resistance, rd: It is the reciprocal of the slope of the drain characteristics and is defined

by

,

GS

DS DSd GS

D DV

V Vr V

I I

held constant.

iii) Amplification factor, : It is defined as

,

D

DS DSD

GS GSI

V VI

V V

held constant.

The relation among the FET parameters is m dg r .

Procedure:

Drain Characteristics:

1. Connect the circuit on the bread board as shown in fig 7.1.

2. Keep VDD = 0 and vary VGG to make VGS = 0 V.

3. Increase VDD from 0 onwards and note down the readings of ID and VDS.

4. Repeat steps 2 and 3 for VGS = -1 V and VGS = -2 V .

5. Plot the graph between VDS and ID for different values of VGS.

Transfer Characteristics:

1. Connect the circuit on the bread board as shown in fig 7.

2. Keep VGG = 0 and vary VDD to make VDS = 2 V.

3. Increase VGG from 0 onwards and note down the readings of ID and VGS.

4. Repeat steps 2 and 3 for VDS = 4 V.

5. Plot the graph between VGS and ID for different values of VDS.



Observations:


VGS = 0 V VGS = -1 V

VDS (V) ID (mA) VDS (V) ID (mA)

0.23 1.6 0.19 0.9

0.5 3.6 0.63 2.2

0.8 5.1 0.8 3.2

1.45 8.4 1.1 3.8

2.3 10 1.46 5.9

3.6 11.6 2.2 8.6

4.29 11.8 3 10.7

4.79 11.8 3.9 11.4

5 11.8 4.3 11.4

5.8 11.8

6.7

7.1

11.8

7.1 11.7

Table:7.1

To obtain transfer characteristics:

Observations:

VDS = 1 V

VGS (V) ID (mA)

0 -4.4

-0.65 -4.1

-1 -3.9

-1.23 -3.7

-1.52 -3.5

-2.2 -2.7

-2.6 -1.9

9-0.7 -3 -0.7

-3.4 0

Table:7.2



Model Graph:

Drain Characteristics: answer for 7.a

Result: The characteristics of FET are studied.



REVIEW QUESTIONS:

1. Explain the operation of N-Channel JFET?

2 What is the meaning of Drain Characteristics and Transfer Characteristics?

3. What is Pinchoff voltage?

4. Explain the Drain Characteristics?

5. Explain the Transfer Characteristics?

6. What are the advantages of JFET over BJT?

7. Give the Expression for Drain Current?

8. What is the depletion mode and Enhancement mode?

9. Explain the operation of Enhancement mode N-Channel MOSFET?

10. Draw the circuit symbol of JFET and MOSFETS?



AIM: 7.b. . Determine the FET(BFW10) parameters (rd, gm and ).

Equipment required:


Circuit diagram: same as 7.a

Theory:

Procedure:

Observations:




0.23 1.6 0.19 0.9

0.5 3.6 0.63 2.2

0.8 5.1 0.8 3.2

1.45 8.4 1.1 3.8

2.3 10 1.46 5.9

3.6 11.6 2.2 8.6

4.29 11.8 3 10.7

4.79 11.8 3.9 11.4

5 11.8 4.3 11.4

5.8 11.8

6.7

7.1

11.8

7.1 11.7

Table:7.1


Observations:

VDS = 1 V

VGS (V) ID (mA)

0 -4.4

-0.65 -4.1

-1 -3.9

-1.23 -3.7

-1.52 -3.5



-2.2 -2.7

-2.6 -1.9

9-0.7 -3 -0.7

-3.4 0

Table:7.2


Calculations:

Drain resistance, DSd

D

Vr

I

, VGS constant=6.7-2.3/(11.8-10)mA=2.44KΩ

Transconductance, Dm

GS

Ig

V

, VDS constant=[-4.1-(-2.7)]mA/-0.65-(-2.2)=0.903mὨ

Amplification factor, DS

GS

V

V

, ID constant=4.4/1.55=2.838

or m dg r = 0.903mὨ*2.44KΩ=2.203

Result:

Drain resistance (rd) =2.44KΩ

Transconductance (gm) =0.903mὨ

Amplification factor ( ) =2.838



AIM:7.c Plot the family of drain characteristics of the given n-Channel JFET transistor

BFW10 with gate resistance 330Ω and a drain resistance of 470Ω

Equipment required:


Circuit diagram:

Theory:

Procedure:

Observations:




0.22 1.4 0.12 0.4

0.53 3.3 0.3 1.1

0.78 4.7 0.4 1.5

0.94 5.5 0.6 2.2

1.29 7 0.8 2.7

1.55 7.9 0.95 3.1

1.83 8.8 1.25 4.3

2.43 10.1 1.5 4.9

3.13 10.9 1.7 5.6

4.39 11.5 2.2 6.5

5.23 11.5 3 7.2

6.89 11.5 3.9 7.5

7.07 11.3 5.5 7.6

7.1 7.6

Table:7.1


Observations:

VDS = 1 V

VGS (V) ID (mA)

0 6

-0.25 -5.9

-0.49 -5.7



-0.83 -5.4

-1 -5.1

-1.4 -4.7

-1.48 -4.6

-1.8 -3.9

-2 -3

-3.19 -0.9

-3.7 0

Table:7.2


Result: The characteristics and the parameters of FET are studied.



AIM:7. d. Determine the FET parameters for gate resistance 330Ω, drain ressitance 470Ω.

Equipment required:


Circuit diagram: same as 7.a

Theory:

Procedure:

Observations:




0.22 1.4 0.12 0.4

0.53 3.3 0.3 1.1

0.78 4.7 0.4 1.5

0.94 5.5 0.6 2.2

1.29 7 0.8 2.7

1.55 7.9 0.95 3.1

1.83 8.8 1.25 4.3

2.43 10.1 1.5 4.9

3.13 10.9 1.7 5.6

4.39 11.5 2.2 6.5

5.23 11.5 3 7.2

6.89 11.5 3.9 7.5

7.07 11.3 5.5 7.6

7.1 7.6

Table:7.1


Observations:

VDS = 1 V

VGS (V) ID (mA)

0 6

-0.25 -5.9

-0.49 -5.7



-0.83 -5.4

-1 -5.1

-1.4 -4.7

-1.48 -4.6

-1.8 -3.9

-2 -3

-3.19 -0.9

-3.7 0

Table:7.2


Calculations:


D

Vr

I



GS

Ig

V

, VDS constant=[-5.9-(-.39)]mA/(-0.25-(-1.8)=1.29mὨ


GS

V

V

, ID constant

m dg r =1.29*1.24=1.605

Inference:

Drain resistance (rd) =1.244 KΩ

Transconductance (gm) =1.29mὨ

Amplification factor ( ) =1.605




AIM:7.e. Plot the family of drain characteristics of the given n-Channel JFET transistor

BFW10 with gate resistance 100Ω and a drain resistance of 470Ω

Equipment required:


Circuit diagram:

Theory:

Procedure:

Observations:




0.22 1.4 0.12 0.4

0.53 3.3 0.3 1.1

0.78 4.7 0.4 1.5

0.94 5.5 0.6 2.2

1.29 7 0.8 2.7

1.55 7.9 0.95 3.1

1.83 8.8 1.25 4.3

2.43 10.1 1.5 4.9

3.13 10.9 1.7 5.6

4.39 11.5 2.2 6.5

5.23 11.5 3 7.2

6.89 11.5 3.9 7.5

7.07 11.3 5.5 7.6

7.1 7.6

Table:7.1


Observations:

VDS = 1 V

VGS (V) ID (mA)

0 6



-0.25 -5.9

-0.49 -5.7

-0.83 -5.4

-1 -5.1

-1.4 -4.7

-1.48 -4.6

-1.8 -3.9

-2 -3

-3.19 -0.9

-3.7 0

Table:7.2


Calculations:


D

Vr

I



GS

Ig

V

, VDS constant=[-5.9-(-.39)]mA/(-0.25-(-1.8)=1.29mὨ


GS

V

V

, ID constant




T1 !NPN 1k

Vcc 12

V2 5

I B

I E

V BE

I C

R TH

R E

V TH

B

E

C

R C

Experiment No:8

DESIGN OF TRANSISTOR SELF BIAS CIRCUIT

AIM: a.Design a self bias circuit with the following given data CCV =12V, operating point

(VCE =5V, IC= 2mA), RC=2.2kΩ,RE =1.3 kΩ stability factor S=8 , R1=33k,R2=12K.

Equipment required:

Bread board-----1No.


Digital DC Voltmeter (0-20V) -----1No.

Digital DC Ammeter ( 0-200mA)-----1No.


Transistor BC107

Resistors

Circuit diagrams:

Fig 8.3 Fig 8.4

T1 !NPN

V1 5 12V

R C

R E

I 2

I 1

V BE

B

E

C

I C

I B

V CE

R 1

R 2



Procedure:

(1) Apply KVL to the output Loop of fig.

Ie., VCC=IC RC+VCE+ICRE -----------------(1)

On substituting values of VCC, IC ,RC, &VCE in above eq—(1),

Then find RE . which is RE=1.3K Ω

(2) The formula for stability factor S=

(1 )(1 )

(1 )

TH

E

TH

E

R

R

R

R

--------------------(2)

Take the multimeter , put it in feh range , insert the transistor and calculate

feh .

Substitute , RE and given S in eq (2)

Then EI .

(3) Apply KVL to input loop of fig.2

(I I ) RTH B TH BE B C EV I R V E B C

CB

I I I

II

Then (1 ) R

TH BEB

TH E

V VI

R

------------------------------(3)

In eq (3) substitute , , , ,&RB TH BE EI R V

Then THV =3.36V

(4) From the formulas 2

1 2

TH CC

RV V

R R

, 1 2

1 2

TH

R RR

R R

Calculate 1R & 2R after substituting THV , THR & CCV .

Then 1 33R K ; 2 12R K .

(5) Now insert 1R , 2R , R E valued resistors in fig 1

(6) Practically find the value of stability factor S .

Observations:

For self bias circuit:

CEV =4.84 V, 0.64BEV V



Drop across 33 ,K 33 8.78KV V; Drop across 12K, 12 3.17KV V

Drop across 2.2K, 2.2 4.64KV V; Drop across 1.3K, 1.3 2.56KV V

Calculations:

1 1

8.26

1

TH

E

TH

E

R

RS

R

R

, Emitter current EI = 1.3 1.9691.3

KVmA

K

Current 122 0.264

12

KVI mA

K

Current 331 0.266

33

KVI mA

K

:. Base current 1 2 0.002BI I I mA

Collector current 1.966C E BI I I mA

Current gain β= 983.46C

B

I

I

Thevenin’s resistance 1 2

1 2

TH

R RR

R R

=8.8 K

Stability factor

1 1

8.26

1

TH

E

TH

E

R

RS

R

R

Result :

Stability factor for self bias circuit =8.26



Review questions?

1.what is meant by biasing?

2.what are the different types of biasing methods?

3.define stability factor?

4.what is the advantage of self biasing method?



AIM:8.b. Design a self bias circuit with the following given data CCV =10V, operating point

(VCE =3V, IC= 1mA,β=100), RC=2.2kΩ, stability factor S=5 for R1=33k,R2=12K

Equipment required:


Circuit diagrams:

Procedure:

Observations:


CEV = 3 V , VBE=0.6 V

Drop across R1= 7.3 V; Drop across R2= 2.66

V

Drop across RC= 10.67 V; Drop across RE= 6.93 V

Calculations:

S=(1+β)[1+RTH/RE/1+ β+ RTH/RE= 3.7 , Emitter current EI =5.335mA

Current I2 = VR2/R2 = 0.221 mA


Collector current IC = IE- IB=4.85mA

Current gain β= IC/IB =100

Thevenin’s resistance RTH=R1R2/R1+R2 = 8.8 KΩ

Stability factor S=(1+β)[1+RTH/RE/1+ β+ RTH/RE=3.7

Result :

Stability factor for self bias circuit = 3.7



AIM: 8.c.Design a self bias circuit with the following given data CCV =12V, operating point

(VCE =6V, IC= 3mA), RC=1.5kΩ, stability factor S=8

Equipment required:


Circuit diagrams:

Procedure:

Observations:


CEV = 6V , VBE= 0.6 V

Drop across R1=8.5 V; Drop across R2= 3.2

V


Calculations:

S=(1+β)[1+RTH/RE/1+ β+ RTH/RE=8.1 , Emitter current EI =3.5mA

Current I2 = VR2/R2 = 0.266mA


Collector current IC = IE- IB=2.8mA

Thevenin’s resistance RTH=R1R2/R1+R2 = 8.8 K


Result :




AIM:8.d.Design a self bias circuit with the following given data CCV =9V, operating point

(VCE =4V, IC= 1mA), RC=1kΩ, stability factor S=10

Equipment required:


Circuit diagrams:

Procedure:

Observations:


CEV = 4 V , VBE= 0.7 V

Drop across R1=5.4V ; Drop across R2=3.2

V


Calculations:

S=(1+β)[1+RTH/RE/1+ β+ RTH/RE= 9.7 , Emitter current EI =

Current I2 = VR2/R2 = mA

Current I1 = VR1/R1 = mA

:. Base current IB= I1 - I2

Collector current IC = IE- IB




Result :




AIM:8.e.Design a self bias circuit with the following given data CCV =14V, operating point

(VCE =7V, IC= 2mA), RC=2.2kΩ, stability factor S=15

Equipment required:


Circuit diagrams:

Procedure:

Observations:


CEV = 7V , VBE= 0.64V

Drop across R1=8.7 V; Drop across R2= 3.1

V


Calculations:

S=(1+β)[1+RTH/RE/1+ β+ RTH/RE= 13.9 , Emitter current EI =1.9mA



:. Base current IB= I1 - I2 =0.002

Collector current IC = IE- IB=1.9




Result :




Experiment No : 9

COMMON EMMITTER AMPLIFIER

AIM: 9. a. Determine the maximum voltage gain in dB , lower and upper cutoff frequencies

and bandwidth of CE amplifier.

Equipment required:

Bread board-----1No

DC power supply(0-20V) -----1No

Function generator (0-1MHz)-----1No

C.R.O-----1No


Transistor BC 107 B-----1No

Resistors 1kΩ,10kΩ,100kΩ-1No each

2.2kΩ-2No’s

Capacitors 10µf – 2No’s,

100µf-1No

Circuit diagrams:

Fig 9.1 CE Amplifier

!NPN

2.2k 10uF

+ FG

100k

10k 1k 100uF

2.2k

10uF

12V

Ch1 + - Ch2 + -

CRO

40mV, 1KHz



Fig 9.2 Input resistance measurement Fig 9.3 Output resistance measurement

THEORY:

The practical circuit of CE amplifier is shown in the figure. It consists of different circuit

components. The functions of these components are as follows:

1. Biasing Circuit: The resistances R1, R2 and RE form the voltage divider biasing circuit for

the CE amplifier. It sets the proper operating point for the CE amplifier.

2. Input capacitor C1: This capacitor couples the signal to the transistor. It blocks any dc

component present in the signal and passes only ac signal for amplification. Because of this,

biasing conditions are maintained constant.

3. Emitter Bypass Capacitor CE: An emitter bypass capacitor CE is connected in parallel with

the emitter resistance, RE to provide a low reactance path to the amplified ac signal. If it is not

inserted, the amplified ac signal passing through RE will cause a voltage drop across it. This will

reduce the output voltage, reducing the gain of the amplifier.

4. Output Coupling Capacitor C2: The coupling capacitor C2 couples the output of the

amplifier to the load or to the next stage of the amplifier. It blocks dc and passes only ac part of

the amplified signal.

Operation:

The CE amplifier provides high gain &wide frequency response. The emitter lead is

common to both input & output circuits and is grounded. The emitter-base circuit is forward

biased. The collector current is controlled by the base current rather than emitter current. The

input signal is applied to base terminal of the transistor and amplifier output is taken across

collector terminal. A very small change in base current produces a much larger change in

collector current.

When +VE half-cycle is fed to the input circuit, it opposes the forward bias of the circuit

which causes the collector current to decrease, it decreases the voltage more –VE. Thus when

input cycle varies through a -VE half-cycle, increases the forward bias of the circuit, which

causes the collector current to increases thus the output signal is common emitter amplifier is in

out of phase with the input signal.



Procedure:

Frequency response characteristics:

1. Construct the circuit as shown in Fig.9.1

2. Connect the function generator to the input terminals.

3. Connect the output terminals to the C.R.O.

4. Set the Amplitude of input Sine Wave signal, VS = 40mV at 1KHz frequency.

5. Measure the input voltage, VI and output voltage ,VO of the amplifier with the

help of C.R.O. Note the voltages.

6. Calculate Output Voltage,VO

Voltage gain = ---------------------

Input Voltage,VI

7. Find the Voltage across the known resistance connected in series with the signal

source i.e; 2.2K (VS-VI). The Input current II is (VS-VI)/2.2K.The output current IO

equal to VO/2.2K.

8. Input impedance is obtained by taking the ratio between input voltages, VI i.e; the

Voltage across 10K ohm and input Current (the calculation of which is included in

the above step -7).

9. To obtain the output resistance, measure the voltage across the output terminals

Without connecting any load. The voltage is the open circuit voltage. Keep the

Input voltage constant. Connect different valued resistors across the output

terminals until you get half the open circuit voltage. This resistance setting gives

the output resistance.



INPUT WAVEFORM:

OUTPUT WAVEFORM:

Tabular Form: input voltage=40mV

Frequency Out put

voltage(volts)

Gain=V0/Vs Gain in

DB=20log(V0/Vs)

10Hz 0.5 12.5 21.938

30 Hz 0.9 22.5 27.04

100 Hz 0.9 22.5 27.04

1K Hz 1 25 27.95

2 K Hz 1 25 27.95

6 K Hz 1 25 27.95

8 K Hz 1 25 27.95

10 K Hz 1 25 27.95

30 K Hz 1 25 27.95

50 K Hz 1 25 27.95

200 K Hz 1 25 27.95

300 K Hz 1 25 27.95

500 K Hz 0.7 17.5 24.86

600 K Hz 0.6 15 23.52



700 K Hz 0.5 12.5 21.93

900 K Hz 0.3 7.5 17.05

1 M Hz 0.05 1.25 1.93

Calculations: Source voltage(Vs)=40mV

Input voltage(Vi)=1.4*20mV=28mV

Vo=1v

Ii=Vs-Vi/2.2kΩ=5.45µA

Io=V0/2.2KΩ=454 µA

Av=Vo/Vi=35.7

Ai=Io/Ii=83.3

Output Voltage,VO

1. Voltage gain = --------------------- = 35.7

Input Voltage,VI

Output Current,IO

2. Current gain = --------------------- = 83.3

Input Current,II

Result: the frequency response of CE amplifier is plotted

Max. Voltage gain, AV(max.) = 27.95 dB

Lower cut-off frequency, f1 =1KHz

Upper cut-off frequency, f2 =300KHz

Bandwidth (f2-f1) =299K Hz



REVIEW QUESTIONS:

1. What is an amplifier?

2. What are the features of CE amplifier?

3. Does phase reversal exist in CE amplifier?

4. Define lower and upper cut-off frequencies.

5. What do you mean by 3-dB point?

6. Define bandwidth.

7. How transistor acts as an amplifier?

8. What is the significance of operating point?

9. Draw the h-parameter model for a CE amplifier.

10.What is the effect of coupling capacitor on low frequency response?



AIM: 9. b. Determine the input and output resistances of CE amplifier.

Equipment required:



Theory:

Procedure:

INPUT WAVEFORM:

OUTPUT WAVEFORM:


Frequency Out put

voltage(volts)

Gain=V0/Vs Gain in

DB=20log(V0/Vs)

10Hz 0.5 12.5 21.938

30 Hz 0.9 22.5 27.04

100 Hz 0.9 22.5 27.04

1K Hz 1 25 27.95

2 K Hz 1 25 27.95

6 K Hz 1 25 27.95

8 K Hz 1 25 27.95

10 K Hz 1 25 27.95



30 K Hz 1 25 27.95

50 K Hz 1 25 27.95

200 K Hz 1 25 27.95

300 K Hz 1 25 27.95

500 K Hz 0.7 17.5 24.86

600 K Hz 0.6 15 23.52

700 K Hz 0.5 12.5 21.93

900 K Hz 0.3 7.5 17.05

1 M Hz 0.05 1.25 1.93

Calculations:

Source voltage(Vs)=40mV

Input voltage(Vi)=1.4*20mV=28mV

Vo=1v

Ii=Vs-Vi/2.2kΩ=5.45µA

Io=V0/2.2KΩ=454 µA

Ri=Vi/Ii=5.13KΩ

Result:

Input resistance, ri = 5.13KΩ

Output resistance, ro = 21MΩ



AIM: 9.c. Draw the frequency response of CE amplifier.

Equipment required:


Circuit diagrams:

Theory:

Procedure:


Frequency Out put

voltage(volts)

Gain=V0/Vs Gain in

DB=20log(V0/Vs)

10Hz 0.5 12.5 21.938

30 Hz 0.9 22.5 27.04

100 Hz 0.9 22.5 27.04

1K Hz 1 25 27.95

2 K Hz 1 25 27.95

6 K Hz 1 25 27.95

8 K Hz 1 25 27.95

10 K Hz 1 25 27.95

30 K Hz 1 25 27.95

50 K Hz 1 25 27.95

200 K Hz 1 25 27.95

300 K Hz 1 25 27.95

500 K Hz 0.7 17.5 24.86

600 K Hz 0.6 15 23.52

700 K Hz 0.5 12.5 21.93

900 K Hz 0.3 7.5 17.05

1 M Hz 0.05 1.25 1.93

MODEL GRAPH:

Result: the frequency response of CE amplifier is plotted



Experiment No : 10

COMMON COLLECTOR AMPLIFIER (EMITTER FOLLOWER)

AIM: 10.a.To obtain the frequency response characteristics of CC amplifier.

Equipment required:

Bread board-----1No



C.R.O-----1No


Transistor BC 107 B-----1No

Resistors 560Ω, 2.2kΩ ,10kΩ,33kΩ-1No each

Capacitors 10µf – 2No’s,

Circuit diagrams:

Fig: 10.1 Emitter Follower Circuit

!NPN

10

k

56

0

2.2k 10uF

+

FG

12

V

10uF

Ch1+ - Ch2+ -

CRO

33

k

40mV. 1KHz



Fig 10.2 Input resistance measurement Fig 10.3 Output resistance measurement

Theory:

In CC amplifier, the output is taken across the emitter terminal. Since the emitter is the

output terminal, it can be noted that the output voltage from a common collector circuit is same

as its input voltage. CC amplifier is also called emitter follower. The characteristics of the CC

amplifier are: High current gain, voltage gain of approximately unity, power gain of

approximately equal to current gain, larger input impedance and small output impedance.

The CC amplifier is widely used as a buffer stage between a high impedance source and a

low impedance load.

Procedure:

Frequency response characteristics:

1. Construct the circuit as shown in Fig.10.1

2. Connect the function generator to the input terminals.

3. Connect the output terminals to the C.R.O.

4. Set the Amplitude of input Sine Wave signal, VS = 40mV at 1KHz frequency.

5. Measure the input voltage, VI and output voltage ,VO of the amplifier with the

help of C.R.O. Note the voltages.

6. Calculate Output Voltage,VO

Voltage gain = ---------------------

Input Voltage,VI

7. Find the Voltage across the known resistance connected in series with the signal

source i.e; 2.2K (VS-VI). The Input current II is (VS-VI)/2.2K.The output current IO

equal to VO/560Ω.

8. Input impedance is obtained by taking the ratio between input voltages, VI i.e; the

Voltage across 10K ohm and input Current (the calculation of which is included in



the above step -7).

9. To obtain the output resistance, measure the voltage across the output terminals

Without connecting any load. The voltage is the open circuit voltage. Keep the

Input voltage constant. Connect different valued resistors across the output

terminals until you get half the open circuit voltage. This resistance setting gives

the output resistance.

10. Plot AV VS frequency on a semi-log sheet.

OBSERVATIONS: Frequency response: Input Voltage (Vi) =40mV

Frequency

(Hz)

Output Voltage (

V0)

Gain=V0/V1 Gain in DB

Av = 20*log10(Vo/Vi)

20Hz 38 0.95 -0.446

50 Hz 38 0.95 -0.446

200 Hz 38 0.95 -0.446

500 Hz 38 0.95 -0.446

1k Hz 38 0.95 -0.446

2 k Hz 38 0.95 -0.446

5 k Hz 38 0.95 -0.446

50 k Hz 38 0.95 -0.446

200 k Hz 37 0.925 -0.677

700 k Hz 37 0.925 -0.677

1M Hz 37 0.925 -0.677

FREQUENCY RESPONSE:.

Result:

The frequency response of the CC amplifier are obtained.



REVIEW QUESTIONS:

1. What are the features of CC amplifier?

2. Does phase reversal exist in CC amplifier?

3. Why CC amplifier is also called as emitter follower?

4. What are the applications of an emitter follower?

5. Compare the input and output resistances of all the three configurations?



AIM:10.b. . Determine the maximum voltage gain in dB, lower and upper cutoff frequencies and

bandwidth of CC amplifier.

Equipment required:



Theory:

Procedure:

OBSERVATIONS:

FREQUENCY RESPONSE: Input Voltage (Vi) =40mV

Frequency

(Hz)

Output Voltage (

V0)



20Hz 38 0.95 -0.446

50 Hz 38 0.95 -0.446

200 Hz 38 0.95 -0.446

500 Hz 38 0.95 -0.446

1k Hz 38 0.95 -0.446

2 k Hz 38 0.95 -0.446

5 k Hz 38 0.95 -0.446

50 k Hz 38 0.95 -0.446

200 k Hz 37 0.925 -0.677

700 k Hz 37 0.925 -0.677

1M Hz 37 0.925 -0.677

CALCULATIONS.

Output Voltage,VO

1. Voltage gain = --------------------- = 38mV/40mV=0.95

Input Voltage,VI

Output Current,IO

2. Current gain = --------------------- =71µA/2.72µA=26

Input Current,II



Inference:

Max. Voltage gain, AV(max.) = -0.677 dB

Lower cut-off frequency, f1 = 70Hz

Upper cut-off frequency, f2 = 700KHz

Bandwidth (f2-f1) = 699.93KHz

RESULT:

The voltage gain,bandwidth ,lower and upper cut off frequencies, of the CC amplifier are

obtained.



AIM:10.c. To determine the input and output resistances of CC amplifier

Equipment required:


Circuit diagrams:

Theory:

Procedure:

Observations:

Frequency response: Input Voltage (Vi) =40mV

Frequency

(Hz)

Output Voltage (

V0)



20Hz 38 0.95 -0.446

50 Hz 38 0.95 -0.446

200 Hz 38 0.95 -0.446

500 Hz 38 0.95 -0.446

1k Hz 38 0.95 -0.446

2 k Hz 38 0.95 -0.446

5 k Hz 38 0.95 -0.446

50 k Hz 38 0.95 -0.446

200 k Hz 37 0.925 -0.677

700 k Hz 37 0.925 -0.677

1M Hz 37 0.925 -0.677

Model waveforms: Input waveform:

Output waveform:



Calculations.

Input Voltage,VI

1 Input Resistance = --------------------- =40mV/2.72µA=16.2KΩ

Input Current II

2. Output resistance =38mV/71 µA=535Ω

Result:

The input and out put resistances of the CC amplifier are obtained.


100 MLRIT,HYDERABAD-43

Experiment:11

11. COMMON SOURCE (FET) AMPLIFIER AIM: 11.a Draw the frequency response of a CS FET amplifier. Equipment required:

Bread board-----1No



C.R.O-----1No


JFET - BFW10

Resistors - 1 KΩ, 10 KΩ, 10 KΩ, 470 Ω

Capacitors - 1 F, 0.01 F, 47 F/40V THEORY:

A field-effect transistor (FET) is a type of transistor commonly used for weak-signal

amplification (for example, for amplifying wireless (signals). The device can amplify analog or

digital signals. It can also switch DC or function as an oscillator. In the FET, current flows along

a semiconductor path called the channel. At one end of the channel, there is an electrode called

the source. At the other end of the channel, there is an electrode called the drain. The physical

diameter of the channel is fixed, but its effective electrical diameter can be varied by the

application of a voltage to a control electrode called the gate. Field-effect transistors exist in two

major classifications. These are known as the junction FET (JFET) and the metal-oxide-

semiconductor FET (MOSFET). The junction FET has a channel consisting of N-type

semiconductor (N-channel) or P-type semiconductor (P-channel) material; the gate is made of

the opposite semiconductor type. In P-type material, electric charges are carried mainly in the

form of electron deficiencies called holes. In N-type material, the charge carriers are primarily

electrons. In a JFET, the junction is the boundary between the channel and the gate. Normally,

this P-N junction is reverse-biased (a DC voltage is applied to it) so that no current flows

between the channel and the gate. However, under some conditions there is a small current

through the junction during part of the input signal cycle. The FET has some advantages and



some disadvantages relative to the bipolar transistor. Field-effect transistors are preferred for

weak-signal work, for example in wireless, communications and broadcast receivers. They are

also preferred in circuits and systems requiring high impedance. The FET is not, in general, used

for high-power amplification, such as required in large wireless communications broadcast

transmitters.

Circuit diagram:

Procedure:

1. As per the design specifications, connect the circuit as shown.

2. Set the frequency of I/P signal at 5 KHz and increase the amplitude, till O/P gets

distorted. The value of I/P signal is maximum signal handling capacity.

3. Set I/P signal at a constant value, less than the maximum signal handling capacity, vary

frequency in the range 50Hz to 1MHz and find O/P voltage for each and every frequency.

4. Calculate voltage gain at each and every frequency.

5. Plot the frequency versus gain and determine fH and fL. 6. Calculate bandwidth fH - fL.

7. Procedure for measuring input impedance: Set the signal generator frequency at 2KHz

and measure Vs and Vi. Then Ii = Vs - Vi / RS. I/P

impedance = Vi / Ii



8. Procedure for measuring O/P impedance: Open the O/P circuit and measure voltage (V

open) across O/P using CRO. After connecting variable resistor at O/P terminals, vary the

resistance to make the O/P (V open) become to half of its value. Then existing resistance

is its O/P resistance.

OBSERVATIONS: input voltage=100mV

Frequency Out put

voltage(volts)

Gain=V0/V1 Gain in

DB=20log(V0/V1)

10Hz 0.24 2.4 7.6

50 Hz 0.44 4.4 12.86

100 Hz 0.48 4.8 13.62

200 Hz 0.48 4.8 13.62

300 Hz 0.48 4.8 13.62

500 Hz 0.48 4.8 13.62

100kHz 0.48 4.8 13.62

300kHz 0.36 3.6 11.12

500kHz 0.32 3.2 10.10

700kHz 0.2 2 6.02

1M Hz 0.16 1.6 4.08

Frequency plot:

A graph is plotted between f on X – axis and 20*log10 (V0 / VI) on Y-axis on a semi-log

sheet. It will be as shown in figure.

BW = fH – f L

Result: The frequency response curve for a common source FET Amplifier is plotted .



REVIEW QUESTIONS:

1. Why a Field Effect Transistor is called so?

2. How does FET behave for small and large values of VDS?

3. Explain how a FET is used as a voltage variable resistor.

4. What are the applications of FET amplifier?



AIM: 11.b. Determine the maximum voltage gain in dB, lower and upper cutoff frequencies and

bandwidth of CS FET amplifier.

Equipment required:


Theory: same as 11.a

Circuit diagram:

Procedure: observations: input voltage=100mV

Frequency Out put

voltage(volts)

Gain=V0/V1 Gain in

DB=20log(V0/V1)

10Hz 0.24 2.4 7.6

50 Hz 0.44 4.4 12.86

100 Hz 0.48 4.8 13.62

200 Hz 0.48 4.8 13.62

300 Hz 0.48 4.8 13.62

500 Hz 0.48 4.8 13.62

100kHz 0.48 4.8 13.62

300kHz 0.36 3.6 11.12

500kHz 0.32 3.2 10.10

700kHz 0.2 2 6.02

1M Hz 0.16 1.6 4.08

Model waveforms:

Frequency plot:

A graph is plotted between f on X – axis and 20*log10 (V0 / VI) on Y-axis on a semi-log

sheet. It will be as shown in figure.

BW = fH – f L



Calculations:

the maximum gain= V0/Vs=4.8

lower cutoff frequencie f1=10Hz

upper cut off frequencie f2=300kHz

bandwidth =f2-f1=299KHz.


Input voltage(Vi)=1.2*50mV= 60mV

Vo=4.8v

Ii=Vs-Vi/10kΩ=4µA

Io=V0/10KΩ µA=0.48mA

Av=Vo/Vi=80

Ai=Io/Ii=120

Result: The the maximum gain, lower and upper cutoff frequencies and bandwidth for a

common source FET Amplifier obtained.



AIM:11.c Determine the input resistance and output resistances of CS FET amplifier Equipment required:


Theory: same as 11.a

Circuit diagram:

Procedure:

Observations: input voltage=100mV

Frequency Out put

voltage(volts)

Gain=V0/V1 Gain in

DB=20log(V0/V1)

10Hz 0.24 2.4 7.6

50 Hz 0.44 4.4 12.86

100 Hz 0.48 4.8 13.62

200 Hz 0.48 4.8 13.62

300 Hz 0.48 4.8 13.62

500 Hz 0.48 4.8 13.62

100kHz 0.48 4.8 13.62

300kHz 0.36 3.6 11.12

500kHz 0.32 3.2 10.10

700kHz 0.2 2 6.02

1M Hz 0.16 1.6 4.08

Model waveforms:

Calculations:


Input voltage(Vi)=1.2*50mV= 60mV

Vo=4.8v

Ii=Vs-Vi/10kΩ=4µA

Io=V0/10KΩ µA=0.48mA

Av=Vo/Vi=80



Ai=Io/Ii=120

Ri=Vi/Ii=15MΩ

Ro=Vo/Io=10KΩ

Result: the input resistance and out put resistances of FET amplifier are calculated.



Experiment No : 12

UJT CHARACTERISTICS

AIM: 12.a. Plot the V-I characteristics of the given Uni Junction Transistor 2N2646 for

VBB=0V,VBB=5V.

Equipment required:

Bread board-----1No

DC power supplies (0-20V) -----2No’s

Digital DC Voltmeters -----2No’s.

Digital DC Ammeter ----1No.


UJT -2N2646 -----1No

Resistors 1KΩ -----2No’s

Circuit diagram:

Fig:12

Theory:

A Uni-junction Transistor (UJT) is an electronic semiconductor device that has only one

junction. The UJT Uni-junction Transistor (UJT) has three terminals, an emitter (E) and two

bases (B1 and B2). The base is formed by lightly doped n-type bar of silicon. Two ohmic

contacts B1 and B2 are attached at its ends. The emitter is of p-type and it is heavily doped. The

1k

1k

20V

VE

(0-20)V

V +

VE

V +

VBB A +

IE

0-20V

0-20mA 0-20V



resistance between B1 and B2, when the emitter is open-circuit is called inter-base resistance.

The original uni-junction transistor, or UJT, is a simple device that is essentially a bar of N type

semiconductor material into which P type material has been diffused somewhere along its

length. The 2N2646 is the most commonly used version of the UJT.

Circuit symbol

The UJT is biased with a positive voltage between the two bases. This causes a potential drop

along the length of the device. When the emitter voltage is driven approximately one diode

voltage above the voltage at the point where the P diffusion (emitter) is, current will begin to

flow from the emitter into the base region. Because the base region is very lightly doped, the

additional current (actually charges in the base region) causes (conductivity modulation) which

reduces the resistance of the portion of the base between the emitter junction and the B2

terminal.

This reduction in resistance means that the emitter junction is more forward biased, and

so even more current is injected. Overall, the effect is a negative resistance at the emitter

terminal. This is what makes the UJT useful, especially in simple oscillator circuits. When the

emitter voltage reaches Vp, the current starts to increase and the emitter voltage starts to

decrease. This is represented by negative slope of the characteristics which is referred to as the

negative resistance region, beyond the valley point; RB1 reaches minimum value and this

region, VEB proportional to IE.

Procedure:

1. Connect the circuit diagram as shown in the Fig :8.1

2. Set the base voltage VBB to 3V by varying the base power supply.

3. Vary the emitter power supply VBB , set the input emitter voltage VE in convenient

steps and correspondingly note the emitter current IE at each step.

4. epeat steps 2 and 3 for VBB=5V and VBB=10V.

5. Tabulate the readings as in Table-15.



VBB =0 VOLTS VBB =5 VOLTS

VE

VOLTS

IE

( mA)

VE

VOLTS

IE

( mA)

0 0 0 0

1 0 2 0

2.3 0 3.59 0

1.01 1.3 1.06 2.2

1.05 2.5 1.07 2.9

1.07 3.9 1.11 3.1

1.12 5 1.14 3.9

1.14 5.9 1.16 5.3

1.18 7.4 1.22 6.9

1.24 10.1 1.25 8.3

1.29 12 1.29 9.9

1.42 15.8 1.34 12.4

1.53 22.9 1.47 18.9

1.7 28.8 1.66 28.9

Table:12.1

Model Graphs:

Plot a graph between VE vs IE by taking IE on X-axis and VE on Y-axis. The

model graph for UJT Characteristics as shown in Fig 8.2. The typical shape of the graph for

family of characteristics is shown in Fig 8.3. Indicate various regions on the graph.

RESULT: The characteristics of UJT are observed



REVIEW QUESTIONS:

1. Explain the operation of UJT?

2. What is the difference between UJT and JFET?

3. Draw the circuit symbol of UJT?

4. Define intrinsic standoff ratio,η?

5 What is the typical value of ―η”.

6. What is the valley voltage and valley current?

7. Explain why base resistance RB1 is decreases.

8. If VBB =5V, η= 0.65, then how much of emitter voltage in needed to conduct the

Emitter diode.

9. What are the applications of UJT?



AIM: 12.b.To plot the V-I characteristics of the given Uni Junction Transistor (UJT-2N2646) for

VBB=0V,VBB=10V

Equipment required:


Circuit diagram:

Theory:

Procedure:

Observations:

VBB =0 VOLTS

VBB =10 VOLTS

VE

VOLTS

IE

( mA)

VE

VOLTS

IE

( mA)

0 0 0 0

1 0 3 0

2.3 0 7.5 0

1.01 1.3 1.24 6.2

1.05 2.5 1.26 7.2

1.07 3.9 1.28 9.2

1.12 5 1.3 10.1

1.14 5.9 1.32 11.3

1.18 7.4 1.34 12.4

1.24 10.1 1.39 15.7

1.29 12 1.46 19.4

1.42 15.8 1.51 22.4

1.53 22.9 1.6 27.5

1.7 28.8 1.69 28.8

Table:12.1

Model Graphs: same as 12.a

Result: The characteristics of UJT are observed



AIM: 12. c. Plot the V-I characteristics of the given Uni Junction Transistor 2N2646 for

VBB=5V,VBB=10V.

Equipment required:

Circuit diagram:

Same as 12.a

Theory:

Procedure:

Observations:

VBB =5 VOLTS VBB =10 VOLTS

VE

VOLTS

IE

( mA)

VE

VOLTS

IE

( mA)

0 0 0 0

2 0 3 0

3.59 0 7.5 0

1.06 2.2 1.24 6.2

1.07 2.9 1.26 7.2

1.11 3.1 1.28 9.2

1.14 3.9 1.3 10.1

1.16 5.3 1.32 11.3

1.22 6.9 1.34 12.4

1.25 8.3 1.39 15.7

1.29 9.9 1.46 19.4

1.34 12.4 1.51 22.4

1.47 18.9 1.6 27.5

1.66 28.9 1.69 28.8

Table:12.1

Model Graphs: Same as 12.a




AIM: 12. d. Plot the V-I characteristics of the given Uni Junction Transistor 2N2646 for

VBB=0V VBB=5V,VBB=10V.

Equipment required:


Circuit diagram:

Theory: Procedure:

Observations:

VBB =0 VOLTS VBB =5 VOLTS VBB =10 VOLTS

VE

VOLTS

IE

( mA)

VE

VOLTS

IE

( mA)

VE

VOLTS

IE

( mA)

0 0 0 0 0 0

1 0 0 3 3 0

2.3 0 0 7.5 7.5 0

1.01 1.3 2.2 1.24 1.24 6.2

1.05 2.5 2.9 1.26 1.26 7.2

1.07 3.9 3.1 1.28 1.28 9.2

1.12 5 3.9 1.3 1.3 10.1

1.14 5.9 5.3 1.32 1.32 11.3

1.18 7.4 6.9 1.34 1.34 12.4

1.24 10.1 8.3 1.39 1.39 15.7

1.29 12 9.9 1.46 1.46 19.4

1.42 15.8 12.4 1.51 1.51 22.4

1.53 22.9 18.9 1.6 1.6 27.5

1.7 28.8 28.9 1.69 1.69 28.8

Table:12.1

Model Graphs: same as 12.a


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