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Engineers’ Guide to VME, VPX & VXS

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2 Engineers’ Guide to VME, VPX & VXS 2013


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Engineers’ Guide to VME, VPX & VXS 2013

Welcome to the Engineers’ Guide to VME, VPX & VXS 2013

The trends in VME are clear: systems are migrating to high-speed fabric interconnects using PCI Express, Serial RapidIO, and 10 Gigabit Ethernet on platforms such as VPX (VITA 46) and OpenVPX (VITA 65). While copper is still the preferred data plane material, lots of work is going into optical interconnects of spaghetti fiber on the backplane. As well, VME vendors are offering all manner of pre-packaged rugged boxes—the term I coined is “shoeboxes”—which may or may not contain 6U, 3U VME or VPX. In fact, they might contain anything, including one of the several Working Group VITA standards: 73, 74, or 75. The challenge, of course, is dealing with the requisite I/O, heat, and environmentals.

I love VME, and have been associated with the ecosystem for nearly 25 years. That’s why when colleague Michael Munroe from Elma Bustronic offered up “VPX Backplanes Go Optical” I jumped on the chance to include it here. Michael’s an expert on all manner of PHY and signaling on VME and VPX. Curtiss-Wright describes how VPX is “Bringing HPC Technology to Mil-Aero Embedded Deployment”, and since power is what drives every-thing, Dawn VME gives us an overview of “VITA 62 Power Supplies: Filling a Standards Gap for 3U VPX Systems”.

As mentioned, heat is a killer in all of these systems so Mentor Graphics, the recent acquirer of FloTHERM and other CFD-related tools, presents an excellent overview of “Tackling the Challenge of Building...Avionics with CFD”. This one’s a must-read.

Yet hardware’s not the only game in VME and VPX. I ran into MultiCoreWare at an AMD conference and twisted a few arms to get them to talk about programming in OpenCL in their article “Performance-Portable Programming”. And we give an “attaboy” (and “attagirl”) to the VME community for being “Agile” before it was popular, as evidenced by the article “The Softer Side of Agile” penned by ESI International.

Last, but not least: be sure to read our insightful Round table Q&A featuring commen-tary by friends from Aitech and Curtiss-Wright in my article “VME’s Long From Dead; Destined to Co-Exist with VPX and Serial Fabrics”.

Of course, that’s not all—this issue is full of product news, datasheets, events and other resources to keep you up to date with the latest in programmable logic. As always, we’d love to hear your feedback, thoughts and comments. Send them to [email protected].

Thanks for joining us by reading.

Chris A. C i u f o , Editor

[email protected]

PS: Watch for InfiniBand on VPX; it’s a trend I’m following closely in the blog www.eecatalog.com/caciufo.

www.eecatalog.com/vme 3

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C ON T E N T S


By Chris A. Ciufo, Editor ..............................................................................................................................................................................................6

OpenATR - SigPro1 Platform OpenVPX™Based Signal Acquisition System

By ELMA .............................................................................................................................................................................................10

3U VPX Solutions from Extreme Engineering Solutions (X-ES)

By Embedded Engineering Solutions (X-ES) ......................................................................................................................................... 12

VPX Backplanes Go Optical

By Michael Munroe, Technical Specialist, Elma Bustronic ................................................................................................................... 14

VITA 62 Power Supplies: Filling a Standards Gap for 3U VPX Systems

By Brian Roberts, Dawn VME ..............................................................................................................................................................................................18

Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD

By Boris Marovic, Product Marketing Manager, Mentor Graphics ............................................................................................................................. 21

Bringing HPC Technology to Mil-Aero, Embedded Deployment

By Eran Strod, System Architect, Curtiss-Wright Controls Defense Solutions .......................................................................................24

The Softer Side of Agile: Leading Collaborative Teams to Success

By Nancy Y. Nee, PMP, CBAP, CSM Executive Director, Project Management & Business Analysis Programs ESI International ............28

The Protocol Wedge

By Ray Alderman, Executive Director, VITA ..........................................................................................................................................40

Products and Services

Chips and Cores

Test and AnalysisTeledyne LeCroyTeledyne LeCroy’s PCI Express® Protocol Analysis and Test Tools ...................................................................31

Hardware

BackplanesSIE Computing SolutionsVPX Backplanes ...............................................................................32

CPU or Single Board ComputersCES - Creative Electronic Systems SAQorlQ T4240 3U OpenVPX SBC (RIOV-2440) ...................................33

CSP Inc.3220Q OpenVPX Intel Blade ............................................................343300GTX OpenVPX NVIDIA GPGPU Blade .......................................35

Emerson Network PowerMVME8100 Freescale P5020 QorlQ processor VME Board ............36MVME2500 ......................................................................................36

Data AquisitionPENTEKModel 53720 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA - 3U VPX Board .........................................37

EnclosuresSIE Computing Solutions717 Series Air-Over Conduction Cooled ATR Enclosures ................38“Mupac” 760 Small Form Factor Series ..........................................39

COVER CREDIT: A U.S. Air Force C-17 Globe-

master III aircraft sits on a runway on Fort

Polk, La., before picking up soldiers for an

airdrop mission during the Large formation

exercise, Dec. 15, 2010. The large formation

exercise demonstrated the global projection

of U.S. airpower and the mission to perform

aerial refueling training. The soldiers are as-

signed to Task Force 1, Operations Group at

the Joint Readiness Training Center. U.S. Air

Force photo by Master Sgt. Jeremy Lock.


Engineers’ Guide to VME, VPX & VXS

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SPECIAL FEATURE


“Born” in 1981, the parallel VMEbus lives on as strong as ever, thanks

to a robust VITA standards organization, highly active suppliers and

contributors, and the defense industry. VME, VPX, OpenVPX and

all the related standards are ideal for long life-cycle, high-reliability

systems that need finely tuned performance along with size, weight

and power.

The newest specs—including VITA 46 (VPX), VITA 65 (OpenVPX),

and several new proposals for small form factor (SFF) versions—are

all designed with multi-gigabit serial fabrics in mind. So it comes as

a bit of a surprise that the much older 32- and 64-bit parallel bus

VME versions continue to live on stronger than ever. This editor

first became associated with VME in the late 1980s, writing his first

article on VME around 1990. Yet it surprises me not one bit that

VME is as popular today as then, partially because of the customer

base that relishes consistency with carefully managed upgrades.

And upgrades are happening, all the time. Intel processors have

replaced the “traditional” Motorola/Freescale PowerPC CPUs of 10

years ago. Our panelists tell us that lower-power ARM processors

are being designed in over Intel CPUs where power or SFF size is

advantageous. Yet as algorithm-intensive FPGAs replace some single-

board computer CPUs, ultra-fast data pipes like Serial RapidIO, PCI

Express, InfiniBand, and 10 GigE represent the next wave of VME-

based upgrades.

Still, as we learned from our discussions with rugged suppliers Aitech

and Curtiss-Wright, there are real-time, closed-loop applications

that will deploy traditional VME right alongside the most leading-

edge new VME standard.

Read on to see how our panelists responded to this set of industry

insider questions.

EECatalog: What is the state of the VME/VPX industry today?

Doug Patterson is VP, Military & Aerospace Business Sector, for

Aitech Defense Systems, Inc.

Patterson, Aitech: The VPX market is emerging slowly despite all the

press that continues to predict that it’s replacing “obsolete technolo-

gies” like [the predecessors] VMEbus and CompactPCI. Customers

with real-time, hard deadline, tight control-loop applications still

value parallel buses like cPCI or VMEbus, and don’t yet use the new

serial, point-to-point fabric topologies.

Parallel buses including VME and cPCI are by definition, “command-

response”, synchronous data buses with bus message formats

and machine instructions often dedicated to this architecture—

including Read-Modify-Write, an instruction that “locks” the bus so

critical messages arrive in order and are, by definition, synchronized

in process and in time. Some of the newer high speed serial fabrics

represent numerous data pipes that seem like a collection of asyn-

chronous “snakes” all swirling and spitting out data at random.

Serial fabrics are ideal for C4ISR applications where passing massive

quantities of high speed data serially to and from predefined points

around a system vehicle, platform or backplane is needed for post-

processing. If data is generated and passed throughout a subsystem

platform asynchronously, data packets can, and most likely will, get

out of sync causing all sorts of unintended actions.

Mike Slonosky, is product marketing manager for the Power

Architecture single board computers at Curtiss-Wright Controls

Defense Solutions.

Steve Edwards, is chief technology officer for COTS Solutions at

Curtiss-Wright Controls Defense Solutions.

Edwards, Curtiss-Wright: VPX (VITA 46) was started in March

2003 and ratified in 2007. OpenVPX (VITA 65) was started in

January 2009 (outside of VITA) and brought into VITA at the end of

2009. The first revision of VITA 65 was released in 2010 and revision

2 (current rev) was released in 2012. We are currently working on rev

3 which should be approved mid-2013. The major additions to the rev

3 specification are faster speed fabrics such as Gen 3 PCIe, 40 GigE

(40GBase-KR) and QDR/FDR InfiniBand.

By Chris A. Ciufo, Editor

Doug Patterson (L), Mike Slonsky(C), and Steve Edwards(R)

A discussion with Aitech and Curtiss-Wright about heat, processors, fabrics, and VME’s

synergy with VPX and all things “U”.

Established platform parallel bus protocols like VMEbus andCompactPCI still have their place in today's and tomorrow'sharsh environment, real-time/hard-deadline embeddedsub-system applications...especially when these products are upgraded and maintained to keep pace with the newest,fastest processor and memory technologies.

While there are some applications where high speed serialfabrics like VPX are ideal, there are others where VMEbus or CompactPCI still rule the roost.

One company continues to actively invest in maintaining –and not obsolescing – their military and space embeddedcomputing products with a proactive 12-year minimum COTS Lifecycle+™ Program.

And one company continues to also invest in deliveringthe very best of the newest embedded COTS computingplatforms with the new, serial fabric protocols.

And one company actively invests in technology insertion at the board level, creating backplane, pin-compatible products with the latest, next generation memory and processor technologies "on-board".

And that same company still delivers their legacy bus products at full speed and full capability and full mil temprange (-55 to +85°C) with those latest technologies.

The one company to do all that? Aitech. Check our websiteto learn more about our technology roadmaps and how they protect your investments.

Aitech Defense Systems, Inc.19756 Prairie Street Chatsworth, CA 91311 email: [email protected] Toll Free: 888-Aitech8 - (888) 248-3248Fax: (818) 407-1502www.rugged.com


SPECIAL FEATURE

We are also in the process or creating one or more “dot” specifications

to cover the use of alternate connectors (optical, RF, etc). We decided

that these alternate connectors were best defined in a dot(s) spec

rather than adding them to the current VITA 65 spec. New profiles

that use only the VITA 46 (VPX) connector will continue to be added

to VITA 65.

EECatalog: Conventional wisdom says boards are getting hotter.

What are you seeing, and what are the trends in thermal manage-

ment?

Patterson, Aitech: “Conventional wisdom” only applies when one

complies and acquiesces to convention, when in fact, only some

boards are getting hotter. Newer processor technologies—like Fre-

escale’s QorIQ and ARM processors— are challenging convention in

terms of performance and power dissipation. The proof can be seen

in today’s full-featured 3G and 4G Smartphones that provide stellar

performance with milliwatt power dissipations. Reductions in SWaP

remain the goal, the engineering prize and the promise of Nirvana.

Edwards, Curtiss-Wright: Boards are getting hotter … and cooler.

Certainly at the high end we are seeing boards getting hotter. This is

driven primarily by the latest generation Intel processors, GPGPUs

and large FPGAs. But we are also seeing that a number of products

(especially in 3U) are using lower power devices such as lower-end

Power Architecture and ARM processors. These processors have more

performance with less power than the CPUs they are replacing from

5+ years ago.

Slonosky, Curtiss-Wright: For technology insertions or technology

refreshes (and there is a difference), customers are requiring next

generation products to fit into the same or similar thermal footprint.

Hence, to meet these needs COTS vendors are designing next genera-

tion boards that provide similar thermal footprints to those in older

products but with increased performance. Not all next-generation

products are going to be able to “fit” thermally—but many can be.

On the hot end there are a number of innovative approaches that

companies are taking for thermal management. Air Flow Through or

AFT (VITA 48.5) is becoming more popular for higher power prod-

ucts. Curtiss-Wright also has a patent pending approach to cooling

high power Intel processors.

EECatalog: The march towards SFFs has affected even predomi-

nantly “U” based VITA. Why is the market so interested in small

form factors?

Patterson, Aitech: Small, rugged, stand-alone form factors, coupled

with high performance, power-efficient, deeply embedded processors

bring the reality of distributed processing and “computing-at-the-

edge” to today’s mobile computing platforms and vehicles. Bus-based

embedded computing subsystems are ideal and still used to create

large, centralized embedded computers.

Compact “smaller than U” embedded computers acting as remote

interface units or data concentrators can now be distributed at the

end of high speed networks and communication buses to gather,

analyze and—more importantly— can gather and compress sensor

data closer to the sensor, then send that data to the central mission

computer, which in-turn, lowers the overall network bandwidth.

Edwards, Curtiss-Wright: In a word: “SWaP”. SFF boards fit best

in niches where the platform is constrained in Size, Weight and/or

Power. Typically smaller UAVs and some ground systems are the big-

gest areas in defense for SFF. Systems that need more performance

use 3U or 6U since they can be used to build the larger systems

required by more demanding applications.

EECatalog: Talk a bit about inter- and intra-box interconnects.

What’s the state of the art today, and where does the user base want

us to go?

Patterson, Aitech: Currently, inter-box interconnect is tending to

adopt the Ethernet TCP/IP and UDP protocols almost universally.

The advent of multi-Gigahertz, multi-core processors with higher

speed RAM and block-oriented Flash memory allows the system

designer to easily overwhelm the box-to-box communications pro-

tocol stacks with plenty of speed and data throughputs left over for

analysis and compression algorithms.

Intra-box data passing is adopting the asynchronous high speed PCIe

(PCI Express) and SRIO (Serial Rapid I/O) serial fabrics with syn-

chronous, even-driven parallel, data buses (like VME and cPCI) that

are providing the real time, interrupt-based system synchronization.

A parallel bus’ interrupt-driven structure with minimal latencies is

the only architecture that can handle these kinds of control-loop

applications in real-time.

Serial fabrics cannot yet replace parallel buses in these closed-loop

feedback systems: none of these fabrics possess the needed real-time

synchronization capability. This is why many systems integrators

for event-driven apps are choosing a hybrid approach to systems

designs—mixing the power, performance and raw speed of high

speed serial data pipes and parallel buses like VME or cPCI for the

control loops.

Edwards, Curtiss-Wright: Today users are predominantly using

3.125 – 6.25 Gbaud fabrics such as SRIO Gen 1 or 2, 10 GigE or PCIe

Gen 1 or 2 inside a box. Interconnects are generally copper. Connec-

tion between boxes are less standardized. We see customers using

sFPDP, Fibre Channel, 10 GigE and proprietary interfaces. Optical

and copper are both used for box-to-box.

40 GigE data plane and PCIe Gen 3 expansion plane products will

be available in the next year. Optical and RF user I/O modules will

also become more prevalent. The general feeling is that VPX can, with

proper layout/routing, support 10Gbaud signaling. Beyond that, the

general belief is that we need to move to optical interfaces (or pick a

new connector that supports 20-25 Gbaud signaling).

EECatalog: Board consolidation continues unabated, and it’s looking

today like that could wind up being all manner of svelte, purpose-

built boxes that don’t seem to follow any standard at all (let alone

VME or VPX). What’s up with this trend?


SPECIAL FEATURE

Patterson, Aitech: Until the smaller, purpose-built, small form

factor boxes can provide all the raw processing power and per-

formance of a multi-slot, large, super high-performance mission

computer, larger C4ISR, sensor-intensive systems will still use a mix

of open system architecture processor and packaging technologies.

Remember how the COTS/NDI market got its start, first a toe-hold,

then a foot-hold and is now deeply entrenched in today’s embedded

processing subsystems and platforms—it’s the limited volumes

associated with the economies of scale that will always displace the

purpose-built systems until the volume increases to justify the devel-

opment and deployment expenses.

The other factor today is the rampaging costs of component obsoles-

cence and how it’s making subsystems obsolete even before they are

deployed out into the field; but that’s a different subject and story,

altogether...

Slonosky, Curtiss-Wright: That is no different than what they do

today, and will probably not change significantly. Standards such as

OpenVPX provide a means to start development with “standard pro-

file cards” in “standard” backplanes or enclosures that can be bought

off the shelf. For example, a system designer is unlikely to use a 5 slot

backplane in an application that requires or only has the space for 2

slots. Not all applications will be able to use standard off-the-shelf

implementations.

EECatalog: What will the future hold regarding SWaP-C and open

standards?

Patterson, Aitech: As implied and eluded to in number 5 above, cost

will always drive system solutions. When the volumes increase to

that “magic quantity” (which is different for every company), where

the volume does not displace the costs to design and manufacture a

unit internally, the use of COTS products will predominate by eco-

nomics alone as long as there are companies who invest their IP into

producing compatible, inter-mateable, open systems architectures.

Edwards, Curtiss-Wright: Open standards are here to stay, but

“openness” can be defined at many levels and we may start seeing

open standards at a subsystem or interface level and not so much at

the module level.

Chris A. Ciufo is senior editor for embedded content

at Extension Media, which includes the EECatalog

print and digital publications and website, Embed-

ded Intel® Solutions, and other related blogs and

embedded channels. He has 29 years of embedded

technology experience, and has degrees in electri-

cal engineering, and in materials science, emphasizing solid state

physics. He can be reached at [email protected].

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SPECIAL FEATURE

VPX Backplanes Go OpticalVPX backplanes surpass 40 Gbps in copper Ethernet and also gain a backplane optical

interface connector.

Optical backplanes are seen by some as the ultimate solution for

higher bandwidth interconnections, and hence long anticipated in

embedded computing. The practicality of backplane-based optical

solutions is closer to becoming a reality with the release of two ANSI-

VITA standards addressing backplane optical interfaces.

VPX has become the backplane architecture of choice for new

embedded applications in the mil-aero marketplace. Important attri-

butes of VPX include:

a 6U card and even more if the 48 volt option were used

-

tial pairs and a 6U card with 192 differential pairs in addition to all

the standard power and utility signals.

The last point is becoming an increasingly

important aspect of the VPX architecture.

In addition to both conventional rear transi-

tion modules and a very capable rear copper

cable interface there are now a series of

ANSI-VITA standards that define backplane

coaxial cables for RF signals and backplane

optical ribbon cables. The VPX optical back-

plane module accepts a standard optical ribbon assembly terminated

with an MT ferrule. (see Figure 1).

The Need For More SpeedVPX backplanes on the market today regularly support 5 Gbps and

6.2 Gbps channels and several new VPX backplanes are supporting

8, 10 and even 14 Gbps channels. All the VPX specifications such as

VITA 65 and the various VITA 46 dot specifications point to VITA

68 for their electrical channel requirements. This document is still

in draft version and when released will address the three currently

defined backplane bandwidths, 3.125, 5.0 and 6.25 Gbaud. It is also

intended to address 10GBASE-KR and 40GBASE-KR4. This docu-

ment is progressing slowly.

PCIe Gen3 and InfiniBand FDR are not currently planned to be

included because of the additional engineering work it will require

to define card and backplane electrical margins to ensure inter-

mateability. So although it will take some time for the VPX interface

channel specification to address these new higher speeds, these back-

planes already now exist and card vendors have begun offering VPX

cards that utilize PCIe Gen3 and 10GBASE-KR Ethernet signaling.

10GBASE-KR and 40GBASE-KR4 are both

backplane Ethernet standards based upon

bi-directional 10Gbps differential lanes.

These are fully defined within IEEE 802.3-

2008. However, in that document individual

backplane and daughter card losses are not

defined because there is no backplane con-

nector addressed in that document. Each

backplane architecture must undertake apportion losses and define

channel requirements individually for the backplane and daughter

card. This work has just been completed within PICMG for PICMG

3.1r2. This should make it easier for all subsequent standards to

address the same issue for their backplane and daughter card designs.

Although there are VPX backplanes that can support serial com-

munication across the backplane at 8, 10 and 14 Gbps, maintaining

these speeds over copper I/O cables is no longer practical. Copper

cables supporting PCIe Gen3 are only defined to support distances of

two meters or less. For longer distances optical cables must be used.

If I/O is going to be able to keep parity with the backplane, it is going

to have to be optical. Copper cabling can carry 1000 Base-T Gigabit

By Michael Munroe, Technical Specialist, Elma Bustronic

Figure 1: A 12 optical fiber ribbon terminated to an MT ferrule.

"VPX IS POISED TO OFFER A GRACEFUL TRANSITION FROM

COPPER TO OPTICAL."


SPECIAL FEATURE

signals for 1,000 meters. At the InfiniBand FDR 14.1 Gbps data rate,

the practical distance for copper I/O cabling is less than seven meters.

VITA’s VPX Keeps PaceTwo new standards released in 2011, ANSI-VITA 66.0 (Optical

Interconnect on VPX – Base Standard) and ANSI-VITA 66.1 (Optical

Interconnect on VPX – MT Variant) are laying the groundwork for

migration to optical technologies within the embedded computing

industry. These two VITA 66 dot standards are the first in a family of

documents that will define a variety of backplane optical interfaces

compatible with the existing Eurocard form factor used by the VPX

architecture. Because the Eurocard architecture also utilizes Com-

pactPCI, CompactPCI Express, CompactPCI SO as well as PXI and PXI

Express these new optical connector interfaces have the potential to

rapidly migrate to other platforms if they first become established

within the VPX community. In addition, AdvancedTCA utilizes a

connector system with the same mating interface as required for the

previously mentioned embedded architectures. This means the VPX

optical module could potentially be used for Zone 3 implementations

in that architecture as well.

It’s Not All “Just Optics”There are three basic system implementations that are now possible

based upon the VITA 66.1 interconnect: 1) Fiber optic I/O from the

chassis to external points such as sensor arrays, 2) Direct slot-to-

slot fiber optic links providing high bandwidth paths between pairs

of cards within a system, and 3) Switched optical data planes with

multiple payload cards connected to an optical switch slot (Figure 2).

Figure 1 shows an optical cable assembly with 12 fibers terminated at

each end with an MT ferrule. This assembly would plug into the VITA

66.1 backplane module and could connect from slot to slot or be used

to connect the backplane to an external sensor array.

Figure 2 shows a 6U backplane with the VITA 66.1 optical modules

implemented in the J5 position of slots 5, 6 and 7. Although the VITA

66.1 optical module is new, it is based upon the existing well-estab-

lished MT and MPO ferrule technology first introduced as an EIA

standard around 1993. VITA 66.1 defines a VPX compatible module

that positions the MPO multi-fiber ferrule with sufficient precision

to allow it to be used as a backplane interface for conventional VPX

plug in cards. The VITA 66.1 standard provides for up to two MT fer-

rules in a one-inch long module. Each of the two MT ferrules can hold

up to 24 optical fibers.

This means that a 6U VPX module could support up to six VITA 66.1

modules for a total of 288 optical fibers, such as the one shown in

Figure 1. Of course, this represents a theoretical maximum and it is

not expected that any card would implement more than one or two

modules for a total of between 24 and 96 optical fibers. The reason

for the wide range is that although an individual MT ferrule today

can hold more than the two 12-fiber ribbons defined within VITA

66.1 and slots could potentially be populated with up to six modules,

there are no defined topologies at this time for card-to-card optical

connections. Therefore the most likely implementations within VPX

will be to carry signals between systems or between a system and an

external sensor field and this will be unlikely to require more than a

single optical module on any individual VPX card.

Another important aspect of the VITA 66.1 technology is that it only

defines the positioning of MT ferrules. The MT ferrule allows the use

of one or more optical fiber ribbons of that can each be comprised of

up to 12 fibers. These fibers can be either single mode or multi-mode.

The data rate at which these fibers can be driven is independent of

the MT ferrule. However, the optical devices that are available today

to drive MT ribbon assemblies are readily available that drive each

fiber at 10 or 14 Gbps and some are already available that drive each

fiber at 28 Gbps. Any such device coupled to a fiber ribbon that is

terminated with an MT ferrule will be accepted by the new VITA 66.1

optical modules.

Although the VITA 66.1 connector is ideal for 6U VPX backplanes, it

is not a good solution for 3U VPX backplanes because it occupies an

Figure 2: Top: Hybrid VME/VPX backplane with VITA 66.1 optical connectors and VITA 67.2 coaxial copper connectors and standard VITA 46 MultiGig connectors in positions J0-J4. Bottom: Optical ferrules close up.

Figure 3: Proposed alternate optical connector, with a single MT ferrule. This connector will be useful on 3U VPX modules.


SPECIAL FEATURE

entire connector module. This is acceptable for 6U cards as shown in

Figure 2 above. However, pins are precious in 3U. Therefore one con-

nector company is preparing a proposed optical module that provides

a single MT ferrule in half the space of a full 16 wafer VPX module.

Figure 3 shows an example of a single MT ferrule implemented in a

half size connector. This is much the same approach that was taken

by the VITA 67.1 committee for their 4-cavity RF module.

Optical and Copper InfiniBand cross paths in the VPX backplane architectureIn mid November 2012, the InfiniBand Trade Association

made available to the public Release 1.3 of its Architectural

Specification. This release includes the InfiniBand FDR

electrical interface that supports 14 Gbps lanes as well as

the FDR optical interface.

VPX is at an interesting intersection of optical and copper

technologies. At the present time, companies within the

VITA community have introduced backplanes and cards

supporting both copper signaling and optical IO at the

InfiniBand data rate:

VPX slots compliant to VITA 66.1 optical modules. Two backplanes

are currently available to support these higher data rates - one is a

12-slot dual star and the other is a 4-slot mesh (see Figure 2).

InfiniBand FDR, 56 Gbit/s Host Channel Adapter with failover

capabilities via a 56 Gbp/s QSFP transceiver on the front panel or

the VITA 66.1 optical interconnect to the backplane (see Figure 4).

-

Band FDR at 14 Gbps/lane on the data plane and PCIe Gen3 at 8 Gbps/

lane on the expansion plane (see Figure 5).

Currently, ANSI-VITA 65 recognizes data rates up to 6.25 Gbaud in

three different steps shown for year 2012 in Table 1. As mentioned,

there are products on the market already that correspond to the lines

shown for year 2013. A big unknown is whether or not the copper

data rates will continue to rise. Note, however that the optical data

rates will continue to grow. This table represents the author’s opinion

and is not sanctioned by VITA.

Embedded computer pundits have been predicting the demise of

copper interconnects for some time and those of in the industry

have wondered when this would happen and what the future would

look like. VPX is poised to offer a graceful transition from copper to

optical. It is well designed to provide all the power future cards will

require. VPX also has features to support system management and

distributed clocks as well as JTAG, and all of these features will be

required regardless of how the data plane communicates with other

cards and the outside world. Now it is clear that if I/O goes optical,

VPX has the necessary features to support that transition as well.

Going slot to slot can also make use of the VITA 66.1 optical ribbon

module.

Michael Munroe is a Backplane Technical Special-

ist for Elma Bustronic Corporation. In addition

to over 20 years of experience in the packaging

and interconnect industry, Michael is an active

member of the VITA Standards Organization, a

professional member of the IEEE and currently

serves as Secretary-Treasurer of PICMG.

Figure 4: Embedded Server card from CSPI with provisions for VITA 66.1 connectivity. (Courtesy CSPI).

Figure 5: This 6U VPX switch card from Annapolis Microsystems is the first VPX switch capable of switching either 40GBASE-KR4 Ether-net channels or 56Gbps InfiniBand FDR channels. (Courtesy Annapo-lis Micro Systems.)

Table 1: Notional VITA 65 Channel Gbaud rate implementation timeline


SPECIAL FEATURE

In today’s defense electronics environment, systems designers rely

on open standards to help them deal with both compressed develop-

ment schedules and the expectation of frequent technology upgrades.

This is especially true for systems targeting smaller platforms where

time to deployment can be sandwiched into a one year window. The

3U VPX board-level standard has evolved to fill this need.

However, while the embedded systems community has embraced

board-level open standards for processing modules, mezzanine

cards, I/O protocols and backplane connections, power supplies have

continued to be addressed in an ad hoc manner, without the guidance

of an accepted standard. The recently ratified VITA 62 standard was

developed to address this gap.

As an accepted industry standard, VITA 62 promotes competition,

reduces costs and advances technology with ready to deploy COTS

(commercial off the shelf) power supply modules, allowing devel-

opers to rapidly integrate reliable power into VPX system designs.

A comprehensive power supply standardThe VITA 62 power supply standard supports interoperability, con-

figuration flexibility, advanced levels of reliability and sophisticated

systems management. It ensures that power supply electrical and

mechanical standards are compatible with the popular VPX system

platform and assures that any standard-compliant power supply can

be interchanged with any other, will fit mechanically into the same

chassis and will meet the same electrical standards.

In scope, the standard defines a connector configuration, power

generation requirements, and utility, functionality and form factor

requirements for power supply modules mating to a VPX backplane.

At a detailed level, VITA 62 specifies power supply input and output

voltages and currents, pin-outs, slot size, and mechanical configura-

tions for VPX systems, and allocates specific pins for multiple power

supply load sharing capability. The VITA 62 connector is specified

so as to withstand frequent reconnect cycles, while the slot and

mechanical sizes and tolerances are defined to achieve the tight fit

required for efficient conduction cooling.

The VITA 62 3U pin out specifies power and signal connections. There

are also User Defined (UD) pins allotted for application-specific tasks

(marked as OPT(x) in Figure 1),

blades and receptacles and pins

provided for power in and out.

This figure shows the VITA 62

3U compliant connector pinout

(card view). UD (User Defined)

pins are available for optional,

application specific purposes.

Power blade and receptacles are

provided for power supply out-

puts PO1 +12V, PO2 +3.3V and

PO3 +5V. These voltages are also

provided on pins as auxiliary

outputs. VBAT is provided for

memory back-up battery.

VITA 62 also exploits the

effectiveness of interlocking

standards, referencing defini-

tions that already exist and are

widely used. It supports VITA

46.11 IPMB (Intelligent Platform

Management Bus), VITA 48 REDI

(Ruggedized Enhanced Design

Implementation) and provides

guidelines for adherence to

MIL-STD-461F (electromagnetic

interference), MIL-STD-704F

(electrical standards and holdup

time) and MIL-STD-810F (mission critical ruggedization) compliance.

Interlocking With Electrical And Harsh Environment StandardsVITA 62 supports MIL-STD-704F which sets electrical standards

for military aircraft such as AC voltage power factor, harmonics,

distortion spectrum and load balance currents, DC voltage, currents,

ripple, transients, ground configuration and the crucial to mission

critical deployment holdup time, which allocates for power on “melt-

down.” Chassis, electrical and power supply return must be separate

to one point.

VITA 62 Power Supplies: Filling a Standards Gap for 3U VPX SystemsThe recently ratified VITA 62 standard provides clear definitions for power supply

vendors and supports a powerful set of advanced features, making the mission-critical

system designer’s job immensely easier.

By Brian Roberts, Dawn VME

Figure 1: VITA 62 compliant con-nector pin out (card view). Note the voltage options for 12V, 3.3V and 5V (PO1-PO3) along with the User Defined (UD) pins.


SPECIAL FEATURE

Also supported is VITA 48

REDI (Ruggedized Enhanced

Design Implementation). Part

of VITA 48 has a defined pitch

–the interval on a backplane

of each module–of 1.0”. This is

an increase over the 0.8” pitch

of the older VME standard, a

change which permits higher

power levels and taller compo-

nents. In addition, air, liquid,

and conduction cooling parame-

ters are defined within VITA 48

to provide uniform packaging

alignment.

Although all semiconductor

devices are subject to damage by

ionizing radiation, high density

semiconductors are the easiest

to be damaged by ionizing radia-

tion. A NED (Nuclear Event

Detect) input is supported by

VITA 62 to shut down power during such an event.

SENSE pins permit feedback of +12V, +5V and +3.3V to the power

supply. These voltages compensate for IR (current-resistance) drop

at the connection and provide correction to some

of the transients produced by load surges. SHARE

pins facilitate current balancing between power

supplies operated in parallel. The VBAT pin permits

an on board battery to supply power to system non-

volatile memory. This is important to save system

CMOS settings and other low power volatile storage.

The block diagram in Figure 2 shows VITA 62 3U

power supply electrical connections. VS1, VS2 and

VS3 show DC outputs +12V, +3.3V and +5V respec-

tively. Current sharing signals represented by the

SHARE signals are sent between power supplies in a

sharing configuration. SENSE lines feedback signals

to regulate power output voltages VS1, VS2 and VS3

to the remote load. VITA 46.11 Bus is the I2C link to

the Chassis Manager. The NED input indicates the

presence of Nuclear Event. ACL and ACN are AC line

(hot) and neutral.

Intelligent Platform Management Bus supportVITA 46.11 IPMB (Intelligent Platform Manage-

ment Bus) is focused on ensuring reliable systems

operation and is referenced in VITA 62. VITA 46.11 specifies that

an I2C serial bus be used for communication between modules and

the Intelligent Chassis Manager. This link facilitates sophisticated

systems management through onboard processor control and

monitoring. Monitoring on board sensors permits an Error Log to

be created that flags conditions that may have contributed to failure.

Conditions in the field can never fully be anticipated by any test since

an unusual set of circumstances may act together to cause system

failure. The Error Log produced by the Intelligent Chassis Manager

is thus extremely important because it documents conditions in the

field that led to failure. It is important that the cause of failure be

identified for future maintenance and design. The design engineer

must be fully aware of events leading to failure. This is where the

Error Log is important, it keeps a log of critical parameters such as

vibration, humidity, and temperature.

For example, the Error Log may indicate that a particular board

has a problem with temperature caused by cooling fans. The System

Manager can then be programmed to lower the fan speed so that the

temperature of the board is just below its upper specification.

Critical Vita 62 Power Supply CharacteristicsVITA 62 power supplies have unique challenges in modern deploy-

ment systems. Smart VITA 62 power supplies have voltage rail

control which enables them to be individually sequenced, up and

down. This provides critical sequencing to CPU cards, FPGA cards

and other VITA 65 cards, which are sensitive to which voltage comes

up first.

Power sharing between two or more supplies can be advantageous

if total current requirements exceed that which can be delivered by

a single supply. It can also be advantageous if there is at least one

supply more than that required. Referred to as N+1 redundancy, if

one power supply fails the system can still supply the required cur-

rent using the remaining functional supplies. It also means that

power supplies can be hot swapped. In addition, N+1 redundancy

reduces the power dissipated by each supply and reduced power

means a lower onboard temperature.

Figure 2: Typical VITA 62 3U electrical configuration

Figure 3: Examples of 3U VITA 62-compliant power supplies from Dawn VME Products. The PSC-6236 air-cooled design on the left includes a front panel with connections, while the equivalent conduction-cooled LRU on the right clearly shows wedgelocks for cold plate cooling. These compact PSUs can source 400 W over a wide temperature range.


SPECIAL FEATURE

A short summary of the benefits includes:

and maintainability.

Brian Roberts has 22 years of design experience

in Silicon Valley developing electronic products for

commercial and defense applications. Over this

period, he has worked with clients in the areas of

system engineering, power supply design, and other

printed circuit board based solutions. Brian has

been with the team at Dawn VME Products since 2005.

Dawn VME Products 510-657-4444 www.dawnvme.com

Paralleling power supplies requires that the output current of each

power supply’s voltage rail be balanced. This is a task accomplished by

a SHARE reference signal. An analog reference signal for each of the

voltage rails is connected between each of the system power supplies

through the appropriate SHARE pin.

VITA 62 compliant solutionsThe first implementations of VITA 62 compliant solutions are now

appearing on the market. An example is shown in Figure 3, the

Dawn PSC-6236 Universal AC Input VITA 62 3U Power Supply for

air or conduction cooled systems. Designed for mission critical

applications, it delivers up to 400 Watts of output power over a wide

temperature range.

New products like this represent a standardized power supply ready

to deliver in harsh mission critical environments.

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SPECIAL FEATURE

Component thermal issues have to be managed in order

to maintain high reliability in military aircraft and

avionics environments. The ratio and tradeoff of size,

weight, and power (SWaP) is a crucial system design

consideration in modern defense systems. As aircraft

are fitted with an increasing amount of electronics and

with more components, they become heavier—and

more weight can mean less time in the target zone. But

they also become hotter as size density increases. The

thermal behavior can also vary from component vendor

to vendor but also over the component aging process.

This is due to the degradation of the materials used in

the component and the influence of thermal management

over the lifetime of the component.

A good understanding of semiconductor components’

thermal behavior is important because it is crucial to

the optimum thermal design for a low SWaP ratio. Insuf-

ficient understanding of a component can lead not only

to an oversized cooling system but also to a bad choice

of the selected components intended for the lifetime system use.

Thermal Characterization of Semiconductor Components A good way to begin formal component characterization is to create

a “smart” implementation of the static test version of the Joint Elec-

tron Devices Engineering Council (JEDEC) JESD51-1 electrical test

method [1] that allows for continuous measurement during a heating

or cooling transient.

The characterization method uses the temperature sensitivity of

the semiconductor component. This sensitivity has to be measured

before the actual characterization can begin, and it should be done

according to the JESD51-14 standard to record the cooling curve of

the component.

Once the measured temperature sensitivity parameters (TSP) are

obtained, the component can be characterized by powering up the

device (heating it) with PH [Watt] until a steady state is reached.

Once the junction temperature TJ is constant, the heating cur-

rent is switched off to a lower measuring current that creates a low

measuring power PM [Watt]. The measuring current is negligible

compared to the heating current. This sharp power step introduces

the cooling process and is recorded until a steady state is reached.

From the temperature sensitivity of the component and the lower

steady state temperature, ideally realized with a cold plate, the tran-

sient cooling curve is created as shown in Figure 1. The temperature

difference ΔT (Kelvin) is derived by the temperature sensitivity of

the component; and the thermal resistance of the component can be

calculated as shown in the equation: Rth = ΔT/(PH ‒ PM).

From the recorded cooling curve, a structure function can be

derived as shown in Figure 2. This structure function shows thermal

resistance and capacitance of the single component layers from

junction to environment. The vertical sections of the curve show

[K/W] materials such as metallic layers in the component structure;

whereas horizontal lines show higher thermal resistance layers such

as die attach, glue, grease, and other thermal interface materials

(TIM), PCB layers, and so on.

Tackling the Challenge of Building Smaller, Lighter, and More Efficient Component-based Avionics with CFD

By Boris Marovic, Product Marketing Manager,

Mentor Graphics

Figure 1: Cooling curve of a sample component.

Computational Fluid Dynamics software helps defense systems designers doubly:

it aids in optimizing component SWaP, and models device thermal behavior across

time and vendors.


SPECIAL FEATURE

Each step of the structure function can then be described as a resistor

and capacitor in a Cauer ladder as shown in Figure 3. By specifying the

final node “case” of the component in the curve, a compact thermal

model can be derived and used for accurate component representa-

tion in a simulation for the thermal resistance from junction to case.

Lifetime Testing and Failure CharacterizationComponent characterization is important to be able to judge the

quality of components for two reasons. Firstly, manufacturers should

characterize components production by taking samples to determine

if the production process is running without errors. Secondly, system

integrators should also characterize

components used because naturally

component properties can vary from

vendor to vendor and such variation can

affect SWaP tradeoffs.

With the necessity of high reliability

for safety critical components, it’s

important to ensure perfect functioning

of the system over its lifetime. A sys-

tem’s lifetime can be several thousand

hours under constantly changing

environmental conditions such as tem-

perature variations and shocks, pressure

variations, humidity, and so on. These

conditions increase the aging process

and can result in component or material

failures. Material degrades over time

because of these fluctuations and can

result in TIM degradation, die delamina-

tion, package hermeticity failure, and

other undesirable behavior.

When characterizing components, they are usually exposed to harsh

environments that are even worse than the actual environments in

order to accelerate the aging process and identify degradation. This

is called highly accelerated life testing (HALT) and can

shorten the original testing time by several orders of

magnitude.

Thermal characterization is a nondestructive measure-

ment and can reveal failures caused by this process

inside the component. If, for example, the die attach is

degrading and the die delaminating, it will result in an

increased thermal resistance. Such an increase of the

thermal resistance increases the junction temperature of

the component because the heat cannot be dissipated as

it is for a healthy component. As a result, the component

is likely to fail sooner than a healthy component, as long

excessive temperature increases the aging process even

more.

As the component changes and heat builds up, the failure

process has begun. As well, the thermal management

system that was designed for the system is no longer

efficient and powerful enough to cope with basically a “different”

component than the originally designed component. If in addition

the system has to function in a worse-case scenario of a failing cooling

system, the situation becomes even worse.

The Mentor Graphics T3Ster® thermal transient tester uses a mea-

surement methodology for the junction-to-case thermal resistance

of power semiconductor devices that makes it possible to thermally

characterize a component with high accuracy and repeatability. The

result is far richer data that is measured from much earlier in the

junction temperature transient than possible with other techniques.

The T3Ster post-processing software fully supports the JESD51-14

standard for junction-to-case thermal resistance measurement [2],

allowing the temperature versus time curve obtained directly from

the measurement to be re-cast as “structure functions” (described in

JESD51-14 Annex A), and then automatically find the value of the

Figure 2: Structure function of a sample component showing thermal capacitance (vertically) and thermal resistance (horizontally)

Figure 3: Step by step from component to Cauer ladder.


SPECIAL FEATURE

junction-to-case thermal resistance. The automatically generated

dynamic compact thermal model of the component can then be

applied directly in computational fluid dynamics (CFD) simulation

software embedded in an MCAD system.

CFD Saves Time and MoneyEngineers at Tecnobit used CFD software to help them understand

and optimize the different heat transfer paths and mechanisms

between electronic components and the ambient surroundings in

the harsh environmental conditions found in aircraft. Designing

appropriate cooling systems is necessary to ensure reliability of

avionics equipment as power and heat dissipation issues increase.

Weight minimization and space optimization were Tecnobit’s key

design goals, and they avoid using cooling fans wherever possible

to minimize possible causes of failure, so thermal management is a

major challenge from the very first design phase.

In the example shown in Figure 4, engineers at Tecnobit designed

a special chassis enabling the avionics to be housed in a reduced

space (maximum dimension close to 10 cm). The system was totally

sealed, so the task was to maximize heat transfer by conduction,

radiation, and natural convection from the outside surface. The pre-

liminary design was not thermally acceptable, and so they modified

the internal chassis structure to increase heat conduction from the

components to the chassis walls.

They also modified the outer surfaces of the chassis using special

fins, sand blasting treatment, and electrostatic painting to enhance

convection and radiation exchange with the external ambient. By

using CFD, they were able to save time and money because no time

was wasted building unfeasible prototypes, and the CFD simulations

Figure 4: Tecnobit special chassis that allowed avionics to be housed in a very small space, optimized using CFD software dedicated for electronics cooling applications.

enabled them to optimize the thermal design rapidly

and reduce component junction temperatures by 40°C

compared with the initial design.

References1. JEDEC Standard JESD51-1; “Integrated Circuit Thermal Mea-

surement Method – Electrical Test Method (Single Semiconductor

Device)”, http://www.jedec.org/standards-documents/docs/jesd-

51-1, JEDEC, Dec. 1995.

2. JEDEC Standard JESD51-14: “Transient Dual Interface Test

Method for the Measurement of the Thermal Resistance Junction-

To-Case of Semiconductor Devices with Heat Flow through a

Single Path”, http://www.jedec.org/standards-documents/

results/JESD51-14, JEDEC, Nov. 2010.

Boris Marovic is product marketing

manager for aerospace and defense

in the Mentor Graphics Mechanical

Analysis Division. He studied aero-

space engineering at the University of

Stuttgart, majoring in aircraft design

and aerodynamics, and started with Mentor Graphics as an ap-

plication engineer where he was responsible for support, training,

consulting, and software demonstration. In his current role, he is

responsible for future product enhancements and requirements, as

well as customer relations and marketing activities for the aero-

space and defense industries. He is located in Frankfurt, Germany.


SPECIAL FEATURE

Bringing HPC Technology to Mil-Aero, Embedded DeploymentEmbedded HPEC systems are following the commercial HPC trend towards Intel x86

architectures running Linux, but deployed on VITA’s rugged OpenVPX form factor with

RapidIO interconnect fabrics.

The five hundred of the fastest com-

puters in the world, based on the

Linpack benchmark, are featured on a

website called top500.org. Recently,

91% of the commercial high-perfor-

mance computing (HPC) systems on

the list were running Linux, nearly

half (44%) were using Ethernet and

over 80% were using an x86 architec-

ture CPU. These systems are used in

scientific, complex simulation, and

many other computationally inten-

sive applications. It’s a fair bet that

these would be the architectures that

sensor systems like high-end radar,

SIGINT and other sensor integrators

would be using if their applications

requirements were not SWaP- and

cost-constrained.

In contrast to these “big iron” systems,

for many years embedded vendors and

system integrators built large, distributed systems around niche-ori-

ented architectures such as PowerPC, real-time operating systems,

and the not-yet-mainstream RapidIO serial fabric. Sensor modes

developed for one platform could not be used on any other. Software

was platform-specific and was difficult to port and maintain. This

constrained innovation. Different platforms could not talk to each

other so data sharing was difficult, resulting in lost opportunities to

take advantage of actionable information.

But Intel’s investment in AVX changed that. Advanced Vector Exten-

sions (AVX) is an extension to the x86 instruction set architecture

that makes the Single Instruction Multiple Data (SIMD) x86 engine

suitable for floating point-intensive calculations in multimedia,

scientific and financial applications. In short: Intel-based CPUs are

more than suitable for high-speed, floating point intensive calcula-

tions. As well, the OpenFabrics Alliance has created open source

software that, along with development by Curtiss-Wright, allows

interfacing RDMA-based Ethernet layers to the very common

RapidIO-based embedded boards deployed in many SWaP-constrained

sensor platforms.

HPEC is Embedded HPCWith this new-found performance, the large node parallel com-

puting systems that are specifically oriented to sensor computing

are moving away from PowerPC to Intel. This gives the application

developer access to a broad software ecosystem and opens up a whole

new set of possibilities for open architecture development.

The shift to Intel CPUs allows sensor computing architectures to

more easily use Linux. While it’s true that Linux practically runs on

every processor architecture known (and probably some unknown),

the marriage of Intel and Linux provides the most seamless path to

adopting software components developed for HPC. The vast majority

of HPC systems run Linux and Intel, and the majority of open source

projects also focus on this architecture. With Linux/Intel as the basis

of the OpenVPX computing standard, back-end sensor processing

that needs to be able to scale to many nodes can take advantage of

commercial HPC’s software ecosystem (Figure 1).

By Eran Strod, System Architect, Curtiss-Wright Controls

Defense Solutions

Figure 1: RapidIO enables a cross-platform ecosystem composed of various CPU/GPU vendors, soft-ware, and sensors.


SPECIAL FEATURE

The process of adapting HPC technologies to the embedded space has

recently been described as high-performance embedded computing

(HPEC). Several vendors in COTS computing, including Curtiss-

Wright, use the term HPEC to mean embedded HPC. Just as HPC

is synonymous with the historical term “supercomputing,” HPEC

systems are the SWaP-constrained variant of supercomputers. In

the defense computing market, the highest performing OpenVPX

systems, from vendors like Curtiss-Wright, fit 28 Intel CPUs (112

cores) in a 16-slot chassis, interconnected with a 224 GB/sec dual-

star system fabric (Figure 2). But it’s not only about CPUs, buses and

interconnects. HPEC is about being able to run the same software

that is used in HPC.

Fabric Discontinuity – Software ContinuityHPC is dominated by Ethernet and InfiniBand, while HPEC 6U

OpenVPX computing has been and continues to be dominated by

RapidIO. This apparent discon-

tinuity has been one of the major

roadblocks to bringing HPC tech-

nologies to the HPEC world as the

fabric has traditionally had a major

impact on software architecture.

The first thing to consider is why

stick with RapidIO in the face of

other reasonably good options?

The answer is simple: RapidIO

dominates telecommunications

DSP computing which faces many

of the same constraints as mili-

tary DSP. Even better, RapidIO is

backed by a volume commercial

market. IDT, the leading RapidIO

switch vendor, just announced

that they have shipped 2.5 million

RapidIO switches. RapidIO has a

dominant position in the DSP pro-

cessing that is essential to 4G and

3G wireless base stations. RapidIO

has captured virtually 100% of the

3G market in China, the fastest

growing telecom market. To put

it another way, when you talk on

your cell phone, there is something

like a 90% chance that the bits that represent your voice are at some

point transmitted between two DSP processors over a RapidIO link.

There are a number of reasons why RapidIO makes sense in the con-

text of HPEC OpenVPX computing:

saving SWaP and cost.

performance

choice in HPC, it is a point technology in OpenVPX HPEC. Unlike

alternatives such as Ethernet and RapidIO, InfiniBand is not

anticipated (per simulation) to run reliably at 10 GHz over existing

OpenVPX technology. It will require a connector change which is a

fairly involved and slow-moving process for an organization like VITA.

There were two major challenges in getting RapidIO working in the

Intel environment. The first was a classic interconnect problem.

PowerPC processors supported RapidIO natively, but Intel did not,

so a bridge was needed. The IDT Tsi721 provided this critical piece

of technology. The Tsi721 converts from PCIe to RapidIO and vice

versa and provides full line rate bridging at 20 Gbaud. Using the

Tsi721 designers can develop heterogeneous systems that leverage

the peer to peer networking performance of RapidIO while at the

same time using multiprocessor clusters that may only be PCIe

enabled. Using the Tsi721, applications that require large amounts

of data transferred efficiently without processor involvement can be

executed using the full line rate

block DMA+Messaging engines of

the Tsi721.

The second major challenge related

to RapidIO was software. RapidIO

isn’t used in HPC so it doesn’t

run the same software as those

large cluster-based systems in the

top500 that use fabrics like Eth-

ernet and InfiniBand. InfiniBand

vendors encountered these same

market constraints while trying to

grow beyond their niche. It’s hard

to “fight” Ethernet. However, Eth-

ernet wasn’t appropriate for the

highest performance HPC systems

because of the CPU and/or silicon

overhead associated with TCP

offload. The answer came in the form

of new protocols and new software.

Open Fabric AllianceThe OpenFabrics Alliance (OFA)

was formed to promote Remote

Direct Memory Acess (RDMA)

functionality that allows Ethernet

silicon to move packets from the

memory of one compute node to the memory of another with very

little CPU intervention. There are competing protocols to do this, but

wisely, the OFA created a unified software layer called OFED which

is supported by Intel, Chelseo, Mellanox and the other members of

the Ethernet RDMA ecosystem. OFED is used in business, research

and scientific environments that require highly efficient networks,

storage connectivity and parallel computing.

The OpenFabrics Enterprise Distribution (OFED™) is open-source

software for RDMA and kernel bypass applications. One of the

things that traditionally slowed Ethernet down and wasted the CPU

was the need to copy a packet payload numerous times before it was

shipped out the Ethernet interface (Figure 3). RDMA has eliminated

Figure 2: Curtiss-Wright showcasing 224GB/s dual-star fabric with 28 Intel CPUs (112 cores) in a mere 16-slot chassis.


SPECIAL FEATURE

the unnecessary copying so a packet can be transferred from one

application to another across the fabric with minimal CPU impact

(single digit CPU utilization). The term that is used to describe OFED

is software verbs, but for those readers not deeply into software,

verbs can be thought of like an API, a uniform software interface that

provides application portability.

OFED over RapidIOOur company has ported OFED to the IDT Tsi721 bridge which

we believe represents the first time that OFED is running on the

industry de facto standard IDT implementation of RapidIO (ie, not

requiring non-mass market, proprietary FPGA IP controlled by a

single vendor). This makes data movement over the RapidIO fabric

indistinguishable from any other fabric that uses OFED, such as

Ethernet, except that RapidIO operates at about twice the speed of

10GbE. OFED support on a RapidIO system enables it to run a broad

set of open source software components supported by members of

the OFA and the open source community.

One of the most important software components is middleware

called Message Passing Interface (MPI) as supported by the open

source project Open MPI. MPI is a message passing library interface

specification and is a key enabling technology for the HPEC systems.

MPI is developed by the MPI Forum, a large developer community

comprised of both industry and research organizations. It is a

Figure 3: OpenFabrics Enterprise Distribution (OFED) is open source RDMA that efficiently moves data from one application across a fabric to another application, with minimal CPU overhead. Contrast this to the multi-copy process of Ethernet, as shown here.

portable, language independent protocol that is used to share data

among distributed processors. It has become a de facto standard for

communication among high-performance compute clusters and is

used by many of the TOP500 most powerful computers in the world.

MPI includes the following:

guages

SummaryWith OFED support, OpenVPX systems based on the RapidIO data

plane are able to seamlessly leverage the software ecosystem that

has developed for High-Performance Computing as illustrated by

TOP500 systems. This brings a new level of software portability to

the highest performing VPX systems as this new generation takes

advantage of the wide ecosystem around Linux-based x86 computing.

Eran Strod is a System Architect in the Advanced

Multicomputing Group at Curtiss-Wright Con-

trols Defense Solutions. He leads the HPEC

Center of Excellence (HPEC COE) which provides

middleware and tools for high-performance DSP

applications. Prior to joining CWCDS, while at

Mercury Computer Systems, Eran served on the VITA Board of

Directors. Prior to that, at Freescale Semiconductor, Eran led the

group-wide RapidIO fabric initiative. His career in the embedded

and software industries has recently passed the 20 year mark.


SPECIAL FEATURE


SPECIAL FEATURE

The Softer Side of Agile: Leading Collaborative Teams to Success

Editor’s note: The VME set of specifications is the result of 30 years’ col-

laboration between competitors and customers; it is the successful progeny

of a team-based standards process through the VITA organization. Though

a relatively recent term, “Agile development” was being practiced by all

those VME and VPX collaborators years ago. Today VITA remains more

relevant than ever—with oft-attempted emulation by other standards

bodies. We thought this article on Agile might give credence to some of

VITA’s successful processes. Hats off and take a bow.

— Chris A. Ciufo, Editor

The Agile Manifesto places customer collaboration over contract

negotiation with a keen focus on a highly skilled, motivated team

in constant interaction with the product and the customer at every

phase of the project. As a result of this collaborative, customer-

centric view, Agile requires more than the technical expertise needed

to gather requirements, and develop and test new product lines. It

requires soft skills, leadership competencies and an understanding

of how to apply those skills in a more malleable, people-focused set-

ting. As practitioners know, collaboration brings a set of challenges.

With the Agile approach, project managers are called upon to team

up with customers in a constant stakeholder dialogue.

Constant customer collaboration provides great opportunities to

measure project success by gauging the level of customer satisfaction

throughout each life cycle of the project. It creates the framework

for faster time-to-market and a more nimble process to deliver suc-

cessful project outcomes. When it comes to successful agile project

delivery, collaboration also is key for the integrated project team.

What Makes Good, Effective Collaboration? To begin to understand, we should first take a look at the 12 prin-

ciples behind the Agile Manifesto. These principles, which are the

building blocks of Agile, identify three areas that lend themselves to

successful collaboration. These principles are as follows:

throughout the project.

the environment and support they need, and trust them to get the

job done.

and within a development team is face-to-face conversation.

Based on the above three principles, successful collaboration among

the team relies heavily on three key factors:

Feedback How does feedback work in a team environment? What is the most

successful way to deliver it on an Agile project? Remember that feed-

back during the iterative development work of an Agile project must

increase awareness and insight as well as foster innovation, yielding

positive alternatives. Having the business as part of the core Agile

project team creates the environment for continuous feedback and an

opportunity to take positive risks in doing things differently, which

is the very nature of why the project is being done in an Agile setting.

Within the iteration work, it is essential to provide feedback that:

For all members of the Agile project team, it is important to identify

what to start, stop and continue doing when it comes to iteration

work. This is where effective feedback is most often used. You can

easily integrate these practices into your daily stand up meetings to

prepare for the day’s work.

CommunicationWhat makes effective communication? When it comes to commu-

nication, it is important to deliver information in a manner that is

understood by the receiver, which means that we need to get past

the receiver’s filters and ensure that the individual understood the

By Nancy Y. Nee, PMP, CBAP, CSM Executive Director, Project

Management & Business Analysis Programs ESI International


SPECIAL FEATURE

intended message. To get past those filters, we, as the sender of

this message, have a responsibility to understand how our receiver

takes in information. Does he communicate in a direct manner? Is

she considerate in her messaging? Understanding your receiver’s

communication style will help you provide feedback that enables

effective dialogue.

Motivation When you combine productive feedback with effective communica-

tion, the foundation for motivation has been established. Motivation

is built on encouragement, partnership and compromise without

making concessions that damage trust. Working together to ensure

that barriers, impediments and unrealistic expectations do not derail

the creative impulses of the team brings about team unity. When the

Agile PM delegates to team members the authority and responsibility

to complete features to which they’ve committed, the Agile PM has

created an environment of trust, partnership and self-directedness.

By creating this environment, the team can discover their patterns

of working.

The soft side of Agile is just as important as the technical side of

Agile. Both sets of skills are required and dependent upon each other

for success in the Agile environment. Given what you just read, ask

yourself, how soft is your Agile team?

Nancy Nee, PMP, CBAP, CSM, Executive Direc-

tor, Project Management & Business Analysis

Programs, ESI International, guides clients in

the development and implementation of learning

programs customized to their specific needs. Her

solutions reflect the insight of almost two decades

of PM and BA experience in healthcare, information technology,

financial services and energy. www.esi-intl.com

© 2012 Reprinted with permission from ESI International.

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Test and AnalysisTe

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◆ Config space can be displayed in its entirety so that driver registers can be verified.

TECHNICAL SPECS

◆ Analyzer Lanes supported: X1,x2,x4,x8,x16 Speeds: 2.5GT/s, 5GT/s and 8GTs Probes/Interposers: active and passive PCIe slot, XMC, AMC, VPX, Express card, Express Module,

Minicard, Mid-Bus, Multi-lead, External PCIe cable, CompactPCI Serial and othersForm factor: Card, Chassis

◆ Exerciser Lanes supported: X1,x2,x4,x8,x16 Speeds: 2.5GT/s, 5GT/s, 8GT/s Emulation: root complex and endpoint emulation◆ Protocol Test Card Speeds: 2.5GT/s and 5GT/s operation Tests: Add-in-card test BIOS Platform Test Single Root IO Virtualization Test

APPLICATION AREAS

Mezzanine Boards, Add-in Cards, Host Carrier Systems, System Boards, Chips

Teledyne LeCroy’s PCI Express® Protocol Analysis and Test Tools

Compatible Operating Systems: Windows XP/7/8

Specification Compliance: PCI Express Standards: 1.1, 2.0, and 3.0

Whether you are a test engineer or firmware developer, Teledyne LeCroy’s Protocol Analyzers will help you mea-sure perfor mance and quickly identify, troubleshoot and solve your protocol problems.

Teledyne LeCroy’s products include a wide range of probe connec tions to support XMC, AMC, VPX, ATCA, microTCA, Express Card, MiniCard, Express Module, CompactPCI Serial, MidBus connectors and flexible mult-lead probes for PCIeR 1.0a, 1.1 (“Gen1” at 2.5GT/s), PCIe 2.0 (“Gen2” at 5 GT/s) and PCIe 3.0 (“Gen3” at 8 GT/s).

The high performance Summit™ Protocol Ana lyzers fea-ture the new PCIe virtualization extensions for SR-IOV and MR-IOV and in-band logic analysis. Decoding and test for SSD drive/devices that use NVM Express, SCSI Express and SATA Express are also supported.

Teledyne LeCroy offers a complete range of protocol test solutions, including analyzers, exercisers, protocol test cards, and physical layer testing tools that are certified by the PCI-SIG for ensuring compliance and compatibility with PCI Express specifications, including PCIe 2.0.

FEATURES & BENEFITS

◆ One button protocol error check. Lists all protocol errors found in a trace. Great starting point for beginning a debug session.

◆ Flow control screen that quickly shows credit balances for root complex and endpoint performance bottlenecks. Easily find out why your add-in card is underperforming on its benchmarks.

◆ LTSSM state view screen that accurately shows power state transitions with hyperlinks to drill down to more detail. Helps identify issues when endpoints go into and out of low power states.

◆ Full power management state tracking with Teledyne LeCroy’s Interposer technology. Prevents loosing the trace when the system goes into electrical idle.

◆ Teledyne LeCroy’s Data View shows only the necessary protocol handshaking ack/naks so you don’t have to be a protocol expert to understand if root complexes and endpoints are communicating properly.

◆ Real Time Statistics puts the analyzer into a monitoring mode showing rates for any user term chosen. Good for showing performance and bus utilization of the DUT.

◆ Zero Time Search provides a fast way to search large traces for specific protocol terms.

Teledyne LeCroy3385 Scott Blvd.Santa Clara, CA, 95054USA1 800 909-7211 Toll Free1 408 727-6622 Faxpsgsales @teledynelecroy.comwww.teledynelecroy.com

Teledyne LeCroy


CONTACT INFORMATION

sie-cs.com

SIE Computing Solutions | 10 Mupac Drive | Brockton, MA 02301 | 508-588-6110

Enclosures

Backplanes

System Integration & Custom Solutions

cPCI

VME

Open VPX

xTCA

rugged & ready when you are

CONTACT INFORMATION

SIE Computing Solutions

SIE Computing Solutions10 Mupac DriveBrockton, MA 02301USA800.926.8722 Toll Free508.588.6110 Telephone508.588.0498 Faxwww.sie-cs.com

AVAILABILITY

Now

APPLICATION AREAS

Military/Aerospace, Industrial, Transportation

VPX Backplanes

VITA 46/48/65 Backplanes

SIE Computing Solutions VPX backplanes are designed to the latest VITA 46, 48, 65 and OPEN VPX standards. The 5-slot I/O PLUS(TM) 3U VPX Full Mesh Backplane is designed for a wide array of VPX applications. The highly configurable backplane offers high-bandwidth in a com-pact size and provides greater I/O flexibility through I/O PLUS(TM), an innovative use of configurable I/O daughter cards to accommodate an array of VPX applications.

FEATURES & BENEFITS

◆ 5 slot full mesh◆ 2 dedicated I/O daughter card slots◆ Over 200 watts per slot◆ 28 layer board◆ Supports Gen2 PCIe

TECHNICAL SPECS

◆ J1: 10 fat pipes/high-speed differential channels◆ J2: 16 fat pipes/high-speed differential channels◆ J2: 20 single-ended signals

BackplanesB

ackp

lane

s

CONTACT INFORMATION

TECHNICAL SPECS

◆ OpenVPX Profiles: Slot profile: SLT3-PAY-1F2F2U-14.2.2, Payload module profile: MOD3-PAY-1F2F2U-16.2.2-n

◆ Processor: Freescale QorIQ™ T4240 (twelve dual-threaded cores) at 1.6 GHz, 2 MBytes internal L2 cache (per cluster) with ECC protection, triple 512 KBytes internal L3 cache with ECC protection

◆ Memory: triple 2/4 GBytes DDR3 SDRAM at 12 GBytes/s peak (per channel) with ECC protection, 2 GBytes Flash EPROM (NAND), 128 MBytes Flash EPROM (NOR), 256 KBytes NVRAM

◆ Interconnect: four PCIe x4 on VPX-P1/P2, two SRIO x4 on VPX-P1, twelve GbE on VPX-P1/P2 + one on front, three 10GbE on VPX-P1/P2, one SATA II on VPX-P2 + one on front, one USB 2.0 on front, one UART on VPX-P2 + one on front, one Aurora on VPX-P2

◆ Advanced Board Management Controller: for VITA 46.11 support, configuration management, event log-ging and other supporting tasks

QorIQ T4240 3U OpenVPX SBC (RIOV-2440)Compatible Operating Systems: Integrity, VxWorks, VxWorks 653, Linux

Compatible Architectures: OpenVPX, PCIe, SRIO, GbE, 10GbE, SATA II

The RIOV-2440 features the QorIQ™ T4240, the first Advanced Multiprocessing SoC from Freescale, with 12 dual-threaded cores. The 24 virtual cores of the T4240, along with the associated Altivec™ technology SIMD engines and hardware accelerators, provide excellent performance for calculation-intensive applications. The integrated I/O peripherals and the data-path acceleration architecture (DPAA) guarantee the highest performance for I/O-intensive applications. The CoreNet™ fabric provides very efficient point-to-point interconnection between the multiple cores and peripherals, making the T4240 the ideal choice for applications requiring very high performance, both in I/O and calculation. The hard-ware-assisted virtualization support enables the safe and flexible partitioning of applications on the multiple cores. The RIOV-2440 supports the T4240 processor with up to 12 GB of high-speed DDR3 memory in three separate banks, 2 GB of onboard Flash, and direct I/O connections to the backplane. The overhead of additional switches and bridges is eliminated, while flexibility is provided by the multiple processor I/O configuration options, including PCIe, SRIO, GbE, 10GbE and SATA II. It is com-patible with most OpenVPX™ payload slot profiles. As the first SBC with the T4240 processor, the RIOV-2440 is intended for air-cooled applications and laboratory models. It provides easy access to the essential I/Os on the front panel, as well as complete connectivity on the backplane. Various RTM modules are available to access the wide range of I/O and debug signals.

FEATURES & BENEFITS

◆ Very high computing power in a single 3U VPX slot, ideal for SWaP-sensitive HPEC applications

◆ Based on T4240, the latest Freescale QorIQ SoC, 24 virtual PPC cores with AMP and Altivec technology

◆ Easy access to front-panel I/O and modular RTM options for full connectivity, including 10GbE, SRIO and PCIe

◆ Rugged air-cooled variant available, conduction-cooled version on request

◆ Support for the latest VSIPL++ libraries as well as legacy Altivec software

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CES - Creative Electronic Systems SA

CES - Creative Electronic Systems SA 38 avenue Eugene LanceGrand-Lancy 1212 Switzerland+41.22.884.51.00 Telephone+41.22.794.74.30 0 [email protected]://www.ces.ch


CONTACT INFORMATION

TECHNICAL SPECS

◆ Dual Socket Intel® Xeon® Processors - 4 Cores/8 Threads per socket - 8 MB On-chip L3 Cache per socket - 2.13 GHz Core Clock - 4.8 GT/s QPI between sockets - 16 GB DDR3 ECC protected device-down Memory

◆ Support for FDR 56 Gb/s InfiniBand, 10/40GbE via a companion Carrier Card

◆ 32 Lanes of PCIe Gen2 to the OpenVPX Data and Expansion Planes; Two 1000Base-T Interfaces to the VITA-46.6 Ethernet Control Plane

◆ Full IPMC Implementation ◆ Available in Air-Cooled or Conduction-Cooled versions

APPLICATION AREAS

Embedded Military Computing: Radar, sonar, digital signal processing, command and control, intelligence,surveillance and reconnaissance (ISR)

AVAILABILITY

Now

3220Q OpenVPX Intel BladeCompatible Operating Systems: Red Hat Enterprise Linux, Red Hat Enterprise MRG

Compatible Architectures: OpenVPX, VPX

The 3220Q is a rugged high-performance 6U OpenVPX Blade, with a dual socket Intel® Xeon® processor and QuickPath Interconnect (QPI) to deliver superior perfor-mance-per-watt and low latency. Operating as a general purpose compute engine, it is one of the fundamental building blocks in the CSPI TeraXP™ family of Embedded Servers.

The 3220Q supports Red Hat Enterprise MRG delivering realtime capabilities and high speed messaging in a commercial off the shelf (COTS) Linux based operating system.

Featuring an Open Software Stack (OpenMPI/OFED, AMQP) and a Converged Fabric (supporting FDR Infini-Band, 10/40GbE, Fibre Channel) the TeraXP™ Embedded Servers provide the scalable processing power and I/O bandwidth needed for embedded military computing applications such as radar, sonar, digital signal pro-cessing, command and control, intelligence, surveillance and reconnaissance (ISR).

FEATURES & BENEFITS

◆ Intel® Multi-core general purpose processors for compute density

◆ Converged Fabric technology for high bandwidth InfiniBand, Ethernet and Fibre Channel connectivity

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CSP Inc.

CSP Inc.43 Manning RoadBillerica, MA 01821, USA978-663-7598 Telephone978-663-0150 [email protected]

CONTACT INFORMATION

APPLICATION AREAS

Embedded Military Computing: Radar, sonar, digital signal processing, command and control, intelligence, surveillance, and reconnaissance (ISR)

AVAILABILITY

Now

3300GTX OpenVPX NVIDIA GPGPU BladeCompatible Operating Systems: Red Hat Enterprise Linux, Red Hat Enterprise MRG

Compatible Architectures: OpenVPX, VPX

The 3300GTX provides CSPI’s TeraXP™ Embedded Servers with a high performance co-processor blade fea-turing many CUDA cores to accelerate parallel streaming and FFT based applications. Optimizing computational density in a 6U OpenVPX slot, the 3300GTX is configured with one NVIDIA MXM Graphics Processing Unit (GPU) and one FDR InfiniBand 56 Gbit/s Host Channel Adapter (HCA).

Application development for the GPGPU’s is enhanced by the use of the industry standard CUDA, OpenCL and OpenACC toolkits.

The 3300GTX board also features failover capabilities via the HCA supporting a 56 Gbp/s QSFP transceiver on the front panel and a VITA 66.1 optical interconnect on the backplane. The addition of this fiber-optic connectivity brings benefits in higher bandwidth and lower weight.

FEATURES & BENEFITS

◆ NVIDIA GPGPU coprocessor with GPUDirect Technology

◆ FDR InfiniBand technology with 56 Gbit/s Host Channel Adapter

◆ VPX Backplane with the VITA 66.1 Optical Interconnect

TECHNICAL SPECS

◆ 6U OpenVPX GPGPU Co-processor Blade with one MXM site supporting a NVIDIA GTX 560M GPGPU

◆ Implemented with the Mobile PCI Express Module (MXM) version 3.0 standard, capable of hosting newer GPGPU’s as they become available

◆ mDP Interface (one link to Front Panel, one link to backplane)

◆ Mellanox HCA with ConnectX-3 Virtual Protocol Interconnect (VPI)

◆ Available in Air-Cooled or Conduction-Cooled versions

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CSP Inc.

CSP Inc.43 Manning RoadBillerica, MA 01821, USA978-663-7598 Telephone978-663-0150 [email protected]


CONTACT INFORMATION

Emerson Network Power

TECHNICAL SPECS

◆ Freescale QorIQ P5020 1.8/2.0GHz ◆ 2 PMC/XMC sites◆ Optional hard drive mounting kit ◆ 2x4 PCIe or 2x4 SRIO connectivity to VXS backplane

P0◆ Up to 3 USB 2.0 ports, 5 Ethernet ports, 5 Serial

ports, GPIO

MVME8100 Freescale P5020 QorIQ processor VME Board Compatible Operating Systems: Linux, Wind River VxWorks, Green Hills Integrity

Compatible Architectures: Power

The MVME8100 is a high performance 6U VME/VXS SBC featuring the new Freescale P5020 QorIQ processor supporting high speed ECC DDR3-1333MHz. It offers expanded IO and memory features with PCIe and SRIO fabric connectivity and multiple USB, Serial and Ethernet ports. Memory includes up to 8GB DDR3, 512K FRAM non-volatile memory, and 8GB eMMC NAND Flash. The MVME8100 is offered in commercial and rugged variants for extreme environments with extended shock, vibration, temperatures and conduction cooling. It is designed for a range of high end industrial control such as SPE and photo lithography and C4ISR, including radar/sonar. It will provide technology insertion to prolong current programs while providing more performance and throughput.

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CONTACT INFORMATION

Emerson Network Power2900 South Diablo Way, Suite 190 Tempe, AZ 85282-3222USA+1 800 759 1107 Toll Free+1 602 438 5720 Telephone [email protected] Emerson.com/EmbeddedComputing

TECHNICAL SPECS

◆ 800 MHz or 1.2G Hz Freescale QorIQ P2010 or P2020 processor

◆ Up to 8GB soldered memory ◆ Optional rear transition module

MVME2500 Compatible Operating Systems: Linux, Wind River VxWorks

Compatible Architectures: Power Architecture

Emerson Network Power’s MVME2500 series features the Freescale QorIQ™ single-core P2010 or dual-core P2020 processor. It is a cost effective migration path for older generation MVME3100, MVME4100, MVME5100 and MVME5110 boards. The MVME2500 series is ideal for automation, medical, and military applications such as railway control, semiconductor processing, test and measurement, image processing, and radar/sonar. Memory includes up to 2GB DDR3 and 512KB non-volatile MRAM. The MVME2502 variant has 8GB soldered eMMC solid state memory for additional rugged, non-volatile storage. Connectivity includes Gigabit Ethernet, USB2, serial, SATA and either one or two PMC/XMC sites. A hard drive mounting kit and conformal coating are available.

Emerson Network Power

Emerson Network Power2900 South Diablo Way, Suite 190 Tempe, AZ 85282-3222USA+1 800 759 1107 Toll Free+1 602 438 5720 Telephone [email protected] Emerson.com/EmbeddedComputing

CONTACT INFORMATION

TECHNICAL SPECS

◆ Two 800 MHz 16-bit D/As

◆ 4 GB of DDR3 SDRAM

◆ Sample clock synchronization to an external system reference

◆ LVPECL clock/sync bus for multiboard synchronization ◆ Optional user-configurable gigabit serial interface

APPLICATION AREAS

Software radio, radar, communications, UAV, signals intelligence

AVAILABILITY

Contact Pentek for price and availability

Model 53720 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA - 3U VPX BoardCompatible Operating Systems: Linux, Windows, and VxWorks operating systems

Compatible Architectures: COTS and rugged, 3U VPX,

3U/6U cPCI, PCIe and XMC

Model 53720 is a member of the Onyx family of high performance 3U VPX boards based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a commu-nications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 53720 includes three A/Ds, one upconverter, two D/As and four banks of memory. It features built-in support for PCI Express over the 3U VPX backplane.

FPGA FunctionsThe 53720 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules for simplifying data capture and data transfer. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 53720 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design For applications that require specialized functions, users can install their own custom IP for data processing using Pentek GateFlow FPGA Design Kits.

GateXpress for FPGA Configuration The Onyx architecture includes GateXpress, a sophisti-cated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress imme-diately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window.

FEATURES & BENEFITS

◆ Supports GateXpress FPGA-PCIe Configuration Manager

◆ Complete radar and software radio interface solution

◆ Supports Xilinx Virtex-7 VXT FPGAs ◆ Three 200 MHz 16-bit A/Ds

Data A

quisition Dat

a A

quis

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PENTEK

PENTEKUPPER SADDLE RIVER, NJ07458, USA 201-818-5900 Telephone201-818-5904 [email protected]://www.pentek.com


CONTACT INFORMATION


SIE Computing Solutions10 Mupac DriveBrockton, MA 02301USA800-926-8722 Toll Free508-588-6110 Telephone508-588-0498 [email protected]

TECHNICAL SPECS

◆ Storage Temp (-40°C to +85°C MIL-STD-810F)◆ EMC (MIL-STD-461D)◆ Input Power (28VDC, 115VAC/ 400Hz. 1Ø, 115VAC/

400Hz. 3Ø- MIL-STD-704A Thru 704E, MIL-STD-1275A)

◆ Wiring (Low Toxicity -MIL-C-24643)◆ Vibration (15 to 2,000Hz At 0.1g2/ Hz. (RMS~12g)

MIL-STD-810F Method 514.5) & Shock (20g for 11ms MIL-STD-810F Method 516.5)

AVAILABILITY

Now

717 Series Air-Over Conduction Cooled ATR EnclosuresCompatible Architecture: VME, VME64x, VXS, VPX and CPCI architectures

The 717 Series is available in standard ARINC sizes that include 1/2 ATR Short to 1-1/2 ATR Long and any custom form factor. From bus standards to application-specific custom designs, the 717 Series provides an expansive offering of ATRs for platforms such as the VME, VME64x, VXS, VPX and CPCI architectures. The 717 Series is a member of SIE’s conduction-cooled line of ATRs. Designed specifically for rugged deployment and to direct air over the thermal conducting walls, its cooling can be configured to meet application require-ments by either drawing air through the walls and out a rear exhaust plenum or forcing air down the walls and directing it away from the equipment. When configured for unpressurized environments, the 717 Series can be configured with a high-altitude cooling scheme to permit ultimate performance at altitudes up to 50,000 feet. When used in conjunction with SIE’s System Performance Monitoring” technology, the 717 Series ATR can be con-figured to activate internal heaters in cold start-ups or control the performance outputs of the optional external cooling fan to maintain an optimal thermal environment for the circuit card assemblies. In addition, the 717 Series is sealed from the environment and meets MIL standards for up to 95% RH (humidity), 5% for 48 hours (salt fog), no fungal growth, 13.5g acceleration, and thermal shock performance. The 717 Series can be configured with an optional avionics trays for isolation from shock and vibra-tion environments common to airborne, vehtronics and shipboard applications. For applications where stringent weight requirements are an issue, SIE Computing Solu-tions offers a lightweight composite solution.

FEATURES & BENEFITS

◆ Dip-brazed construction◆ Expansive range of ARINC sizes◆ Modular power supply /AC or DC filtered inputs◆ Cold start heaters & high altitude fan offering◆ Configurable I/O panel

EnclosuresEncl

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es

CONTACT INFORMATION


SIE Computing Solutions10 Mupac DriveBrockton, MA 02301USA800-926-8722 Toll Free508-588-6110 Telephone508-588-0498 [email protected]

ALC888 HD SUPPORTED AUDIO

◆ Enhanced configurability via a Mini PCIe Expansion Slot that can be configured by SIE for video capture, DOM, wireless and many other functions

AVAILABILITY

Now

APPLICATION AREAS

Harsh industrial and military environments requiring small form factors and where extreme temperatures, air particulates, liquids and vibration prevent the use of standard commercial computers.

“Mupac” 760 Small Form Factor Series

Designed to deliver mission-critical computing perfor-mance in a fully portable enclosure - ideal for rugged small spaces.

Building on SIE Computing Solution’s 40-year history of design excellence in rugged electronic and embedded systems, the “Mupac” 760 Small Form Factor product line is designed for mission-and performance-critical communications and intelligence. “Mupac” 760 Small Form Factor compute platforms allow data processing in the field in a fully transportable, highly rugged com-puting module that improves speed and efficiency by completing processing in the machine, at the distributed level, before delivering data upstream. SIE Computing Solutions’ Small Form Factor line provides a complete distributed computing module – exceptionally powerful and fully portable in everything from a UAV to a back-pack. “Mupac” 760 Small Form Factor compute modules enable the most modern technology to work in harsh con-ditions at a level of distributed computing never before possible. In addition to standard offerings, the “Mupac” 760 Small Form Factor line can also be customized for a wide variety of unique specifications, providing high-end compute-class performance for harsh industrial and military environments where extreme temperatures, air particulates, liquids and vibration prevent the use of standard commercial computers.

FEATURES & BENEFITS

◆ Extremely rugged◆ Easily customized◆ Dip-brazed construction◆ Modular power supply◆ Rated to operate in temperatures ranging from -40 to

+85 degrees Celsius

TECHNICAL SPECS

◆ Two standard dimensions: 3.25” h x 6.5” w x 8.5” d or 5.25” h x 6.5” w x 8.5” d

◆ Available in an IP67 NEMA Rated Version and IP50 NEMA Rated Version

◆ Quickly deployable with Intel® Core™ i3/i5/i7 multi-core processors and up to 4 GB RAM

◆ Standard I/O includes dual DVI display: one DVI-I (DVI-D+VGA) and one DVI-D; GbE Ethernet Port, 8 x USB 2.0, 2 x RS-232, 2 x SATA 3Gb/s with RAID 0,

1 support; 1 x 6-pin header for KB/MS

EnclosuresEncl

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The Protocol Wedge

When you look at all the interconnects in the market, things can

get confusing and frustrating fast. The best way to untangle this

morass, as a rule of thumb, is to look at the interconnects by the

distance they are designed to run (http://en.wikipedia.org/wiki/

List_of_device_bit_rates .) The closer together the connected

devices reside, the “lighter” the protocol stack, and less protocol

latency will be experienced. The further away the devices are, the

“heavier” the protocol stack, and more protocol latency will be

induced. This observed phenom-

enon creates a reverse “wedge”,

with the apex starting at chip-to-

chip connections, and the wide end

of the wedge at the location-to-

location end, the Internet.

Chip-to-chip connections don’t

need a lot of protocol to control data

flow. PCI and PCIExpress are some

examples. You don’t have to worry

about multiple packet recipients,

you don’t need to worry too much

about synchronization and error

handling, and you don’t have big

packet headers defining the origin

of the data and who handled it

before it was received. In a point-to-

point connection like chip-to-chip, it can only come from the trusted

device on that link.

Board-to-board connections have heavier protocols. RapidIO and

InfiniBand are examples. You could have multiple data senders, error

handling gets messier, critical data may need time-stamping, and

synchronization becomes necessary. Box-to-box connections get

even heavier. Ethernet is a perfect example. Not only do you have

the overheads of the board-to-board connections, but now you need

to verify the sender as a valid data source, you need a history of who

handled the data before it was received, error handling becomes

more prolific, and packet headers become huge.

Finally, we have location-to-location connections. Internet Protocol

(IPv6) is an example here. The protocol stack is a monster; all the

legacy protocol requirements are there plus many more. Packet

headers are now massive, the history of the packet across all the pre-

vious internet systems involved in its transmission is needed, and

byte counts plus packet numbers are needed, too (since most large

packets are broken-up into smaller packets and must be reassembled,

in order, by the receiver).

Nicholas Negroponte warned us about this increasing protocol-stack

burden in his 1996 book, “Being Digital”. He claims that “the bits

about the bits” are becoming more important that the bits themselves

(the real usable data). Protocol, while giving us the benefits of secu-

rity and reliability, kills performance and efficiency. Data centers and

“cloud computing” machines are beginning to tell us that we need to

reduce the protocol stack overheads of the board-to-board and box-

to-box (or rack-to-rack) interconnects. The way to do this is to make

those interconnections look more

like chip-to-chip connections, with

their lighter protocol stacks. RDMA

(Remote Direct Memory Access)

used in InfiniBand and Ethernet

today are doing just that. But, IPvx

protocols continue to expand and

become heavier. This modifies the

protocol “wedge” somewhat, and

gives us much better performance

and efficiency once the internet

connection protocols are stripped-

off when they enter the data center.

Ray Alderman is

the Executive Di-

rector of VITA,

an ANSI-certified standards developer for

high-performance computer systems and archi-

tectures used in critical embedded applications.

He is a recognized authority on embedded architectures

and computing.

By Ray Alderman, Executive Director, VITA

VIEWPOINT

“DATA CENTERS AND ‘CLOUD COMPUTING’

MACHINES ARE BEGINNING TO TELL US THAT WE

NEED TO REDUCE THE PROTOCOL STACK

OVERHEADS OF THE BOARD-TO-BOARD AND

BOX-TO-BOX INTERCONNECTS.”

Protocol, while giving us the benefits of security and reliability, kills performance and efficiency.

Produced and managed by y UBM Canonubmcanonevents.com

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