putting vpx and openvpx to work - vic myers vpx and openvpx to work 3u vpx board figure 5 the 3u...

PPPPPentek, Inc.entek, Inc.entek, Inc.entek, Inc.entek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: [email protected] • http://www.pentek.com

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Putting VPX and OpenVPX Putting VPX and OpenVPX Putting VPX and OpenVPX Putting VPX and OpenVPX Putting VPX and OpenVPX to Wto Wto Wto Wto WorkorkorkorkorkBy: Rodger H. Hosking


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Putting VPX and OpenVPX to WPutting VPX and OpenVPX to WPutting VPX and OpenVPX to WPutting VPX and OpenVPX to WPutting VPX and OpenVPX to WorkorkorkorkorkFirst Edition

PPPPPentek, Inc.entek, Inc.entek, Inc.entek, Inc.entek, Inc.One Park Way, Upper Saddle River, New Jersey 07458

Tel: (201) 818-5900 • Fax: (201) 818-5904Email: [email protected] • http://www.pentek.com

Copyright © 2016 Pentek Inc.Last updated: February 2016

All rights reserved.Contents of this publication may not be reproduced in any form without written permission.

Specifications are subject to change without notice.Pentek, GateFlow, ReadyFlow, SystemFlow, Cobalt, Onyx, Talon, Bandit, Flexor, GateXpress, SPARK, and QuickPac are trademarks or registered trademarks of Pentek, Inc

Other trademarks are properties of their respective owners..

VPX, VPX REDI, OpenVPXVPX, VPX REDI, OpenVPXVPX, VPX REDI, OpenVPXVPX, VPX REDI, OpenVPXVPX, VPX REDI, OpenVPX

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FPGA RFPGA RFPGA RFPGA RFPGA Resourcesesourcesesourcesesourcesesources

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ApplicationsApplicationsApplicationsApplicationsApplications

by

RRRRRodger Hodger Hodger Hodger Hodger H. Hosking. Hosking. Hosking. Hosking. HoskingVice-President & Cofounder of Pentek, Inc.

®


33333

Putting VPX and OpenVPX to Work

Preface

Before the advent of OpenVPX, designers of embedded systems took advantage of the extreme connectivityoffered by VPX (VITA 46), but were faced with a virtually unlimited number of possible implementations.

Specific choices for the control and data channel assignments for each slot, the backplane connectivity, and serial fabricswere often made somewhat arbitrarily to suit the particular needs of the current system.

Although following the general framework of VITA 46, each system tended to be so unique, that the boards andbackplanes designed for one system were seldom usable in other systems, even from the same vendor.

Now, OpenVPX provides an effective method for describing VPX components, and also defines numerous “profiles” forboards, slots and backplanes that detail specific configurations of channels, interconnections and fabrics.

Instead of starting from scratch each time, designers can browse through these standardized profiles to find one thatsatisfies the objectives of each new system.

By narrowing the field of configurations, these profiles boost reusability and interoperability between vendors.OpenVPX presents a formal, well-organized system for defining all components in VPX systems, and the efforts of the

working group should be applauded. Many of the figures and the profiles in this handbook were derived from thefull OpenVPX specification. The OpenVPX specification is maintained by VITA as VITA 65.

For more information on complementary subjects, the reader is referred to these Pentek Handbooks:Critical Techniques for High-Speed A/D Converters in Real-Time Systems

High-Speed Switched Serial Fabrics Improve System Design

Putting FPGAs to Work in Software Radio Systems

High-Speed, Real-Time Recording Systems

Software Defined Radio

http://www.pentek.com/adhandbook/ADHandbook.cfm

http://www.pentek.com/dsphandbook/DSPHandbook.cfm

http://www.pentek.com/fpgahandbook/FPGAHandbook.cfm

http://www.pentek.com/rechandbook/rechandbook.cfm

http://www.pentek.com/fpgahandbook/sftradHandbook.cfm


44444


VPXVPXVPXVPXVPX VPX REDIVPX REDIVPX REDIVPX REDIVPX REDI


Figure 1 Figure 2

To eliminate backplane bottlenecks of the venerableVME architecture, the embedded community launchedthe VPX initiative, formally defined under VITA 46.

The shared, parallel VMEbus connecting all cardslots is completely replaced by numerous point-to-pointgigabit serial links between VPX card slots.

VPX shares the same outline as 3U and 6U cardsand supports XMC mezzanine modules defined underthe VITA 42 standard.

VPX uses three MultiGig RT connectors for a 3Ucard and seven for a 6U card.

As a result, VPX cards boost the traffic bandwidthby a several orders of magnitude compared to VME.

The VITA 46.0 VPX base specification does notdefine backplane topologies or specific gigabit serialfabrics or protocols.

Implementations of each fabric protocol are definedas subspecifications, or “dot specs.”

As industry started using VPX, a new extensionemerged to deal with severe environmental requirements.

The VITA 48 REDI (Ruggedized Enhanced DesignImplementation) defines specific mechanical designs forenhanced thermal management using forced air, conduc-tion cooling, and liquid cooling methods.

It also defines protective metal covers for thecards to satisfy new requirements for simplified fieldservicing in deployed military applications.

� REDI - Ruggedized Enhanced Design Implementation

� Defines Specific Mechanical Design Implementations for VPX

� Enhanced thermal management

� Air, conduction, and liquid cooling

� Improved structural integrity

� Cover plates to protect circuitry and ESD protection

� 2 Level Maintenance compatibility

� Modules can be field swapped for field maintenance

� Dot Specifications Define Implementation Details

� VITA 48.1 – REDI Air Cooling

� VITA 48.2 – REDI Conduction Cooling

� VITA 48.3 – REDI Liquid Cooling

� VITA 48.5 – Air Flow Through Cooling

■ Switched Fabric Links Boost I/O Speed● Eliminates parallel bus backplane bottlenecks● 8 to 24 gigabit serial 4X links for each card slot

■ Optional Switch Card● Programmable reconfiguration of serial link connectors

■ 3U and 6U Form Factors● Same dimensions as VME

■ New Backplane I/O Options● Optical and RF backplanes now available

■ Fully Compliant With XMC Modules● VITA 42 XMC specification

■ Modernized Power Distribution● Supports high-power and high-density cards


55555


OpenVPX InitiativeOpenVPX InitiativeOpenVPX InitiativeOpenVPX InitiativeOpenVPX Initiative


OpenVPX: VITOpenVPX: VITOpenVPX: VITOpenVPX: VITOpenVPX: VITA 65A 65A 65A 65A 65

� Rationale

� To embrace VPX as a new system architecture, U.S. DOD mandated

industry-wide definition and adoption of standards for VPX technology

� Provide interoperability across vendors

� Promote market priced components among competitors

� Provide long-term availability for life-cycle support

� OpenVPX Industry Organization was formed in January 2009

� 26 embedded system vendors, manufacturers and contractors

� Goal: accelerate definition and turn over to VITA for standardization

� Transition to VITA Standard

� Transferred to VSO (VITA Standards Organization) in October 2009

� Designated as VITA 65

� Ratified by VITA in February 2010

� ANSI Standardization

� Received in June 2010

� Defines sets of system implementations and system architectures

� Promotes multi-vendor interoperability and life-cycle maintenance

� Uses existing VITA 46 VPX Baseline and VITA 48 VPX REDI standards

� Defines various sizes of pipes used for serial communication

� Defines various profiles for structure and hierarchy:

� slot profiles

� backplane profiles

� module profiles

� development chassis profile

� Defines multiple planes for signal types within the specification:

� Utility

� Management

� Control

� Data

� Expansion

Figure 3 Figure 4

The OpenVPX organization was formed in January2009 to promote industry-wide standards and long-termavailability of VPX technology across the industry. Theoriginal VPX specification was being used, but because itpermitted such a wide range of architectures, VPX systemstended to be unique, vendor-specific implementations.

The mission of OpenVPX was to enhance theoriginal VPX standard by adding a set of well-definedsystem architectures, nomenclature and conventionsto enable interoperability among vendors. Consisting ofkey vendors in the embedded-system community, alleager to convince government and military customersthat VPX was suitable for current and future systems,the group made fast progress and turned over thecompleted specification to the VSO in October 2009for standardization under VITA 65. In February 2010, thespecification was ratified by VSO and ANSI approvalwas received in June 2010.

OpenVPX defined new nomenclature for systems todescribe the gigabit serial links in terms of the numberof lanes and their function. The term “pipe” is used todefine the number of bidirectional differential serialpairs that are grouped together to form a logical datachannel.

OpenVPX also categorized the different kinds oftraffic carried though the pipes as “planes”. The fiveplanes defined are the utility, management, control,data and expansion planes.

In order to define architectural characteristics ofsystems, several “profiles” were defined. A slot profilespecifies the pipes and planes found on the backplaneconnectors of each slot. The module profile specifiesthe pipes, planes, fabrics and protocols implementedon each card. The backplane profile defines how theslots are connected to each other by pipes. Andfinally, the development chassis profile includes thebackplane profile and defines the dimensions, powersupply, and cooling method.


66666


3U VPX Board3U VPX Board3U VPX Board3U VPX Board3U VPX Board

Figure 5

The 3U board outline is the same as the 3U VMEboard. The board has a P0 Utility connector whichprovides power, system reset, reference clock, addressing,bus management, and any other required utility functions.

The 3U board has two MultiGig RT2 Signal connec-tors, P1 and P2. Each connector provides up to four 4Xgigabit serial ports and this board offers a maximum ofeight 4X ports. The VPX specification also defines howmany signal and ground connections are available persignal connector.

The 3U VPX board has one XMC mezzannine sitethat accepts one XMC module.

The 6U board outline is the same as the 6U VMEboard. The board has a P0 Utility connector whichprovides power, system reset, reference clock, addressing,bus management, and any other required utility functions.

The 6U board has six Multi-Gig RT2 Signalconnectors P1 through P6. Each connector provides upto four 4X gigabit serial ports and this board offers amaximum of 24 4X ports. The VPX specification alsodefines how many signal and ground connections areavailable per signal connector.

The 6U VPX board has two XMC mezzannine siteand accepts one or two XMC modules.

� 3U board outline same as 3U VME

� P0 Utility Connector

� Power, system reset, reference clock,bus management, addressing, etc.

� MultiGig RT-2 for P1 and P2 Signal Connectors

� Definitions for differential or single-ended signals

� Up to eight 4X gigabit serial ports

� One XMC mezzanine site

VITA 46 – 3U VPX

XMC

Module

P0 P2P1

P1 – P2 Signal Connectors

Differential (each conn)

Four 4X Serial Ports

+8 single ended signals+40 grounds

~or~

Single-Ended (each conn)

+ 80 single ended signals

+ 32 grounds

Pin alignment blocks

� 6U board outline same as 6U VME

� P0 Utility Connector

� Power, system reset, reference clock,bus management, addressing, etc.

� MultiGig RT2 for P1 through P6 Signal Connectors

� Definitions for differential or single-ended signals

� Up to 24 4X gigabit serial ports

� One or two XMC mezzanine sites

VITA 46 – 6U VPX

P0

XMC

Module

XMC

Module

P2 P3 P4 P5 P6P1

P1 – P6 Signal Conns

Differential (each conn)

Four 4X Serial Ports

+ 8 single ended signals

+ 40 grounds

~or~

Single-Ended (each conn)

80 single ended signals+ 32 grounds

Pin alignment blocks

Figure 6

6U VPX Board6U VPX Board6U VPX Board6U VPX Board6U VPX Board



77777


OpenVPX PipesOpenVPX PipesOpenVPX PipesOpenVPX PipesOpenVPX Pipes


Figure 7 Figure 8

� Pipes

� A grouping of differential pairs for an interconnect channel

� Does not specify fabric protocols

X3232OFPOctal Fat Pipe

X1616QFPQuad Fat Pipe

X88DFPDouble Fat Pipe

X44FPFat Pipe

X22TPThin Pipe

X11UTPUltra Thin Pipe

Also used# Diff PairsAbbreviationPipe Name

6U

P0

P1

P2

P3

P4

P5

P6

P2

Utility

signals

Utility

signals

16 full-duplex

differentialpairs

�One QFP

�Two DFPs

�Four FPs

�Eight TPs

�Sixteen UTPs

P0

P1

P2

3U

P2

Utility

signals

Utility

signals

8 single-endedsignals

8 single-endedsignals

16 full-duplexdifferentialpairs

�One QFP

�Two DFPs

�Four FPs

�Eight TPs

�Sixteen UTPs

OpenVPX Connector LOpenVPX Connector LOpenVPX Connector LOpenVPX Connector LOpenVPX Connector Layoutayoutayoutayoutayout

The OpenVPX Pipes are groups of differential pairsthat are used to interconnect channels. As shown in thefigure above, the defined OpenVPX pipe sizes rangefrom one lane (1X) called an “ultra-thin pipe” or UTP,up to 32 lanes (32X) called an “octal fat pipe” or OFP.

The next size up from UTP is the “thin pipe” or TPwhich has two lanes or 2X. The popular 4X link iscalled a “fat pipe” or FP. The next size up from it is the“double fat pipe” or DFP with 8X links.

Next in size is the “quad fat pipe”, QFP or 16X andthe fattest one is the “octal fat pipe”, OFP or 32X.

As used here and elsewhere in this handbook, thedesignation NX is the same as XN, or xN, where N isthe number of lanes/pipes; The last designation, xN, ismost commonly used with PCI Express.

Shown here are the connector layouts for the 3Uand 6U cards.

As shown previously, the 3U card has one utilityconnector for utilities such as power, clock, etc. It alsohas two signal connectors P1 and P2. Each of theseprovides connections for eight single-ended signals plusgrounds. In addition, each one provides 16 full-duplexdifferential pairs with the following pipes: sixteen UTPs,eight TPs, four FPs, two DFPs and one QFP.

Likewise, the 6U board has the same utility connec-tor and six signal connectors P1 through P6. Each ofthese provides connections for eight single-ended signalsplus grounds. In addition, each one provides 16 full-duplexdifferential pairs with the following pipes: sixteen UTPs,eight TPs, four FPs, two DFPs and one QFP.


88888


TTTTTypical OpenVPX Backplane Pypical OpenVPX Backplane Pypical OpenVPX Backplane Pypical OpenVPX Backplane Pypical OpenVPX Backplane Profilerofilerofilerofilerofile


TTTTTypical OpenVPX Module Pypical OpenVPX Module Pypical OpenVPX Module Pypical OpenVPX Module Pypical OpenVPX Module Profilerofilerofilerofilerofile

Figure 9 Figure 10

The OpenVPX specification established quite alarge number of backplane profiles. The backplaneprofile is a physical definition of a backplane implemen-tation. Included in this definition are:

● Slot sizes such as 3U or 6U

● Slot spacing such as 1.00, 0.85, or 0.80 inches

● Quantity of slots and type of slots

● Topologies used to interconnect the slots, such as:◆ Mesh◆ Central switch◆ Distributed◆ Root-leaf

Shown here is a typical 6-slot backplane with fivepayload cards and one switch/management card.Backplanes such as this one are primarily intended fordevelopment environments. However, some systemscould be deployed in the field with these backplanes.

In addition to the backplane profiles, OpenVPXspecifies module profiles. The module profile provides aphysical mapping of ports into the module’s backplaneconnectors. The module profile includes the assignmentof specific protocols used for each port. It also providesfirst-order compatibility checks between modules andslots.

The typical module profile above shows the assign-ments for P1, P2, and P4. P0 is used for the utilityfunctions. The assignments for the balance of connec-tors may be user-specified to suit the application.

6U

P0

P1

P2

P3

P4

P5

P6

P2

Data Plane: Two FPs

PCIe Gen 2.0 at 5 GHz

Expansion Plane: Two FPs

SRIO 2.0 at 5 GHz

Control Plane: 2 UTPs

1000BaseX


99999


Figure 11

Figure 12

XMC: Switched Serial FXMC: Switched Serial FXMC: Switched Serial FXMC: Switched Serial FXMC: Switched Serial Fabric for PMCabric for PMCabric for PMCabric for PMCabric for PMC PMC/XMC Connector DefinitionPMC/XMC Connector DefinitionPMC/XMC Connector DefinitionPMC/XMC Connector DefinitionPMC/XMC Connector Definition


Defined under VITA 42.0, the XMC specificationextends the PMC card by adding new connections tosupport gigabit serial interfaces plus a growing list ofalternative I/O standards.

As shown in the figure above, VITA 42.0 is the basespecification that includes general information, referenceand inheritance documentation, dimensional specifica-tions, connectors, pin numbering and primary allocationof pairing and grouping of pin functions.

As of this writing VITA 42.0 and all subspecificationsexcept 42.10 have been approved by VITA and ratifiedby ANSI. Subspecification 42.10 has been withdrawn.

XMCs can be single- or double-width modules thatuse a pin-socket connector with 114 pins arranged in a6 x 19 array. A single-width XMC can have one or twoconnectors with pin functions as shown in Figure 12. Adouble-width XMC can have up to four connectors.

To support gigabit serial interfaces, notice that bothP15 and P16 connectors define 10 full-duplex differen-tial pair lines. The VITA 42.0 base specification does notdictate signal types, data rates, protocols, voltage levelsor grouping for these signals. Instead, it wisely leaves thatup to the several subspecifications that follow, allowingXMCs to evolve as new standards emerge.

In fact, contrary to the fundamental mission ofsupporting serial interfaces, the first subspecification,VITA 42.1, defines these same pins for Parallel RapidIO.

VITA Doc Description

42.0 Base Specification:connectors, mechanical, etc.

42.1 Parallel RapidIO Protocol Layer

42.2 Serial RapidIO Protocol Layer

42.3 PCI Express Protocol Layer

42.6 10 GbE Protocol Layer

42.10 General Purpose I/O

P15 Primary XMC Connector● 10 differential pairs each direction● JTAG● System Management● Auxiliary● 3.3 V Power:

● Main: 4 pins, 1 A/pin, 13.2 W● Auxiliary: 1 pin, for system management

● Variable Power● 8 pins, 1 A/pin● 5 V (40 W max) or 12 V (96 W max)● Modules must accept 5 V or 12 V● Carriers may provide 5 V or 12 V

P16: Secondary XMC Connector● 10 more differential pairs each direction● High-speed or single-ended user I/O● Extensions of gigabit serial fabrics

While VITA 42.1 is approved and fielded, few vendorshave embraced this standard and have instead optedfor the more popular serial protocols.

As shown in Figure 12, most of the pins on P15 arereserved for serial links, power and other functions, but P16has a wealth of user-defined pins now being addressed bythe VITA 42.10 General Purpose I/O draft specification. Itoffers a standardized way of implementing interfaces forpopular system I/O including Ethernet, USB ports,RS-232, RS-485, Serial ATA, Fibre Channel, and SAS(Serial Attached SCSI). The clear benefit here is that byfollowing these definitions, XMC and carrier boarddesigners can achieve a much wider range of interoperab-ility, the essential goal of industry standards.


1010101010


VPX Specification StatusVPX Specification StatusVPX Specification StatusVPX Specification StatusVPX Specification Status


Figure 13

For the latest and most up-to-date specificationsregarding VITA/ANSI standards, contact:

VITA

http://www.vita.com/specifications

� VITA 46.0 – VPX Baseline Specification Approved

� VITA 46.1 VMEbus Signal Mapping Approved

� VITA 46.3 4x Serial RapidIO Signal Mapping Approved

� VITA 46.4 PCI Express Signal Mapping

� VITA 46.6 Gbit Ethernet Control Plane Signal Mapping

�

�

VITA 46.7

VITA 46.8

10Gbit Ethernet Signal Mapping

Infiniband Draft

� VITA 46.9 PMC/XMC Rear I/O Fabric Signal Mapping Approved

�

�

VITA 46.10

VITA 46.11

Rear Transition Module

System Management

Approved

Approved

�

�

�

�

VITA 48.0

VITA 60.0

VITA 62.0

VITA 63.0

–

–

–

–

REDI – Baseline Specification

VPX: Alterative Connector for VPX

VPX: Power supply

VPX: KVPX, Alternate Connector for VPX

� VITA 48.1 REDI Air Cooling Approved

Approved

Approved

Approved

� VITA 48.2 REDI Conduction Cooling

�

�

VITA 48.3

VITA 48.4

REDI Liquid Cooling

REDI Mech Spec for Liquid Flow Through

Draft

Draft

�

�

VITA 48.5

VITA 48.7

Air Flow Through Cooling

Air Flow-By Cooling

� VITA 65.0 – OpenVPX

� VITA 65.0 - Base Specification Approved

Approved

Approved

Approved

Approved

� VITA 66.0 – Optical Interconnect on VPX

� VITA 66.0 Optical Interconnect on VPX, Base Spec

�

�

�

�

VITA 66.1 Optical Interconnect on VPX, MT Variant

VITA 66.2 Optical Interconnect on VPX, Airinc Variant

VITA 66.3 Optical Interconnect on VPX, Beam Variant

VITA 66.4 Optical Interconnect on VPX, Half Width Bm Var

�

�

VITA 67.0

VITA 68.0

–

–

Coaxial Interconnect on VPX

VPX: Compliance Channel

� VITA 67.0 Coaxial Interconnect on VPX, Base Spec

VITA 67.1 Coaxial Interconnect on VPX, 3U

VITA 67.2 Coaxial Interconnect on VPX, 6U 8 Position

�

�

�

Approved

Approved

Approved

Approved

Approved

Approved

Approved

Approved

ApprovedApproved

Approved

Approved

Approved

Approved

VITA 67.3 Coaxial Interconnect on VPX, 6U 4 Position Draft

Draft

Draft

As of this writing, the VPX Baseline Specificationhas been approved by VITA, ratified by ANSI and hasbeen released as VITA 46.0. Most of its subspecificationshave also been approved.

Likewise, the VITA 48.0 REDI is approved. Alsoapproved are most of its subspecifications.

Also, the OpenVPX VITA 65.0 Base Specificationhas been approved by VITA and ratified by ANSI.

Two more VITA standards have been approved:VITA 66.0 Optical Interconnect on VPX and VITA67.0 Coaxial Interconnect on VPX. The latter wasinitiated by DRS. Pentek has been actively involved inthe development of this specification.


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1. Why was OpenVPX created in the first place?The US Department of Defense and other users aremandating improved implementation of open standardsand interoperability. VPX specifications have been focusedat the board level, but there is also a need for consideringsystem-level requirements to improve interoperability andreduce customization, testing, cost, and risk.

2. What are the general OpenVPX features?• OpenVPX is a defined set of system implementationswithin VPX• Specifies a set of system architectures• Uses existing VPX REDI standards and drafts withminimal possible changes• Defines multiple planes for Utility, Management, Control,Data, Expansion• Defines various sizes of pipes used for serial communication• Defines several types of profiles for structure and hierarchyin the specification (slot profile, backplane profile, moduleprofile, development chassis profile)• Backplane profiles define the backplane topology (types:centralized and distributed switching, and host/slave)

3. Does OpenVPX replace VPX?No. OpenVPX is a system specification for VPX thatprovides a defined framework for interoperability betweenOpenVPX products. OpenVPX leverages the VPX dotspecs for details such as fabric protocols.

4. What’s the difference between VPX and OpenVPX?OpenVPX builds on VPX dot specs and provides a definedframework for interoperability between OpenVPX productsbased on compatible OpenVPX profiles for modules, back-planes, and development chassis.

5. What is an OpenVPX module profile?An OpenVPX module profile is a physical mapping ofPorts onto a given Module’s backplane Connectors andprotocol mapping(s), as appropriate, to the assigned Port(s).This definition provides a first-order check of operatingcompatibility between modules and slots as well as betweenmultiple modules in a chassis. Profile parameters are used tofurther describe properties of a Module Profile.

6. What is an OpenVPX backplane profile?An OpenVPX backplane profile is a physical definitionof a backplane implementation that includes details suchas the number and type of slots that are implemented


and the topologies used to interconnect them. Ulti-mately a Backplane Profile is a description of channelsand buses that interconnect slots and other physicalentities in a backplane. Profile parameters are used tofurther describe properties of a backplane profile.

7. What are OpenVPX pipes used for?OpenVPX pipes are a physical aggregation of differentialpairs used for common function that is characterized interms of the total number of differential pairs. A pipe is notcharacterized by the protocol used on it. The followingpipes are predefined by OpenVPX: Ultra Thin Pipe (UTP),Thin Pipe (TP), Fat Pipe (FP), Double Fat Pipe (DFP),Quad Fat Pipe (QFP), Octal Fat Pipe (OFP).

8. What styles of OpenVPX backplanes are available?OpenVPX backplanes are available in lengths between oneand twenty-one slots. On most standard backplanes, boardsare located on 1.0" centers (i.e. 1.0" pitch), though 0.8"pitch or 0.85" pitch may also be used. Backplanes are avail-able in 3U and 6U form factors. Furthermore, there are manydifferent profiles available for OpenVPX backplanes:• Central switch topologies• Distributed topologies• Root-leaf topologies

9. Can I get conduction-cooled OpenVPX hardware?Yes. A popular OpenVPX card style is the conduction-cooledmodule. These are used mainly in military and aerospaceapplications where convection cooling cannot be used.These allow heat to conduct through the printed circuitboard or through a conduction plate on the module. Expan-ding wedge locks then transfer the heat out to the chassisthrough wide slots cut into the metal chassis sidewalls.

10. What are the OpenVPX connector pin assignments?OpenVPX connector pin assignments are defined inseveral slot profiles aimed at different types of slots:• Payload slot profiles• Switch slot profiles• Peripheral slot profiles

11. What power supplies are available on the backplane?The same as VPX with the exception that OpenVPXcurrently does not support the 48V power option for 6Umodules. OpenVPX also encourages more standardizationin the use of the primary power rails but the rails are unchangedfrom VPX.

(These Frequently Asked Questions Courtesy of VITA)


1212121212



Property Copper OpticalInterface Transceiver Cost Low High but dropping

PC Network Interface Cards Integrated in PC or laptop Usually optional at $100-$200

Power over Ethernet Supported at low cost Not possible

Data Rate 1 GHz >10 GHz

Cable Loss - 100 meters 94% 3%

Max Transmission Distance 100 m (cat 6) 300 m (multi-mode)10 km (single mode)

EMI Susceptibility Risk Moderate Zero

EMI Radiation Risk Moderate Zero

Security / Eavesdropping Risk High Extremely Low

Termination Costs Low High

Cable Cost per Length High Low

Cable Weight per 1000 m 60 to 600 kg 6 kg

Fire Hazard Supports current flow if shorted Zero

Tensile Strength 25 pounds 100-250 pounds

Cleaning Requirements No Yes

Optical Links Offer Many BenefitsOptical Links Offer Many BenefitsOptical Links Offer Many BenefitsOptical Links Offer Many BenefitsOptical Links Offer Many Benefits

Figure 14

One major shortcoming of copper cable is signal loss,which becomes a serious limitation for higher frequencysignals and longer cable lengths. Across a span of 100meters, optical cables can sustain data rates up to 100 timeshigher than copper cable.

Because copper cables radiate electromagnetic energy,eavesdropping on network cables is a major security concern,not only for military and government customers, butalso for corporations, banks, and financial institutions.Advanced signal sniffers in vehicles and briefcases arehard to detect and restrict. Optical cables are extremelydifficult to “tap” without damaging the cable, resultingin immediate detection.

Signals flowing in copper cables are also susceptibleto contamination from nearby sources of electromagneticradiation, such as antennas, generators, and motors. Thisis critical for military and commercial aircraft and ships,as well as manned or unmanned vehicles, which are oftenpacked with dozens of different electronic payloads. Opticalcables are completely immune to EMI.

Physically, optical cables are much smaller and lighterthan copper cables, especially important for weight-sensitiveapplications such as weapons, unmanned vehicles, and aircraft.Optical cables will operate just as well when submerged inseawater, and are completely immune to electrical shorting,especially important where explosive vapors may be present.To ease installation through conduits and passages, opticalcables have smaller diameters and can withstand up to tentimes more pulling tension than copper cables.

Driven by huge commercial markets for data servers,storage networks, telecom systems, and home or officeinternet and entertainment systems, optical interfaces arereplacing older copper connections for good reasons: costand performance. As the use of optical cables becomesmore widespread, the cost per length can be muchlower than copper cables that depend on commoditymetal pricing. As is often the case, industrial, militaryand government embedded systems are now takingadvantage of the many benefits of this rapidly advanc-ing commercial technology.


1313131313



An optical cable is a waveguide for propagating lightthrough an optical fibre. It consists of a central core cladwith a dielectric material having a higher index ofrefraction than the core to ensure total internal reflec-tion. Optical cables use either multi-mode or single-mode transmission.

Multi-mode cables accept light rays entering the corewithin a certain angle of the axis. They travel down thecable by repeatedly reflecting off the dielectric boundarybetween the core and the cladding. The core diametersare typically 50 or 62.5 mm, and the wavelength of lightis typically 850 nm.

Single-mode cables propagate light as an electromag-netic wave operating in a single transverse mode straightdown the fibre using typical wavelengths of 1310 and1550 nm. The core diameter must be no greater than tentimes the light wavelength, typically 8 to 10 µm. Althoughsingle-mode cables can carry signals over lengths 10 to100 times longer than multi-mode, the transceivers aremore expensive.

Optical CablesOptical CablesOptical CablesOptical CablesOptical Cables

Hundreds of different types of optical cable connec-tors exist in the market, each addressing specific applica-tions and environments. The challenge is connecting theends of two optical cables to retain the maximum fidelity ofthe light interface, in spite of human factors, tolerances,contamination, and environments. Special tools and kitsfor cleaning the ends of each optical fibre are essentialfor reliable operation.

Optical TOptical TOptical TOptical TOptical Transceiversransceiversransceiversransceiversransceivers

Coupling electrical signals to light signals for transmis-sion through optical cables requires optical transceivers. Mostsystems require full-duplex operation for each optical link tosupport flow-control and error correction. A pair of opticalfibers, often bonded together in the same cable, supportstransmit and receive data flowing in opposite directions.

Although several analog light modulation schemes (includ-ing AM and FM) have been used in the past, now almost alltransceivers use digital modulation. Optical emitters simplytranslate the digital logic levels into on/off modulation of the laserlight beam, while the detectors convert the modulated light backinto digital signals. This physical layer interface for transporting0s and1s is capable of supporting any protocol.

The latest transceivers use laser emitters to supportdata rates to 100 Gbits/sec and higher, and each genera-tion steadily reduces the power, size and cost of devices.Different technologies are required for emitters and detectors,but both are often combined in a single product to providefull-duplex operation.

Optical transceivers thus provide a physical layerinterface between optical cables and the vast array ofelectrical multi-gigabit serial ports found on processors,FPGAs, and network adapters. As a result, optical transceiv-ers are transparent to the protocols they support, makingthem appropriate for any high-speed serial digital link.

Electrical signals of the optical transceivers connectto the end point device, which must then handle clockencoding and recovery, synchronization, and line balanceat the physical layer. Data link layer circuitry establishesframing so that data words can be sent and received acrossthe channel.

Figure 15

The Pentek Model 52611 Quad SerialFPDP 3U VPX modulesupports four full-duplex LC optical cables for connections

between chassis, each operating at over 400 MB/sec


1414141414



Choosing the Right Optical PChoosing the Right Optical PChoosing the Right Optical PChoosing the Right Optical PChoosing the Right Optical Protocolrotocolrotocolrotocolrotocol

Protocols define the rules and features supported by eachtype of system link, ranging from simple transmission of rawdata to sophisticated multi-processor support for distributednetworks, intelligent routing, and robust error correction. Ofcourse, heavier protocols invariably mean less efficient datatransfers and increased latency. Generally, it is best to use thesimplest protocol that satisfies the system requirements.

As an example of a lightweight protocol, Aurora for XilinxFPGAs features on-board link-layer engines and high-speedserial transceivers. Aurora is intended primarily for point-to-point connectivity for sending data between two FPGAs. Itincludes 8b/10b or 64b/66b channel coding to balance thetransmission channel, and supports single- or full-duplexoperation. Aurora handles virtually any word length and allowsmultiple serial lanes to be bonded into a single logical channel,aggregating single lane bit rates for higher data throughput.Data rates for each serial lane can be 12.5 Gbits/sec or higher.Extremely simple and with minimal overhead, Aurora is veryefficient in linking data streams between multiple FPGAswithin a module, or between modules across a backplane.

Stepping up in complexity is the SerialFPDP protocoldefined under VITA 17.1 It addresses several importantneeds of embedded systems including flow control to avoiddata overruns, and copy mode to allow one node to receivedata and also forward it on to another node. The copy/loopmode supports a ring of multiple nodes eventually complet-ing a closed loop. The nominal data rate on each lane is2.5 Gbits/sec, but advances in device technology now supportrates over twice that speed.

Infiniband defines a flexible, low-latency, point-to-point interconnect fabric for data storage and servers withcurrent rates of 14 Gbits/sec, moving up to 50 Gbits/sec inthe next few years. Channel speeds can be boosted by forminglogical channels by bonding 4 or 12 lanes.

The venerable Ethernet protocol still dominatescomputer networks, with 10GbE now commonly supportedby a vast range of computers, switches, and adapters. Eventhough Ethernet suffers from high overhead, making itsomewhat cumbersome for high-data rate low-latencyapplications, its ubiquitous presence virtually assurescompatibility.

VITVITVITVITVITA 49.0: VITA 49.0: VITA 49.0: VITA 49.0: VITA 49.0: VITA RA RA RA RA Radio Tadio Tadio Tadio Tadio Transporransporransporransporransport (VRT) Standardt (VRT) Standardt (VRT) Standardt (VRT) Standardt (VRT) Standard

Figure 16

New extensions to the VITA VRT Protocol define standardizedpackets for control and status of radio receiver and transmitter

equipment and digitized receive and transmit signalpayload packets for added flexibility

Approved as an ANSI standard in 2007, VITA 49.0defines standardized packets for connecting softwareradio systems for communications, radar, telemetry,direction finding, and other applications. The originalspecification addressed only receiver functions. Receivesignal data packets deliver digitized payload data, aprecise time stamp, and identifiers for each channel andsignal. Context packets include operating parameters ofthe receiver including tuning frequency, bandwidth,sampling rate, gain, antenna orientation, speed, heading,etc. One notable shortcoming of the original specifica-tion was its inability to control the receiver.

VITA 49.2, a new extension to VRT now in ballot-ing, adds control packets for delivering operationalparameters to all aspects of the radio equipment, as wellas support for transmitters. The new stimulus packetscontain streaming digital samples of signals to be transmit-ted. Other new packets, called capabilities packets, inform thehost control system of the available hardware in the radioalong with the allowed range of parameters for control.Lastly, spectrum packets from the receiver deliver spectralinformation to help simplify spectral survey and energydetection operations required by the control system.

With this latest extension, VRT provides a standard-ized protocol for controlling and configuring all aspectsof a software-radio transceiver. One major objective isenabling a common radio hardware platform to handle awide range of applications simply by implementing newhost software algorithms that exploit VRT protocols toachieve the required modes of operation.


1515151515



Optical InterOptical InterOptical InterOptical InterOptical Interfaces for VPXfaces for VPXfaces for VPXfaces for VPXfaces for VPX

Figure 17

Although optical interfaces using various connectorsand cable types have been deployed in embedded systemsfor years, most of them use front panel connections. Thiscan be a maintenance issue and is often not permitted inconduction-cooled systems.

The VITA 66 Fiber Optic Interconnect group hasdeveloped a set of standards that bridge optical connectionsdirectly through the VPX backplane connector. The firstthree are variants for 3U and 6U systems and are based onMT, ARINC 801 Termini, and Mini-Expanded Beamoptical connector technology, respectively.

The metal housings are physically dimensioned to replaceone or more of the standard MultiGig RT-2 VPX bladed copperconnectors. The high-density MT variant defined in VITA 66.1provides the highest density of the three, with up to 12 or 24 pairsof optical fibers, while VITA 66.2 and 66.3 each provide 2 pairs.

A fourth standard soon to be released, VITA 66.4, usesthe MT ferrule but with a metal housing half the size ofVITA 66.1, thus occupying only half of the 3U VPX P2connector position.

To simplify implementation, Samtec offers its FireFlyTM

Micro Fly-Over system. It consists of 12 pairs of opticalfibers installed in an MT ferrule. One 12-lane optical flat

cable connects to a small VCSEL laser emitter module andthe other connects to a detector module.

Figure 17 shows the industry’s first implementation ofthe emerging VITA 66.4 standard, the Pentek Model 59733U VPX Virtex-7 FMC carrier. Here the electrical interfacesof the FireFly emitter and detector modules are connecteddirectly to the GTX serial transceiver pins of the Virtex-7FPGA. Today, FireFly transceivers are rated for 14 Gbits/secwith 28 Gbits/sec versions coming soon. With the 5973operating at nominal data rates of 10 Gbits/sec through eachoptical fibre using Aurora protocol, the backplane throughputis 12 GB/sec, simultaneously in both directions.

The first version of this product uses multi-modetransceivers and cable to support cable lengths of 100 metersor more. Single-mode transceivers will extend the distance toseveral kilometers. A wide range of MT optical cables andconnector products allow board-to-board connections acrossthe backplane, and backplane-to-chassis connections forexternal MTP cables to remotely located systems.

The 12 GB/sec VITA 66.4 optical interface complementsthe 8 GB/sec Gen 3 x8 copper PCIe interface on VPX P1,offering plenty of I/O for demanding applications. Systemengineers can now choose between optical and copperlinks to solve high-data rate connectivity requirements.


1616161616



Early REarly REarly REarly REarly Roles for FPGAsoles for FPGAsoles for FPGAsoles for FPGAsoles for FPGAs LLLLLegacy FPGA Design Methodologiesegacy FPGA Design Methodologiesegacy FPGA Design Methodologiesegacy FPGA Design Methodologiesegacy FPGA Design Methodologies

Figure 18 Figure 19

As true programmable gate functions becameavailable in the 1970’s, they were used extensively byhardware engineers to replace control logic, registers,gates, and state machines which otherwise would haverequired many discrete, dedicated ICs.

Often these programmable logic devices were one-time factory-programmed parts that were soldered downand never changed after the design went into production.

These programmable logic devices were mostly thedomain of hardware engineers and the software toolswere tailored to meet their needs. You had tools foraccepting boolean equations or even schematics to helpgenerate the interconnect pattern for the growingnumber of gates.

Then, programmable logic vendors started offeringpredefined logic blocks for flip-flops, registers andcounters that gave the engineer a leg up on popularhardware functions.

Nevertheless, the hardware engineer was stillintimately involved with testing and evaluating thedesign using the same skills he needed for testingdiscrete logic designs. He had to worry about propaga-tion delays, loading, clocking and synchronizing—alltricky problems that usually had to be solved the hardway—with oscilloscopes or logic analyzers.

� Used primarily to replace discrete digital

hardware circuitry for:

� Control logic

� Glue logic

� Registers and gates

� State machines

� Counters and dividers

� Devices were selected by hardware engineers

� Programmed functions were seldom changed

after the design went into production

� Tools were oriented to hardware engineers

� Schematic processors

� Boolean processors

� Gates, registers, counters, multipliers

� Successful designs required high-level

hardware engineering skills for:

� Critical paths and propagation delays

� Pin assignment and pin locking

� Signal loading and drive capabilities

� Clock distribution

� Input signal synchronization and skew analysis


1717171717



FPGAs: New Device TFPGAs: New Device TFPGAs: New Device TFPGAs: New Device TFPGAs: New Device Technologyechnologyechnologyechnologyechnology FPGAs: New Development TFPGAs: New Development TFPGAs: New Development TFPGAs: New Development TFPGAs: New Development Toolsoolsoolsoolsools

Figure 20 Figure 21

� High Level Design Tools

� Block Diagram System Generators

� Schematic Processors

� High-level language compilers for

VHDL & Verilog

� Advanced simulation tools for modeling speed,

propagation delays, skew and board layout

� Faster compilers and simulators save time

� Graphically-oriented debugging tools

� IP (Intellectual Property) Cores

� FPGA vendors offer both free and licensed cores

� FPGA vendors promote third party core vendors

� Wide range of IP cores available

� 500+ MHz DSP slices and memory structures

Over 3500 dedicated on-chip hardware multipliers

On-board GHz serial transceivers

Partial reconfigurability maintains

operation during changes

Switched fabric interface engines

Over 690,000 logic cells

Gigabit Ethernet media access controllers

On-chip 405 PowerPC RISC microcontroller cores

Memory densities approaching 85 million bits

Reduced power with core voltages at 1 volt

Silicon geometries to 28 nanometers

High-density BGA and flip-chip packaging

Over 1200 user I/O pins

Configurable logic and I/O interface standards

�

�

�

�

�

�

�

�

�

�

�

�

�

It’s virtually impossible to keep up to date on FPGAtechnology, since new advancements are being madeevery day.

The hottest features are processor cores inside thechip, computation clocks to 500 MHz and above, andlower core voltages to keep power and heat down.

Several years ago, dedicated hardware multipliersstarted appearing and now you’ll find literally thousandsof them on-chip as part of the DSP initiative launchedby virtually all FPGA vendors.

High memory densities coupled with very flexiblememory structures meet a wide range of data flowstrategies. Logic slices with the equivalent of over tenmillion gates result from silicon geometries shrinkingbelow 0.1 micron.

BGA and flip-chip packages provide plenty of I/Opins to support on-board gigabit serial transceivers andother user-configurable system interfaces.

New announcements seem to be coming out everyday from chip vendors like Xilinx and Altera in a never-ending game of outperforming the competition.

To support such powerful devices, new design toolsare appearing that now open up FPGAs to both hard-ware and software engineers. Instead of just acceptinglogic equations and schematics, these new tools acceptentire block diagrams as well as VHDL and Verilogdefinitions.

Choosing the best FPGA vendor often hingesheavily on the quality of the design tools available tosupport the parts.

Excellent simulation and modeling tools help toquickly analyze worst case propagation delays andsuggest alternate routing strategies to minimize themwithin the part. This minimizes some of the trickytiming work for hardware engineers and can save onehours of tedious troubleshooting during design verifica-tion and production testing.

In the last few years, a new industry of third partyIP (Intellectual Property) core vendors now offer thou-sands of application-specific algorithms. These are readyto drop into the FPGA design process to help beat thetime-to-market crunch and to minimize risk.


1818181818



FPGA RFPGA RFPGA RFPGA RFPGA Resource Comparisonesource Comparisonesource Comparisonesource Comparisonesource Comparison

Figure 22

The above chart compares the available resources inthe five Xilinx FPGA families that are used or have beenused in most of Pentek products.

● Virtex-II Pro: VP● Virtex-4: FX, LX and SX● Virtex-5: LX and SX● Virtex-6: LX and SX● Virtex-7: VX

The Virtex-II family includes hardware multipliersthat support digital filters, averagers, demodulatorsand FFTs—a major benefit for software radio signalprocessing. The Virtex-II Pro family dramaticallyincreased the number of hardware multipliers and alsoadded embedded PowerPC microcontrollers.

The Virtex-4 family is offered as three subfamiliesthat dramatically boost clock speeds and reduce powerdissipation over previous generations.

The Virtex-4 LX family delivers maximum logic andI/O pins while the SX family boasts of 512 DSP slicesfor maximum DSP performance. The FX family is agenerous mix of all resources and is the only family tooffer RocketIO, PowerPC cores, and the newly addedgigabit Ethenet ports.

*Virtex-II Pro and Virtex-4 Slices actually represent 2.25 Logic Cells;*Virtex-5, Virtex-6 and Virtex-7 Slices actually represent 6.4 Logic Cells

VirVirVirVirVirtex-II Ptex-II Ptex-II Ptex-II Ptex-II Prororororo VirVirVirVirVirtex-4tex-4tex-4tex-4tex-4 VirVirVirVirVirtex-5tex-5tex-5tex-5tex-5 VirVirVirVirVirtex-6tex-6tex-6tex-6tex-6 VirVirVirVirVirtex-7tex-7tex-7tex-7tex-7VPVPVPVPVP FX, LX, SXFX, LX, SXFX, LX, SXFX, LX, SXFX, LX, SX LX, SXLX, SXLX, SXLX, SXLX, SX LX, SXLX, SXLX, SXLX, SXLX, SX VXVXVXVXVX

Logic Cells 53K–74K 55K–110K 52K–155K 128K–314K 326K–693KSlices* 23K–33K 24K–49K 8K–24K 20K–49K 51K–108KCLB Flip-Flops 46K–66K 48K–98K 32K–96K 160K–392K 408K–864KBlock RAM (kb) 4,176–5,904 4,176–6,768 4,752–8,784 9,504–25,344 27,000–52,920DSP Hard IP 18x18 Multipliers DSP48 DSP48E DSP48E DSP48EDSP Slices 232–328 96–512 128–640 480–1,344 1,120–3,600Serial Gbit Transceivers N/A 0–20 12–16 20–24 28–80PCI Express Support N/A N/A N/A Gen 2 x8 Gen 2 x8, Gen 3 x8User I/O 852–996 576–960 480–680 600–720 700–1,000

The Virtex-5 family LX devices offer maximumlogic resources, gigabit serial transceivers, and Ethernetmedia access controllers. The SX devices push DSPcapabilities with all of the same extras as the LX.

The Virtex-5 devices offer lower power dissipation,faster clock speeds and enhanced logic slices. They alsoimprove the clocking features to handle faster memoryand gigabit interfaces. They support faster single-endedand differential parallel I/O buses to handle fasterperipheral devices.

The Virtex-6 and Virtex-7 devices offer still higherdensity, more processing power, lower power consump-tion, and updated interface features to match the latesttechnology I/O requirements including PCI Express.Virtex-6 supports PCIe 2.0 and Virtex-7 supports PCIe 3.0

The ample DSP slices are responsible for themajority of the processing power of the Virtex-6 andVirtex-7 families. Increases in operating speed from 500 MHzin V-4, to 550 MHz in V-5, to 600 MHz in V-6, to900 MHz in V-7 and continuously increasing densityallow more DSP slices to be included in the same-sizepackage. As shown in the chart, Virtex-6 tops out at animpressive 1,344 DSP slices, while Virtex-7 tops out atan even more impressive 3,600 DSP slices.


1919191919


� Allows FPGA design engineers to easily add

functions to standard factory configuration

� Includes VHDL source code for all standard functions:

� Control and status registers

� A/D and Digital receiver interfaces

� Mezzanine interfaces

� Triggering, clocking, sync and gating functions

� Data packing and formatting

� Channel selection

� A/D / Receiver multiplexing

� Interrupt generation

� Data tagging and channel ID

� User Block for inserting custom code


Figure 23 Figure 24

GateFlow FPGA Design RGateFlow FPGA Design RGateFlow FPGA Design RGateFlow FPGA Design RGateFlow FPGA Design Resourcesesourcesesourcesesourcesesources GateFlow FPGA Design KitGateFlow FPGA Design KitGateFlow FPGA Design KitGateFlow FPGA Design KitGateFlow FPGA Design Kit

If you want to add your own algorithms to Pentekcatalog products, we offer the GateFlow FPGA DesignKit that includes VHDL source code for all the standardfactory functions.

VHDL is one of the most popular languages usedin the FPGA design tools. The GateFlow Design Kitincludes the VHDL source code for every softwaremodule we use to create these standard factory featuresof the product.

The standard factory configuration supports a widerange of operating modes, timing and sync functions, aswell as several different data formatting options.

This includes control and status registers, peripheralinterfaces, mezzanine interfaces, timing functions, dataformatting, channel selection, interrupt support, anddata tagging.

These are also fully supported with our ReadyFlowBoard Support Package.

We also include a special User Block, positionedright in the data stream, so you can easily drop in yourown custom signal processing algorithms.

GateFlow® is Pentek’s flagship collection of FPGADesign Resources. The GateFlow line is compatiblewith the Xilinx Virtex products and is available as twoseparate offerings:

If you want to add your own custom algorithms, weoffer the GateFlow FPGA Design Kit.

We also offer popular high-performance signal-process-ing algorithms with the GateFlow factory-installed IPCores. These algorithms are designed expressly for XilinxFPGAs and Pentek hardware products

Installed Cores are delivered to you preinstalled inyour Pentek FPGA-based product of choice and are fullysupported with Pentek ReadyFlow® Board SupportPackages.

Let’s start with the GateFlow FPGA Design Kit.

GateFlow

FPGA

Design

Kit

GateFlow

Factory

Installed

IP Cores


2020202020


Figure 25


Front Panel Interface

Memory

Controller

MemoryController

Sync Bus

Interface

PCI Express Interface

Global Registers

FLASH Interface

ClockGenerator

Timestamp

TestGenerator

PCI Express Backend

MemoryController

Memory

Controller

V-6 or V-7-

FPGA

User Application Container

Defined and

documented

interface signals

Board

RegistersUser

Registers

DMAs P14

LVDS

P16

MGTs

Factory Installed

Base Function Application

A/D & D/A Control

Data Packing & Formatting

Meta Data Files

Linked-List A/D Control

Linked-List D/A Control

GateFlow FPGA Design Kit for Cobalt, Onyx and Flexor PGateFlow FPGA Design Kit for Cobalt, Onyx and Flexor PGateFlow FPGA Design Kit for Cobalt, Onyx and Flexor PGateFlow FPGA Design Kit for Cobalt, Onyx and Flexor PGateFlow FPGA Design Kit for Cobalt, Onyx and Flexor Productsroductsroductsroductsroducts

The GateFlow FPGA Design Kit allows the user tomodify, replace and extend the standard factory-installedfunctions in the FPGA to incorporate special modes ofoperation, new control structures, and specialized signal-processing algorithms.

The Cobalt, Onyx and Flexor architectures config-ure the FPGA with standard factory-supplied interfacesincluding memory controllers, DMA engines, A/Dand D/A interfaces, timing and synchronizationstructures, triggering and gating logic, time stampingand header tagging, data formatting engines, and thePCIe interface. These resources are connected to the UserApplication Container using well-defined ports that presenteasy-to-use data and control signals, effectively abstract-ing the lower level details of the hardware.

Shown here is the FPGA block diagram of a typicalCobalt, Onyx or Flexor module. The User ApplicationContainer holds a collection of different factory-installed IPmodules connected to the various interfaces through thestandard ports surrounding the container. The specific IPmodules for each product are described in further detail inthe datasheet of that product.

The GateFlow Design Kit provides a completeXilinx ISE Foundation or Vivado project foldercontaining all the files necessary for the FPGAdeveloper to recompile the entire project with orwithout any required changes. VHDL source code foreach module provides an example of how the IPmodules work, how they might be modified, and howthey might be replaced with custom IP to implement aspecific function.


2121212121


GateFlow FPGA Design Kit for Other GateFlow FPGA Design Kit for Other GateFlow FPGA Design Kit for Other GateFlow FPGA Design Kit for Other GateFlow FPGA Design Kit for Other PPPPPentek entek entek entek entek PPPPProductsroductsroductsroductsroducts

The GateFlow FPGA Design Kit is intended for theprogramming of predefined user blocks located in the dataflow path specifically reserved for custom applications.These predefined blocks protect users from inadvertentlyaltering base functionality.

Pentek recommends user programming be limited tothe predefined user blocks to maintain base functional-ity. However, for more complex requirements, sufficientinformation is supplied in the kit for the user to modify,add to, or replace default board functions if necessary.Default configuration files are included with the DesignKit should it be necessary to restore standard factoryconfiguration.

Shown above is the block diagram of a typicalsoftware radio module. The diagram includes the FPGAand external hardware devices connected to it.

The blocks inside the FPGA are VHDL codemodules that handle the standard factory functions andinterfaces. The User Block is a VHDL module that sitsin the data path with pin definitions for input, output,status, control and clocks.

In the standard Design Kit product, the User Block isconfigured as a straight wire between the input and outputports. By creating a custom algorithm inside the block thatconforms to the pin definition, the user will have a low-riskexperience in recompiling and installing the custom code.Since Pentek provides source code for all the modules,changes outside the user block can also be made by the user.

EXT

CLK

XTAL

OSC

LVDS

CLK &

SYNC

CLOCK

CONTROL

SYNC / GATE /

TRIGGER

GENERATOR

INTERRUPT

GENERATORSTATUS &

CONTROL

A/D

DIGITAL

RECEIVER

ANALOG

INPUT DATA

SELECT

DATA

FORMATTER

CLOCK

& SYNC

DRIVERS

MEZZANINE

INTERFACE

DIGITAL

INPUT

DMA CONTROL

& COUNTERS

FPGA

USER BLOCK

INPUT OUTPUT

STATUSCONTROL

DEFAULT

BYPASS

Figure 26



2222222222


GateFlow Installed IP CoresGateFlow Installed IP CoresGateFlow Installed IP CoresGateFlow Installed IP CoresGateFlow Installed IP Cores

Figure 27

� Pentek Installs IP Cores in Pentek Products

� Cores are tailored and optimized for:

� Specific devices and I/O found on Pentek products

� Efficient FPGA resource utilization

� Execution and throughput speed

� Eliminates need for customer FPGA development

� Fully supported with ReadyFlow Board Support Libraries

Pentek is an AllianceCore Member, a third partyprogram sponsored by Xilinx for companies that special-ize in specific areas of expertise in developing FPGAalgorithms for niche application areas. These includeimage processing, communications, telecom, telemetry,signal intelligence, wireless communications, wirelessnetworking, and many other disciplines.

Pentek offers popular high-performance signalprocessing algorithms installed in Pentek products. Thesealgorithms are designed expressly for Xilinx FPGAs andPentek harware products. The cores take full advantageof the numerous hardware multipliers to achieve highly-parallel processing structures that can dramaticallyoutperform programmable RISC and DSP processors.

Installed Cores are optimized for efficient FPGAresource utilization, execution and throughput speed.They are delivered to you preinstalled in your PentekFPGA-based product of choice and are fully tested andsupported with the Pentek ReadyFlow Board SupportPackages. Purchasing these popular factory-installedcores saves you the time and costs of acquiring FPGAtools and developing custom FPGA code.



2323232323


Figure 28


The Pentek family of board-level software radioproducts is the most comprehensive in the industry. Allof these products are available in several formats tosatisfy a wide range of requirements: 3U and 6U VPX,PMC/XMC, PCI Express, AMC, FMC, 3U and 6UCompactPCI.

Software radio products are supported by clocksynthesizer, synchronizer and distribution boards. Theseproducts are also available in the same formats as thesoftware radio products.

In addition to their commercial versions, many ofthe above products are available in ruggedized versionsup to and including conduction-cooled.

All Pentek software radio products include multiboardsynchronization that facilitates the design of multichannelsystems with synchronous clocking, gating and triggering.

Pentek’s comprehensive software support includesthe ReadyFlow® Board Support Package, the GateFlow®

FPGA Design Kit and high-performance factory-installedIP cores that expand the features and range of manyPentek software radio products. In addition, Pentek high-speed recording systems are supported with SystemFlow®

recording software that features a Windows®-based graphicaluser interface.

In addition to the product overviews presented inthe pages that follow, active links to their datasheets andthe datasheets of similar products on Pentek’s website,are included with each product.

VPX, PMC/XMC, PCI Express, AMC, FMC, and CompactPCIVPX, PMC/XMC, PCI Express, AMC, FMC, and CompactPCIVPX, PMC/XMC, PCI Express, AMC, FMC, and CompactPCIVPX, PMC/XMC, PCI Express, AMC, FMC, and CompactPCIVPX, PMC/XMC, PCI Express, AMC, FMC, and CompactPCISofSofSofSofSoftware Rtware Rtware Rtware Rtware Radio and Supporadio and Supporadio and Supporadio and Supporadio and Supporting Pting Pting Pting Pting Productsroductsroductsroductsroducts

XMC Module

6U CompactPCIBoard

x8 PCI Express Board AMC Board

PMC/XMCModule

FMC I/O Module

FMC Carrier

6U VPXBoard

3U VPX BoardsCOTS and Rugged


2424242424


GSM Channelizer

Cobalt & Onyx 3U VPX Models

Co

balt

On

yx

DDC Interp Sum

Adaptive Relay

200 MHz / 16-bit3 800 MHz / 16-bit252x20

400 MHz / 14-bit2

# Type

A/D Converters

# Type

D/A Converters

Type

IP or Other I/OModel

3.6 GHz / 12-bit1.8 GHz / 12-bit

200 MHz / 16-bit3

200 MHz / 16-bit3

200 MHz / 16-bit4

800 MHz / 16-bit2

800 MHz / 16-bit2

52x21

52x24

52x60

52x61 200 MHz / 16-bit4 DDC Sum

52x62 200 MHz / 16-bit4 DDC

52x63 200 MHz / 16-bit4

52x64 200 MHz / 16-bit4 DDC VITA-49

52x90 200 MHz / 16-bit2

52x50-014 800 MHz / 16-bit2

52x50 500 MHz / 12-bit2 800 MHz / 16-bit2

400 MHz / 14-bit252x51-014 800 MHz / 16-bit2 DDC Interp Sum

52x51 500 MHz / 12-bit2 800 MHz / 16-bit2 DDC Interp Sum

52x30 1 GHz / 12-bit1 1 GHz / 16-bit1

52x40 12

52x41 3.6 GHz / 12-bit1.8 GHz / 12-bit

12 DDC

52x70

52x71

52x10

52x11

1.25 GHz / 16-bit4

1.25 GHz / 16-bit4 Interp

32 pair LVDS I/O

Quad Serial FPDP

.925 – 2.175 GHz L-Band Tuner

Figure 29



2525252525



Figure 30 Figure 31

VPX FVPX FVPX FVPX FVPX Families for Cobalt Pamilies for Cobalt Pamilies for Cobalt Pamilies for Cobalt Pamilies for Cobalt Productsroductsroductsroductsroducts VPX FVPX FVPX FVPX FVPX Families for Onyx Pamilies for Onyx Pamilies for Onyx Pamilies for Onyx Pamilies for Onyx Productsroductsroductsroductsroducts

VPX Family Comparison

52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8

on VPX P1 on VPX P1 or P2

20 pairs on VPX P2

Yes

PCIe width x4 x8

Lowest Price

Two x4 or one x8

No

Yes No

VPX Family Comparison

52xxx

Form Factor

One XMC

3U VPX

# of XMCs

Crossbar Switch

PCIe path

Option -105 path

Option -104 path

Lowest Power

53xxx

No Yes

VPX P1 VPX P1 or P2

Two x4 or one x8

on VPX P1 on VPX P1 or P2

Yes

PCIe width x4 x4 or x8

20 pairs on VPXP224 pairs on VPXP2

Lowest Price

Two x4 or one x8

No

Yes No

Pentek offers two families of Onyx® 3U VPXproducts: the 52xxx and the 53xxx. For more informationon a 52xxx or a 53xxx product, please refer to the productdescriptions in the pages that follow. The table aboveprovides a comparison of the main features of the families.

Onyx products utilize the Xilinx Virtex-7 FPGA.

Pentek offers two families of Cobalt® 3U VPXproducts: the 52xxx and the 53xxx. For more informationon a 52xxx or a 53xxx product, please refer to the productdescriptions in the pages that follow. The table aboveprovides a comparison of the main features of the families.

Cobalt products utilize the Xilinx Virtex-6 FPGA.


2626262626


Model 52620 3U VPXCOTS and rugged

Figure 32

3-3-3-3-3-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 200 MHz A/D, DUC, 2-Channel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, VirChannel 800 MHz D/A, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 52620, 53620 3U VPX Models 52620, 53620 3U VPX Models 52620, 53620 3U VPX Models 52620, 53620 3U VPX Models 52620, 53620 3U VPX ●●●●● Models 57620, 58620 6U VPX Models 57620, 58620 6U VPX Models 57620, 58620 6U VPX Models 57620, 58620 6U VPX Models 57620, 58620 6U VPX ● ● ● ● ● Model 71620 XMC Model 71620 XMC Model 71620 XMC Model 71620 XMC Model 71620 XMC ●●●●● Model 78620 PCIe Model 78620 PCIe Model 78620 PCIe Model 78620 PCIe Model 78620 PCIeModel 56620 AMC Model 56620 AMC Model 56620 AMC Model 56620 AMC Model 56620 AMC ● ● ● ● ● Models 72620, 74620 6U cPCI Models 72620, 74620 6U cPCI Models 72620, 74620 6U cPCI Models 72620, 74620 6U cPCI Models 72620, 74620 6U cPCI ● ● ● ● ● Model 73620 3U cPCIModel 73620 3U cPCIModel 73620 3U cPCIModel 73620 3U cPCIModel 73620 3U cPCI

Model 52620 is a member of the Cobalt family ofhigh-performance 3U VPX modules based on the XilinxVirtex-6 FPGA. A multichannel, high-speed dataconverter, it is suitable for connection to HF or IF portsof a communications or radar system. Its built-in datacapture and playback features offer an ideal turnkey solution.It includes three 200 MHz, 16-bit A/Ds, a DUC withtwo 800 MHz, 16-bit D/As and four banks of memory.In addition to supporting PCI Express Gen. 2 as anative interface, the Model 52620 includes generalpurpose and gigabit serial connectors for application-specific I/O .

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths are acces-sible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, data packing,gating, triggering and memory control. The Cobalt architec-ture organizes the FPGA as a container for data processingapplications where each function exists as an intellec-tual property (IP) module.

Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The 52620 factory-installedfunctions include an A/D acquisition and a D/A waveformplayback IP modules. In addition, IP modules for eitherDDR3 or QDRII+ memories, a controller for all dataclocking and synchronization functions, a test signalgenerator and a PCIe interface complete the factory-installed functions.

Multiple 52620’s can be driven from the LVPECLbus master, supporting synchronous sampling and syncfunctions across all connected modules. The architecturesupports up to four memory banks which can be configuredwith all QDRII+ SRAM, DDR3 SDRAM, or combinations.

Versions of the 52620 are available as another 3U VPX(Model 53620), 6U VPX (Models 57620 and 58620 dualdensity), XMC module (Model 71620), x8 PCIe (Model78620), AMC (Model 56620), 6U cPCI (Models 72620and 74620 dual density), and 3U cPCI (Model 73620).

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS

VCXO

200 MHz16-BIT A/D

RFXFORMR

RFXFORMR

VIRTEX-6 FPGA

LX130T, LX240T or SX315T

16

QDRII+SRAM8 MB

TTL Gate / TrigTTL Sync / PPS

Sample ClkReset

Gate A/DGate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

200 MHz16-BIT A/D

Sample Clk /Reference Clk In

800 MHz16-BIT D/A

RFXFORMR

321616

RFXFORMR

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RFXFORMR

200 MHz16-BIT A/D

16

Memory Banks 1 & 2 Memory Banks 3 & 4

DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In RF In RF In RF OutRF Out

D/AClock/Sync

Bus

A/DClock/Sync

Bus

RFXFORMR

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

GigabitSerial I/O

VPX-P1

Option -105

4X4X 4X

x4PCIe


http://pentek.com/products/Detail.cfm?Model=52620











2727272727



Figure 33


Models 5Models 5Models 5Models 5Models 5373737373720, 520, 520, 520, 520, 5272727272720 3U VPX 20 3U VPX 20 3U VPX 20 3U VPX 20 3U VPX ●●●●● Models 57 Models 57 Models 57 Models 57 Models 577777720, 5820, 5820, 5820, 5820, 587777720 6U VPX20 6U VPX20 6U VPX20 6U VPX20 6U VPX ● ● ● ● ● Model 71Model 71Model 71Model 71Model 717777720 XMC 20 XMC 20 XMC 20 XMC 20 XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 787777720 PCIe20 PCIe20 PCIe20 PCIe20 PCIeModel 56720 AMC Model 56720 AMC Model 56720 AMC Model 56720 AMC Model 56720 AMC ● ● ● ● ● Models 72720, 74720 6U cPCI Models 72720, 74720 6U cPCI Models 72720, 74720 6U cPCI Models 72720, 74720 6U cPCI Models 72720, 74720 6U cPCI ● ● ● ● ● Model 73720 3U cPCIModel 73720 3U cPCIModel 73720 3U cPCIModel 73720 3U cPCIModel 73720 3U cPCI

Model 53720 is a member of the Onyx family ofhigh-performance 3U VPX modules based on the XilinxVirtex-7 FPGA. A multichannel, high-speed data converter,it is suitable for connection to HF or IF ports of acommunications or radar system. Its built-in datacapture and playback features offer an ideal turnkeysolution. It includes three 200 MHz, 16-bit A/Ds, a DUCwith two 800 MHz, 16-bit D/As and four banks ofmemory. In addition to supporting PCI Express Gen. 3 asa native interface, the Model 53720 includes general-purpose and gigabit-serial connectors for application-specific I/O.

The Pentek Onyx architecture features a Virtex-7FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installedfunctions including data multiplexing, channel selection,data packing, gating, triggering and memory control. TheOnyx architecture organizes the FPGA as a container fordata processing applications where each function existsas an intellectual property (IP) module.

Each member of the Onyx family is delivered withfactory-installed applications ideally matched to the board’sanalog interfaces. The 53720 factory-installed functionsinclude three A/D acquisition and a D/A waveformplayback IP modules for simplifying data capture anddata transfer. IP modules for DDR3 SDRAM memories, acontroller for all data clocking and synchronization functions, atest signal generator, and a PCIe interface complete thefactory-installed functions.

Multiple 53720’s can be driven from the LVPECLbus master, supporting synchronous sampling and sync.

Versions of the 53720 are also available as another 3UVPX (Model 52720), 6U VPX (Models 57720 and58720 dual density), XMC (Model 71720), x8 PCIeboard (Model 78720), AMC (Model 56720), 6U cPCI(Models 72720 and 74720 dual density), and 3U cPCI(Model 73620).

GateXpress® is a configuration manager for loadingand reloading the Virtex-7 FPGA. More in the next page.

TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RFXFORMR

RFXFORMR


Sample ClkReset

Gate A/DGate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

200 MHz16-BIT A/D


800 MHz16-BIT D/A

RFXFORMR

321616

RFXFORMR

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

RFXFORMR

200 MHz16-BIT A/D

16

RF In RF In RF In RF OutRF Out

D/AClock/Sync

Bus

A/DClock/Sync

Bus

RFXFORMR

LVDS

40

Option -104FPGAI/O

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X4X

VIRTEX-7 FPGA

VX330T or VX690T

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

PCIeGen. 2 x8

CONFIGFLASH1 GB

PCIeGen. 2x8

FPGAConfigBus

GATEXPRESS PCIeCONFIGURATION

MANAGER













2828282828


Figure 34

GateXpress for FPGAGateXpress for FPGAGateXpress for FPGAGateXpress for FPGAGateXpress for FPGA-PCIe Configuration Management-PCIe Configuration Management-PCIe Configuration Management-PCIe Configuration Management-PCIe Configuration Management

ONYX: VIRTEX-7 FPGA

VX330T or VX690T

40 Cobalt48 Onyx

4X

GTX

4X8X

GTX LVDS

Option-104FPGAGPIO

Option-105SerialI/O

P14PMC

P16XMC

GTX

P15XMC

CONFIGFLASH1 GB

PCIe

FPGAConfigBus


MANAGER

32 32 32 32

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

The Onyx architecture includes GateXpress, a sophisti-cated FPGA-PCIe configuration manager for loading andreloading the FPGA. At power up, GateXpress immediatelypresents a PCIe target for the host computer to discover,effectively giving the FPGA time to load from FLASH.This is especially important for larger FPGAs where theloading times can exceed the PCIe discovery window,typically 100 msec on most PCs.

The board’s configuration FLASH can hold fourFPGA images. Images can be factory-installed IP orcustom IP created by the user, and programmed into theFLASH via JTAG using Xilinx iMPACT or through theboard’s PCIe interface. At power up the user can choosewhich image will load based on a hardware switch setting.

Once booted, GateXpress allows the user threeoptions for dynamically reconfiguring the FPGA with anew IP image. The first is the option to load an alternateimage from FLASH through software control. The userselects the desired image and issues a reload command.

The second option is for applications where theFPGA image must be loaded directly through the PCIeinterface. This is important in security situations wherethere can be no latent user image left in nonvolatilememory when power is removed. In applications wherethe FPGA IP may need to change many times duringthe course of a mission, images can be stored on the hostcomputer and loaded through PCIe as needed.

The third option, typically used during development,allows the user to directly load the FPGA through JTAGusing Xilinx iMPACT.

In all three FPGA loading scenarios, GateXpresshandles the hardware negotiation simplifying and stream-lining the loading task. In addition, GateXpress preservesthe PCIe configuration space allowing dynamic FPGAreconfiguration without needing to reset the hostcomputer to rediscover the board. After the reload, thehost simply continues to see the board with the expecteddevice ID.



2929292929


Models 52624, 53624 3U VPX Models 52624, 53624 3U VPX Models 52624, 53624 3U VPX Models 52624, 53624 3U VPX Models 52624, 53624 3U VPX ● ● ● ● ● Models 57624, 58624 6U VPX Models 57624, 58624 6U VPX Models 57624, 58624 6U VPX Models 57624, 58624 6U VPX Models 57624, 58624 6U VPX ●●●●● Model 71624 XMC Model 71624 XMC Model 71624 XMC Model 71624 XMC Model 71624 XMC ● ● ● ● ● Model 78624 PCIe Model 78624 PCIe Model 78624 PCIe Model 78624 PCIe Model 78624 PCIe Model 56624 AMC Model 56624 AMC Model 56624 AMC Model 56624 AMC Model 56624 AMC ●●●●● ModelModelModelModelModelsssss 72 72 72 72 72724, 724, 724, 724, 724, 7474747474624624624624624 6U cPCI 6U cPCI 6U cPCI 6U cPCI 6U cPCI ●●●●● Model 73Model 73Model 73Model 73Model 73624624624624624 3U cPCI 3U cPCI 3U cPCI 3U cPCI 3U cPCI

Dual-Dual-Dual-Dual-Dual-Channel 34-Signal Adaptive IF RChannel 34-Signal Adaptive IF RChannel 34-Signal Adaptive IF RChannel 34-Signal Adaptive IF RChannel 34-Signal Adaptive IF Relayelayelayelayelay, Installed IP Cores, Vir, Installed IP Cores, Vir, Installed IP Cores, Vir, Installed IP Cores, Vir, Installed IP Cores, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 52624 is a member of the Cobalt family ofhigh-performance 3U VPX boards based on the XilinxVirtex-6 FPGA. As an IF relay, it accepts two IF analoginput channels, modifies up to 34 signals, and then deliversthem to two analog IF outputs. Any signal within eachIF band can be independently enabled or disabled,and changed in both frequency and amplitude as it passesthrough the board.

The 52624 supports many useful functions for bothcommercial and military communications systems includingsignal drop/add/replace, frequency shifting and hopping,amplitude equalization, and bandwidth consolidation.Applications include countermeasures, active tracking andmonitoring, channel security, interception, adaptive spectralmanagement, jamming, and encryption.

The Pentek Cobalt product family features the Virtex-6FPGA. All of the board’s data converters, interfaces andcontrol lines are connected to the FPGA, which performsthe data-routing and DSP functions for the adaptive relay.

A PCIe Gen 1 system interface supports control, statusand data transfers.

The Model 52624 digitizes two analog IF inputsusing two 200 MHz 16-bit A/D converters. The band-width of each IF signal can be up to 80 MHz, and maycontain multiple signals, each centered at a differentfrequency. An array of 34 DDCs can be independentlyprogrammed to translate any signal to baseband andthen bandlimit the signal as required. DDC tuning frequencyis programmable from 0 Hz to the A/D sample rate. Outputbandwidth is programmable from around 20 kHz to 312 kHzfor a sample rate of 200 MHz. Each DDC can indepen-dently source IF data from either of the two A/Ds.

Versions of the 52624 are also available as a different3U VPX (Model 53624), 6U VPX (Models 57624 and58624 dual density), XMC module (Model 71624), anx8 PCIe board (Model 78624), AMC (Model 56624), 6UcPCI (Models 72624 and 74624 dual density), and 3U cPCI(Model 73624).

800 MHz16-BIT

D/A

IF 1Out

INTERPX4

TIMING BUSGENERATOR

Triggering/Clock / Sync /Gate / PPS VCXO

200 MHz16-BIT

A/D

INPUTGAIN 1


Gate A/DGate D/A

Sync / PPS A/DSync / PPS D/A


A/DClock/Sync Bus

IF 1In

DDC1

OUTPUTGAIN 1

DUC1

INP

UT

MU

LTIP

LEX

ER

INPUTGAIN 2

DDC2

OUTPUTGAIN 2

DUC2

INPUTGAIN 3

DDC3

OUTPUTGAIN 3

DUC3

INPUTGAIN 34

DDC34

OUTPUTGAIN 34

DUC34

OU

TP

UT

MU

LTIP

LEX

ER

200 MHz16-BIT

A/D

IF 2In

SU

MM

AT

ION

1S

UM

MA

TIO

N2

800 MHz16-BIT

D/A

IF 2Out

INTERPX4

TRANSMIT DMACONTROLLER

RECEIVE DMACONTROLLER

PCIeINTERFACE

STATUS &CONTROL

To AllSections

D/AClock/Sync Bus

VPX BACKPLANE

VPX-P1

PCIeGen. 1 x8


Figure 35























3030303030


Figure 36

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS D/A Clock/Sync Bus

VCXO

16

QDRII+SRAM8 MB

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16 1616 16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

1 GHz12-BIT A/D

12

Memory Banks 1 & 2 Memory Banks 3 & 4DDR3 option 155 DDR3 option 165

Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2 VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe

1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Vir1 GHz A/D, 1 GHz D/A, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 52630, 53630 3U VPX Model 52630, 53630 3U VPX Model 52630, 53630 3U VPX Model 52630, 53630 3U VPX Model 52630, 53630 3U VPX ●●●●● Model 57630, 58630 6U VPX Model 57630, 58630 6U VPX Model 57630, 58630 6U VPX Model 57630, 58630 6U VPX Model 57630, 58630 6U VPX ● ● ● ● ● Model 71630 XMC Model 71630 XMC Model 71630 XMC Model 71630 XMC Model 71630 XMC ●●●●● Model 78630 PCIe Model 78630 PCIe Model 78630 PCIe Model 78630 PCIe Model 78630 PCIeModel 56630 AMC Model 56630 AMC Model 56630 AMC Model 56630 AMC Model 56630 AMC ●●●●● Models 72630, 74630 6U cPCI Models 72630, 74630 6U cPCI Models 72630, 74630 6U cPCI Models 72630, 74630 6U cPCI Models 72630, 74630 6U cPCI ● ● ● ● ● Model 73630 3U cPCIModel 73630 3U cPCIModel 73630 3U cPCIModel 73630 3U cPCIModel 73630 3U cPCI

Model 52630 is a member of the Cobalt family of high-performance 3U VPX boards based on the Xilinx Virtex-6FPGA. A high-speed data converter, it is suitable forconnection to HF or IF ports of a communications or radarsystem. Its built-in data capture and playback features offeran ideal turnkey solution as well as a platform for develop-ing and deploying custom FPGA processing IP. It includes1 GHz, 12-bit A/D, 1 GHz, 16-bit D/A converters andfour banks of memory. In addition to supporting PCIExpress Gen. 2 as a native interface, the Model 52630includes optional general purpose and gigabit serial cardconnectors for application- specific I/O protocols.

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths are acces-sible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, data packing,gating, triggering and memory control. The Cobalt architec-ture organizes the FPGA as a container for data process-ing applications where each function exists as an intellec-tual property (IP) module.

Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The 52630 factory-installedfunctions include an A/D acquisition and a D/A waveformplayback IP module. In addition, IP modules for eitherDDR3 or QDRII+ memories, a controller for all dataclocking and synchronization functions, a test signalgenerator and a PCIe interface complete the factory-installed functions.

Multiple 52630’s can be driven from the LVPECL busmaster, supporting synchronous sampling and sync functionsacross all connected boards. The architecture supports up tofour memory banks which can be configured with allQDRII+ SRAM, DDR3 SDRAM, or as combinations.

Versions of the 52630 are available as a different 3UVPX (Model 53630), 6U VPX (Models 57630 and58630 dual density), XMC (Model 71630), x8 PCIeModel 78630) AMC (Model 56630), 6U cPCI (Models72630 and 74630 dual density), and 3U cPCI (Model 73630).
























3131313131


TTTTTwo 1 GHz A/Ds, Two 1 GHz A/Ds, Two 1 GHz A/Ds, Two 1 GHz A/Ds, Two 1 GHz A/Ds, Two 1 GHz D/As, Two 1 GHz D/As, Two 1 GHz D/As, Two 1 GHz D/As, Two 1 GHz D/As, Two Virwo Virwo Virwo Virwo Virtex-7 FPGAstex-7 FPGAstex-7 FPGAstex-7 FPGAstex-7 FPGAs

Model 5Model 5Model 5Model 5Model 588888730, 5730, 5730, 5730, 5730, 5777777777730 6U VPX30 6U VPX30 6U VPX30 6U VPX30 6U VPX ●●●●● Model 52730, 53730 3U VPX Model 52730, 53730 3U VPX Model 52730, 53730 3U VPX Model 52730, 53730 3U VPX Model 52730, 53730 3U VPX ●●●●● Model 71730 XMC Model 71730 XMC Model 71730 XMC Model 71730 XMC Model 71730 XMC ●●●●● Model 78730 PCIe Model 78730 PCIe Model 78730 PCIe Model 78730 PCIe Model 78730 PCIeModel 56730 AMC Model 56730 AMC Model 56730 AMC Model 56730 AMC Model 56730 AMC ●●●●● Model 72730, 74730 6U cPCI Model 72730, 74730 6U cPCI Model 72730, 74730 6U cPCI Model 72730, 74730 6U cPCI Model 72730, 74730 6U cPCI ● ● ● ● ● Model 73730 3U cPCIModel 73730 3U cPCIModel 73730 3U cPCIModel 73730 3U cPCIModel 73730 3U cPCI

Model 58730 is a member of the Onyx family ofhigh-performance 6U VPX boards based on the XilinxVirtex-7 FPGAs. A high-speed data converter, it issuitable for connection to HF or IF ports of a communi-cations or radar system. Its built-in data capture and playbackfeatures offer an ideal turnkey solution as well as a platformfor developing and deploying custom FPGA processingIP. It includes two 1 GHz A/Ds, two 1 GHz D/A convert-ers and eight banks of memory. In addition to support-ing PCI Express Gen. 3 as a native interface, the Model58730 includes optional general purpose and gigabitserial connectors for application-specific I/O.

The Pentek Onyx architecture features two Virtex-7FPGAs. All of the board’s data and control paths areaccessible by the FPGAs, enabling factory-installedfunctions including data multiplexing, channel selection,data packing, gating, triggering and memory control. TheOnyx architecture organizes the FPGA as a container fordata-processing applications where each function existsas an intellectual property (IP) module.

Each member of the Onyx family is delivered withfactory-installed applications ideally matched to theboard’s analog interfaces. The 58730 factory-installedfunctions include two A/D acquisition and two D/Awaveform playback IP modules for simplifying datacapture and data transfer. IP modules for DDR3 SDRAMmemories, controllers for all data clocking and synchroniza-tion functions, test signal generators and a PCIe interfacecomplete the factory-installed functions and enable the58730 to operate without the need to develop any FPGA IP.

The front end accepts analog HF or IF inputs on frontpanel SSMC connectors with transformer coupling into TIADS5400 1 GHz, 12-bit A/D converters. The digital outputsare delivered into the Virtex-7 FPGAs for signal processing, etc.

Versions of the 58730 are available as 6U VPX (Model57730 single density), 3U VPX (Models 52730 and53730), XMC (Model 71630), x8 PCIe (Model 78730),AMC (Model 56730), 6U cPCI (Models 72730 and74730 with dual density), and 3U cPCI (Model 73730).

Figure 37See page 28

Model 587306U VPX

dual density

LVDS

48

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

VIRTEX-7 FPGA

VX330T or VX690T

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

GTXGTXGTX

PCIeGen. 3 x8

4X4X

PCIeGen. 3 x8

CONFIGFLASH1 GB

PCIeGen. 3x8

FPGAConfigBus


MANAGER

VPX-P2VPX-P1

PCIe-to PCIeSWITCH

From/ToOther XMCModule ofModel 58730

Option -105Gigabit Serial I/O

Block Diagram, Model 57730.

Model 58730 doubles all resources

except the PCIe-to-PCIe Switch and

provides 24 LVDS pairs from the

2nd FPGA to VPX-P5

TIMING BUSGENERATOR

Clock / Sync /Gate / PPS D/A Clock/Sync Bus

VCXO

Gate InSync In

A/D Sync Bus


A/D Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

RF In

RFXFORMR

1 GHz12-BIT A/D

12Gate InSync In

D/A Sync Bus

1 GHz16-BIT D/A

TTLPPS/Gate/Sync













3232323232


Figure 38

TIMING BUSGENERATOR


32

Gate In

Reset In

Sync Bus

Sample Clk

A/D Clock/Sync Bus

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

3.6 GHz (1 Channel)or

1.8 GHz (2 Channel)12-Bit A/D

12


TTLPPS/Gate/Sync

RF In

RFXFORMR

Ref Clk In

Ref Clk Out 12

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

VIRTEX-6 FPGA


1-1-1-1-1-Channel 3.6 GHz and 2-Channel 3.6 GHz and 2-Channel 3.6 GHz and 2-Channel 3.6 GHz and 2-Channel 3.6 GHz and 2-Channel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, VirChannel 1.8 GHz, 12-bit A/D, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Model 53640 is a member of the Cobalt family ofhigh-performance 3U VPX boards based on the XilinxVirtex-6 FPGA. It consists of one Model 71640 XMCmodule mounted on a 3U VPX carrier board. This modelincludes one 3.6 GHz, 12-bit A/D converter and fourbanks of memory.

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, datapacking, gating, triggering and memory control. TheCobalt architecture organizes the FPGA as a container fordata-processing applications where each function exists asan intellectual property (IP) module.

Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The factory-installed functions ofthis model include one A/D acquisition IP module. In

addition, IP modules for DDR3 memories, controllers forall data clocking and synchronization functions, a testsignal generator and a PCIe interface complete thefactory-installed functions.

The front end accepts analog HF or IF inputs onfront panel SSMC connector with transformer-couplinginto a Texas Instruments ADC12D1800 12-bit A/D. Theconverter operates in single-channel interleaved mode witha sampling rate of 3.6 GHz and an input bandwidth of1.75 GHz; or, in dual-channel mode with a sampling rateof 1.8 GHz and input bandwidth of 2.8 GHz. TheADC12D1800 provides a programmable 15-bit gainadjustment allowing an input range of +2 to +4 dBm.

Versions of the 53640 are available as a different3U VPX (Model 52640), 6U VPX (Models 57640 and58640 dual density), XMC module (Model 71640),x8 PCIe (Model 78640), AMC (Model 56640), 6U cPCI(Models 72640 and 74640 dual density), and 3U cPCI (Model73640).

Models 5Models 5Models 5Models 5Models 533333640, 5640, 5640, 5640, 5640, 522222640 3U VPX 640 3U VPX 640 3U VPX 640 3U VPX 640 3U VPX ●●●●● Models 57640,Models 57640,Models 57640,Models 57640,Models 57640, 58640 6U VPX 58640 6U VPX 58640 6U VPX 58640 6U VPX 58640 6U VPX ●●●●● Model 71640 XMC Model 71640 XMC Model 71640 XMC Model 71640 XMC Model 71640 XMC ●●●●● Model 78640 PCIe Model 78640 PCIe Model 78640 PCIe Model 78640 PCIe Model 78640 PCIeModel 56640 AMC Model 56640 AMC Model 56640 AMC Model 56640 AMC Model 56640 AMC ●●●●● Models 72640, 74640 6U cPCI Models 72640, 74640 6U cPCI Models 72640, 74640 6U cPCI Models 72640, 74640 6U cPCI Models 72640, 74640 6U cPCI ● ● ● ● ● Model 73640 3U cPCIModel 73640 3U cPCIModel 73640 3U cPCIModel 73640 3U cPCIModel 73640 3U cPCI














3333333333


Figure 39


Model 52650, 53650 3U VPX Model 52650, 53650 3U VPX Model 52650, 53650 3U VPX Model 52650, 53650 3U VPX Model 52650, 53650 3U VPX ●●●●● Models 57650, 58650 6U VPX Models 57650, 58650 6U VPX Models 57650, 58650 6U VPX Models 57650, 58650 6U VPX Models 57650, 58650 6U VPX ●●●●● Model 71650 XMC Model 71650 XMC Model 71650 XMC Model 71650 XMC Model 71650 XMC ●●●●● Model Model Model Model Model 7865078650786507865078650 PCIe PCIe PCIe PCIe PCIeModel 56650 AMC Model 56650 AMC Model 56650 AMC Model 56650 AMC Model 56650 AMC ●●●●● Models 72650, Models 72650, Models 72650, Models 72650, Models 72650, 7777744444650650650650650 6U cPCI 6U cPCI 6U cPCI 6U cPCI 6U cPCI ● ● ● ● ● Model 73650 3U cPCIModel 73650 3U cPCIModel 73650 3U cPCIModel 73650 3U cPCIModel 73650 3U cPCI


D/AClock/Sync

Bus

VCXO

500 MHz12-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB

TTL Gate / Trig

TTL Sync / PPS

Sample Clk

Reset

Gate A/D

Gate D/A

Sync / PPS A/D

Sync / PPS D/A

Timing Bus

500 MHz12-BIT A/D

Sample Clk /Reference Clk In A/D

Clock/SyncBus 800 MHz

16-BIT D/A

RFXFORMR

321616

RF Out

RFXFORMR

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

RFXFORMR

RF Out

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

TTLPPS/Gate/Sync

TIMING BUSGENERATOR


LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2 VPX-P1

VIRTEX-6 FPGA


GTXGTXGTX

GigabitSerial I/O

Option -105

4X4X 4X

x4PCIe

Model 52650 is a member of the Cobalt family ofhigh-performance 3U VPX boards based on the XilinxVirtex-6 FPGA. A two-channel, high-speed dataconverter, it is suitable for connection to HF or IF portsof a communications or radar system. Its built-in datacapture and playback features offer an ideal turnkeysolution as well as a platform for developing and deployingcustom FPGA processing IP. The 52650 includes two500 MHz 12-bit A/Ds, one DUC, two 800 MHz 16-bitD/As and four banks of memory. It features built-insupport for PCI Express over the 3U VPX backplane.

The Pentek Cobalt architecture features a Virtex-6FPGA. All of the board’s data and control paths are acces-sible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, data packing,gating, triggering and memory control. The Cobalt architectureorganizes the FPGA as a container for data-processingapplications where each function exists as an intellectualproperty (IP) module.

Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The 52650 factory-installedfunctions include an A/D acquisition and a D/A waveformplayback IP module. In addition, IP modules for eitherDDR3 or QDRII+ memories, a controller for all dataclocking and synchronization functions, a test signalgenerator and a PCIe interface complete the factory-installed functions.

Multiple 52650’s can be driven from the LVPECL busmaster, supporting synchronous sampling and sync functionsacross all connected boards. The architecture supports up tofour memory banks which can be configured with allQDRII+ SRAM, DDR3 SDRAM, or as combinations.

Versions of the 52650 are available as another 3UVPX (Model 53650), 6U VPX (Models 57650 and58650 dual density), XMC module (Model 71650), x8 PCIe(Model 78650), AMC (Model 56650), 6U cPCI (Models72650 and 74650 dual density), and 3U cPCI (Model 73650).

This Model is alsoavailable with 400 MHz,

14-bit A/Ds













3434343434



Figure 40

4-4-4-4-4-Channel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with VirChannel 200 MHz 16-bit A/D with Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 5Models 5Models 5Models 5Models 53663663663663660, 50, 50, 50, 50, 52662662662662660 3U VPX 0 3U VPX 0 3U VPX 0 3U VPX 0 3U VPX ●●●●● Models 57 Models 57 Models 57 Models 57 Models 5766666666660, 580, 580, 580, 580, 5866666666660 6U VPX0 6U VPX0 6U VPX0 6U VPX0 6U VPX ●●●●● Model 71Model 71Model 71Model 71Model 7166666666660 XMC 0 XMC 0 XMC 0 XMC 0 XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 7866666666660 PCIe0 PCIe0 PCIe0 PCIe0 PCIeModel 56660 AMC Model 56660 AMC Model 56660 AMC Model 56660 AMC Model 56660 AMC ● ● ● ● ● Models 72660, 74660 6U cPCI Models 72660, 74660 6U cPCI Models 72660, 74660 6U cPCI Models 72660, 74660 6U cPCI Models 72660, 74660 6U cPCI ● ● ● ● ● Model 73660 3U cPCIModel 73660 3U cPCIModel 73660 3U cPCIModel 73660 3U cPCIModel 73660 3U cPCI

TIMING BUSGENERATOR


VCXO

200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

16

QDRII+SRAM8 MB


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

RF In

RFXFORMR

200 MHz16-BIT A/D

16


DDR3 option 155

QDRII+ option 160

DDR3 option 165

RF In

RFXFORMR

200 MHz16-BIT A/D

16

Gate / Trigger /Sync / PPS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTXLVDS

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

Option -105

4X8X 4X

x8PCIe

VIRTEX-6 FPGA


Model 53660 is a member of the Cobalt family ofhigh-performance 3U VPX boards based on the XilinxVirtex-6 FPGA. A multichannel, high-speed dataconverter, it is suitable for connection to HF or IF portsof a communications or radar system. Its built-in datacapture and playback features offer an ideal turnkey solutionas well as a platform for developing and deploying customFPGA processing IP. It includes four 200 MHz, 16-bit A/Dsand four banks of memory. In addition to supportingPCI Express Gen. 2 as a native interface, the Model53660 includes general purpose and gigabit serial connec-tors for application-specific I/O .


Each member of the Cobalt family is deliveredwith factory-installed applications ideally matched to theboard’s analog interfaces. The 53660 factory-installedfunctions include four A/D acquisition IP modules. Inaddition, IP modules for either DDR3 or QDRII+memories, a controller for all data clocking and syn-chronization functions, a test signal generator and aPCIe interface complete the factory-installed functions.

Multiple 53660’s can be driven from the LVPECLbus master, supporting synchronous sampling and syncfunctions across all connected modules. The architecturesupports up to four memory banks which can be configuredwith all QDRII+ SRAM, DDR3 SDRAM, or as combina-tion of two banks of each type of memory.

Versions of the 53660 are available as another 3U VPX(Model 52660 ), 6U VPX (Models 57660 and 58660dual density), XMC (Model 71660), x8PCIe (Model78660), AMC (Model 56660), 6U cPCI (Models 72660 and74660 with dual density), and 3U cPCI (Model 73660).













3535353535


Figure 41See page 28

8-8-8-8-8-Channel 200 MHz, 16-bit A/D with TChannel 200 MHz, 16-bit A/D with TChannel 200 MHz, 16-bit A/D with TChannel 200 MHz, 16-bit A/D with TChannel 200 MHz, 16-bit A/D with Two Virwo Virwo Virwo Virwo Virtex-7 FPGAstex-7 FPGAstex-7 FPGAstex-7 FPGAstex-7 FPGAs

Models 5Models 5Models 5Models 5Models 58768768768768760, 50, 50, 50, 50, 57767767767767760 6U VPX0 6U VPX0 6U VPX0 6U VPX0 6U VPX ●●●●● Models 52 Models 52 Models 52 Models 52 Models 5276767676760, 530, 530, 530, 530, 5376767676760 3U VPX 0 3U VPX 0 3U VPX 0 3U VPX 0 3U VPX ●●●●● Model 71Model 71Model 71Model 71Model 7176767676760 XMC 0 XMC 0 XMC 0 XMC 0 XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 7876767676760 PCIe0 PCIe0 PCIe0 PCIe0 PCIeModel 56760 AMC Model 56760 AMC Model 56760 AMC Model 56760 AMC Model 56760 AMC ● ● ● ● ● Models 72760, 74760 6U cPCI Models 72760, 74760 6U cPCI Models 72760, 74760 6U cPCI Models 72760, 74760 6U cPCI Models 72760, 74760 6U cPCI ● ● ● ● ● Model 73760 3U cPCIModel 73760 3U cPCIModel 73760 3U cPCIModel 73760 3U cPCIModel 73760 3U cPCI

Model 58760 is a member of the Onyx family ofhigh-performance 6U VPX boards based on the XilinxVirtex-7 FPGA. A multichannel, high-speed data converter,it is suitable for connection to HF or IF ports of acommunications or radar system. Its built-in data capturefeatures offer an ideal turnkey solution as well as aplatform for developing and deploying custom FPGAprocessing IP. It includes eight A/Ds and eight banks ofmemory. In addition to supporting PCI Express Gen. 3 as anative interface, the Model 58760 includes general purposeand gigabit serial connectors for application-specific I/O.

Based on the proven design of the Pentek Cobalt family,Onyx raises the processing performance with the flagship familyof Virtex-7 FPGAs from Xilinx. As the central feature of theboard architecture, the FPGA has access to all data andcontrol paths, enabling factory-installed functions including datamultiplexing, channel selection, data packing, gating, triggeringand memory control. The Onyx Architecture organizes theFPGA as a container for data processing applications where eachfunction exists as an intellectual property (IP) module.

Each member of the Onyx family is delivered with factory-installed applications ideally matched to the board’s analoginterfaces. The 58760 factory-installed functions include eightA/D acquisition IP modules for simplifying data capture anddata tranfer. IP modules for DDR3 SDRAM memories,controllers for all data clocking and synchronization functions,test signal generators, and a PCIe interface complete the factory-installed functions.

The 58760 architecture supports eight independentDDR3 SDRAM memory banks. Each bank is 1 GB deepand is an integral part of the board’s DMA capabilities,providing FIFO memory space for creating DMA packets.Built-in memory functions include multichannel A/Ddata capture, tagging and streaming.

Versions of the 58760 are also available as a 6U VPX(Model 57760 single density), 3U VPX (Models 52760and 53760), XMC (Model 71760), x8 PCIe (Model78760), AMC (Model 56760), 6U cPCI (Models 72760and 74760 dual density), and 3U cPCI (Model 73760).

LVDS

48

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

VIRTEX-7 FPGA

VX330T or VX690T

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

32 32 32 32

GTXGTXGTX

PCIeGen. 3 x8

4X4X

PCIeGen. 3 x8

CONFIGFLASH1 GB

PCIeGen. 3x8

FPGAConfigBus


MANAGER

VPX-P2VPX-P1

PCIe-to PCIeSWITCH



Block Diagram, Model 57760.


except the PCIe-to-PCIe Switch and

provides 24 LVDS pairs from the

2nd FPGA to VPX-P5

TIMING BUSGENERATOR


200 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR


Sample ClkReset

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus

200 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

200 MHz16-BIT A/D

16

RF In

RFXFORMR

200 MHz16-BIT A/D

16


VCXO

Model 587606U VPX

dual density













3636363636


Figure 42

4-4-4-4-4-Channel 200 MHz 16-bit A/D with Installed DDC and Beamforming Cores, VirChannel 200 MHz 16-bit A/D with Installed DDC and Beamforming Cores, VirChannel 200 MHz 16-bit A/D with Installed DDC and Beamforming Cores, VirChannel 200 MHz 16-bit A/D with Installed DDC and Beamforming Cores, VirChannel 200 MHz 16-bit A/D with Installed DDC and Beamforming Cores, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 5Models 5Models 5Models 5Models 536613661366136613661, 5, 5, 5, 5, 52661 2661 2661 2661 2661 3U VPX 3U VPX 3U VPX 3U VPX 3U VPX ●●●●● Models 57 Models 57 Models 57 Models 57 Models 57661661661661661, 58, 58, 58, 58, 58661 661 661 661 661 6U VPX6U VPX6U VPX6U VPX6U VPX ●●●●● Model 71Model 71Model 71Model 71Model 71661661661661661 XMC XMC XMC XMC XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 78661661661661661 PCIe PCIe PCIe PCIe PCIeModel 56661 AMC Model 56661 AMC Model 56661 AMC Model 56661 AMC Model 56661 AMC ● ● ● ● ● Models 72661, 74661 6U cPCI Models 72661, 74661 6U cPCI Models 72661, 74661 6U cPCI Models 72661, 74661 6U cPCI Models 72661, 74661 6U cPCI ●●●●● Model 73660 3U cPCIModel 73660 3U cPCIModel 73660 3U cPCIModel 73660 3U cPCIModel 73660 3U cPCI

Model 53661 3U VPXCOTs andrugged

BEAMFORMER CORE

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe

8Xfrom previousboard

to nextboard

sum out

sum in

VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL

A/DACQUISITIONIP MODULE 1




LINKED-LISTDMA ENGINE




METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MUX MUX MUX MUX

DATA PACKING &FLOW CONTROL




AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�

SUMMER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE DDC CORE DDC CORE

TESTSIGNAL

GENERATOR



8X4X 4X

Model 53661 is a member of the Cobalt family of highperformance XMC modules based on the Xilinx Virtex-6FPGA. A multichannel, high-speed data converter based onthe Model 53660 described earlier, it includes factory-installedIP cores to enhance the performance of the 53660 and addressthe requirements of many applications.

The 53661 factory-installed functions include four A/Dacquisition IP modules. Each of the four acquisition IPmodules contains a powerful, programmable DDC IPcore. IP modules for either DDR3 or QDRII+ memo-ries, a controller for all data clocking and synchronizationfunctions, a test signal generator, an Aurora gigabitserial interface, and a PCIe interface complete thefactory-installed functions.

Each DDC has an independent 32-bit tuning frequencysetting that ranges from DC to ƒs, where ƒs is the A/Dsampling frequency. Each DDC can have its ownunique decimation setting, supporting as many as fourdifferent output bandwidths for the board. Decimations

can be programmed from 2 to 65,536 providing a widerange to satisfy most applications.

The 53661 also features a complete beamformingsubsystem. Each DDC core contains programable I & Qphase and gain adjustments followed by a power meterthat continuously measures the individual average poweroutput. The power meters present average power measure-ments for each DDC core output in easy-to-read registers. Athreshold detector automatically sends an interrupt tothe processor if the average power level of any DDCcore falls below or exceeds a programmable threshold.

For larger systems, multiple 53661’s can be chainedtogether via the built-in Xilinx Aurora gigabit serialinterface. More on Beamforming Application, page 75.

Versions of the 53661 are available as another 3U VPX(Model 52661), 6U VPX (Models 57661 and 58661 dualdensity), XMC (Model 71661), x8 PCIe (Model 78661),AMC (Model 56661), 6U cPCI (Models 72661 and74661 dual density), and 3U cPCI (Model 73661).













3737373737


Figure 43

4-4-4-4-4-Channel 200 MHz 16-bit A/D with Installed DDC and VITChannel 200 MHz 16-bit A/D with Installed DDC and VITChannel 200 MHz 16-bit A/D with Installed DDC and VITChannel 200 MHz 16-bit A/D with Installed DDC and VITChannel 200 MHz 16-bit A/D with Installed DDC and VITA 49 IP Cores, VirA 49 IP Cores, VirA 49 IP Cores, VirA 49 IP Cores, VirA 49 IP Cores, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 5Models 5Models 5Models 5Models 536643664366436643664, 5, 5, 5, 5, 526642664266426642664 3U VPX 3U VPX 3U VPX 3U VPX 3U VPX ●●●●● Models 57 Models 57 Models 57 Models 57 Models 57664664664664664, 58, 58, 58, 58, 58664664664664664 6U 6U 6U 6U 6U VPXVPXVPXVPXVPX ●●●●● Model 71Model 71Model 71Model 71Model 71664664664664664 XMC XMC XMC XMC XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 78664664664664664 PCIe PCIe PCIe PCIe PCIeModel 56664 AMC Model 56664 AMC Model 56664 AMC Model 56664 AMC Model 56664 AMC ● ● ● ● ● Models 72664, 74664 6U cPCI Models 72664, 74664 6U cPCI Models 72664, 74664 6U cPCI Models 72664, 74664 6U cPCI Models 72664, 74664 6U cPCI ● ● ● ● ● Model 73664 3U cPCIModel 73664 3U cPCIModel 73664 3U cPCIModel 73664 3U cPCIModel 73664 3U cPCI

Model 53664 3U VPXCOTS & Rugged

BEAMFORMER CORE

PCIe INTERFACE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

PCIe

8Xfrom previousboard

to nextboard

sum out

sum in

VIRTEX-6 FPGA DATAFLOW DETAILVIRTEX-6 FPGA DATAFLOW DETAIL





LINKED-LIST DMAENGINE & VITA 49.0


METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 3

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MUX MUX MUX MUX





AURORAGIGABITSERIAL

INTERFACE

INPUT MULTIPLEXER

�SUMMER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

MUXDDC CORE DDC CORE DDC CORE DDC CORE

TESTSIGNAL

GENERATOR



8X4X 4X



Model 53664 is a member of the Cobalt family of high-performance 3U VPX boards based on the Xilinx Virtex-6FPGA. A multichannel, high-speed data converter based onthe Model 53660 described previously, it includes a program-mable DDC and is suitable for connection to HF or IF portsof a communications or radar system. Its built-in data captureand playback features offer an ideal turnkey solution. The53664 PCIe output supports fully the VITA 49.0 VITARadio Transport (VRT)Standard described on page 14.

The 53664 factory-installed functions include four A/Dacquisition IP modules. Each of the four acquisition IPmodules contains a powerful, programmable DDC IPcore. IP modules for either DDR3 or QDRII+ memo-ries, a controller for all data clocking and synchronizationfunctions, a test signal generator, an Aurora gigabitserial interface, and a PCIe interface complete thefactory-installed functions.

The VITA 49.0 specification addresses the problem ofinteroperability between different elements of Software

Defined Radio (SDR) systems. Specifically, each SDRreceiver manufacturer typically develops custom andproprietary digitized data and metadata formats, makinginteroperability of data from different receivers impossible.

VITA 49.0 solves this problem by providing a frame-work for SDR receivers used for analysis of RF spectrum and localization of RF emmisions. It is based upon a transport protocol layer to convey time-stamped digital data between components in the system. With a com-mon protocol, SDR receivers can be interchanged, thereby enabling hardware upgrades and mitigating hardware lifecycle limitations. This eliminates the need to create new software to support each new receiver. The 53664 supports fully the VITA 49.0 specification.

Versions of the 53664 are also available as a different3U VPX (Model 52664), 6U VPX (Models 57664 and58664 dual density), XMC (Model 71664), x8 PCIe (Model78664), AMC (Model 56664), 6U cPCI (Models 7266and 74664 dual density), and 3U cPCI (Model 73664).













3838383838


Figure 44

4-4-4-4-4-Channel 1.25 GHz D/A with DUCs, VirChannel 1.25 GHz D/A with DUCs, VirChannel 1.25 GHz D/A with DUCs, VirChannel 1.25 GHz D/A with DUCs, VirChannel 1.25 GHz D/A with DUCs, Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 5Models 5Models 5Models 5Models 576707670767076707670, 5, 5, 5, 5, 586708670867086708670 6U VPX 6U VPX 6U VPX 6U VPX 6U VPX ●●●●● Models 53 Models 53 Models 53 Models 53 Models 53670670670670670, 52, 52, 52, 52, 52670670670670670 3U VPX 3U VPX 3U VPX 3U VPX 3U VPX ●●●●● Model 71Model 71Model 71Model 71Model 71670670670670670 XMC XMC XMC XMC XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 78670670670670670 PCIe PCIe PCIe PCIe PCIeModel 56670 AMC Model 56670 AMC Model 56670 AMC Model 56670 AMC Model 56670 AMC ●●●●● Models 72670, 74670 6U cPCI Models 72670, 74670 6U cPCI Models 72670, 74670 6U cPCI Models 72670, 74670 6U cPCI Models 72670, 74670 6U cPCI ● ● ● ● ● Model 73670 3U cPCIModel 73670 3U cPCIModel 73670 3U cPCIModel 73670 3U cPCIModel 73670 3U cPCI

Model 57670 is a member of the Cobalt family ofhigh-performance 6U VPX boards based on the XilinxVirtex-6 FPGA. This 4-channel, high-speed dataconverter is suitable for connection to transmit HF or IFports of a communications or radar system. Its built-indata playback features offer an ideal turnkey solutionfor demanding transmit applications. It includes fourD/As, four digital upconverters and four banks ofmemory. In addition to supporting PCI Express Gen. 2 asa native interface, the Model 57670 includes a front panelgeneral-purpose connector for application-specific I/O.

The Pentek Cobalt Architecture features a Virtex-6FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installed functionsincluding data multiplexing, channel selection, datapacking, gating, triggering and memory control. TheCobalt Architecture organizes the FPGA as a containerfor data processing applications where each functionexists as an intellectual property (IP) module.

Each member of the Cobalt family is delivered withfactory-installed applications ideally matched to the board’sanalog interfaces. The Model 57670 factory-installedfunctions include a sophisticated D/A WaveformPlayback IP module. Four linked-list controllers supportwaveform generation to the four D/As from tables storedin either on-board memory or off-board host memory.

IP modules for DDR3 SDRAM memories, acontroller for all data clocking and synchronizationfunctions, a test signal generator, and a PCIe interfacecomplete the factory-installed functions and enable the57670 to operate as a turnkey solution without the need todevelop FPGA IP.

Versions of the 57670 are also available as 6U VPX(Model 58670 dual density), 3U VPX (Models 53670 and52670), XMC (Model 71670), PCIe (Model 78670),AMC(Model 56670), 6U cPCI (Models 72670 and 74670dual density), and 3U cPCI (Model 73670).

VIRTEX-6 FPGA


16

ConfigFLASH64 MB

LVDS GTX

40 8X

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P3

GTXGTX

PCIeGen. 2 x8

4X 4X

VPX-P2VPX-P1


TIMING BUSGENERATOR


VCXO


Clock/SyncBus A

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

16-BIT D/A1.25 GHz

DIGITALUPCONVERTER

RF Out

RFXFORMR

RFXFORMR

1.25 GHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

16 16

Gate InSync In

�Sync Bus A

Gate InSync In

�Sync Bus B

Trigger In

Clock/SyncBus B

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB


Model 576706U VPX

single density













3939393939


Models 53Models 53Models 53Models 53Models 53690690690690690, 52, 52, 52, 52, 52690690690690690 3U VPX 3U VPX 3U VPX 3U VPX 3U VPX ●●●●● Models 57 Models 57 Models 57 Models 57 Models 57690690690690690, 58, 58, 58, 58, 58690690690690690 6U VPX 6U VPX 6U VPX 6U VPX 6U VPX ●●●●● Model 71Model 71Model 71Model 71Model 71690690690690690 XMC XMC XMC XMC XMC ●●●●● Model 78 Model 78 Model 78 Model 78 Model 78690690690690690 PCIe PCIe PCIe PCIe PCIeModel 56690 AMC Model 56690 AMC Model 56690 AMC Model 56690 AMC Model 56690 AMC ●●●●● Models 72690, 74690 6U cPCI Models 72690, 74690 6U cPCI Models 72690, 74690 6U cPCI Models 72690, 74690 6U cPCI Models 72690, 74690 6U cPCI ● ● ● ● ● Model 73690 3U cPCIModel 73690 3U cPCIModel 73690 3U cPCIModel 73690 3U cPCIModel 73690 3U cPCI

Figure 45

LLLLL-Band RF T-Band RF T-Band RF T-Band RF T-Band RF Tuner with 2-uner with 2-uner with 2-uner with 2-uner with 2-Channel 200 MHz A/D and VirChannel 200 MHz A/D and VirChannel 200 MHz A/D and VirChannel 200 MHz A/D and VirChannel 200 MHz A/D and Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA


VCXO

16

QDRII+SRAM8 MB


Sample ClkRef In

Gate AGate B

Sync / PPS A

Sync / PPS B

Timing Bus


A/D Clock/Sync

16 16

ConfigFLASH64 MB

16

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB

QDRII+ option 150

16

QDRII+SRAM8 MB

1616

QDRII+SRAM8 MB

16

DDR3SDRAM512 MB

DDR3SDRAM512 MB


DDR3 option 155

QDRII+ option 160

DDR3 option 165

Trigger 1

200 MHz16-BIT A/D

200 MHz16-BIT A/D

1616

MAX2112

I Q

RefIn

RFIn

RefOut

12-BITD/A

2

I C2

GC

Control

Trigger 2

TIMINGGENERATOR


Ref

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTXLVDS

Gigabit Serial I/O

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1

4X8X 4X

x8PCIe

Option -105

VIRTEX-6 FPGA


Model 53690 is a member of the Cobalt family ofhigh-performance 3U VPX boards based on the XilinxVirtex-6 FPGA. A 2-channel high-speed data converter, itis suitable for connection directly to the RF port of acommunications or radar system. Its built-in data capturefeatures offer an ideal turnkey solution. The Model 53690includes an L-Band RF tuner, two 200 MHz, 16-bitA/Ds and four banks of memory. It features built-insupport for PCI Express over the 3U VPX backplane.


Each member of the Cobalt family is delivered withfactory-installed applications ideally matched to the

board’s analog interfaces. The 53690 factory-installedfunctions include two A/D acquisition IP modules. IPmodules for either DDR3 or QDRII+ memories, acontroller for all data clocking and synchronizationfunctions, a test signal generator, and a PCIe interfacecomplete the factory-installed functions.

A front panel connector accepts L-Band signalsbetween 925 MHz and 2175 MHz from an antenna LNB. AMaxim MAX2112 tuner directly converts these signals tobaseband using a broadband I/Q downconverter. The deviceincludes an RF variable-gain LNA (low-noise amplifier), a PLLsynthesized local oscillator, quadrature (I + Q) downconvertingmixers, baseband lowpass filters and variable-gain basebandamplifiers. See an L-Band Application on page 74.

Versions of the 53690 are available as a different 3UVPX (Model 52690), 6U VPX (Models 57690 and 58690dual density), XMC (Model 71690), an x8 PCI (Model78690), AMC (Model 56690), 6U cPCI (Models 72690and 74690 dual density), and 3U cPCI (Model 73690).













4040404040


Figure 46


VIRTEX-6 FPGA


32

32 PairsLVDS Data

16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

Memory Banks 1 & 2 Memory Banks 3 & 4Option 165

80-pin Front PanelConnector

LVDSClock

DataValid

DataSuspend

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

VPX-P2

GTXGTXGTX

GigabitSerial I/O

VPX-P1

Option -105

4X4X 4X

x4PCIe

LLLLLVDS Digital I/O with VirVDS Digital I/O with VirVDS Digital I/O with VirVDS Digital I/O with VirVDS Digital I/O with Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

Models 52610, 53610 3U VPX Models 52610, 53610 3U VPX Models 52610, 53610 3U VPX Models 52610, 53610 3U VPX Models 52610, 53610 3U VPX ●●●●● Models 57610, 58610 6U VPX Models 57610, 58610 6U VPX Models 57610, 58610 6U VPX Models 57610, 58610 6U VPX Models 57610, 58610 6U VPX ●●●●● Model 71610 XMC Model 71610 XMC Model 71610 XMC Model 71610 XMC Model 71610 XMC ●●●●● Model 78610 PCIe Model 78610 PCIe Model 78610 PCIe Model 78610 PCIe Model 78610 PCIeModel 56610 AMC Model 56610 AMC Model 56610 AMC Model 56610 AMC Model 56610 AMC ●●●●● Models 72610, 74610 6U cPCI Models 72610, 74610 6U cPCI Models 72610, 74610 6U cPCI Models 72610, 74610 6U cPCI Models 72610, 74610 6U cPCI ● ● ● ● ● Model 73610 3U cPCIModel 73610 3U cPCIModel 73610 3U cPCIModel 73610 3U cPCIModel 73610 3U cPCI

Model 52610 is a member of the Cobalt family ofhigh-performance 3U VPX boards based on the XilinxVirtex-6 FPGA. This digital I/O module provides 32LVDS differential inputs or outputs plus LVDS clock,data valid, and data flow control on a front panel 80-pinconnector. Its built-in data capture and data generationfeature offers an ideal turnkey solution.

In addition to supporting PCI Express as a nativeinterface, the Model 52610 includes a general-purposeconnector for application-specific I/O.

The Pentek Cobalt Architecture features a Virtex-6FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installed functionsincluding data transfer and memory control. The CobaltArchitecture organizes the FPGA as a container for dataprocessing applications where each function exists as anintellectual property (IP) module.

Each member of the Cobalt family is delivered withfactory-installed applications ideally matched to the

board’s interface. The 52610 factory-installed functionsinclude 32-bit acquisition and generation IP modules, tosupport either input or output functions, respectively.

IP modules for DDR3 SDRAM memories, a control-ler for all data clocking, a test signal generator, and a PCIeinterface complete the factory-installed functions andenable the 52610 to operate as a complete turnkeysolution without the need to develop any FPGA IP.

The Model 52610 includes an industry-standardinterface fully compliant with PCI Express Gen. 1 busspecifications. Supporting a PCIe x4 or x8 connection,the interface includes multiple DMA controllers forefficient transfers to and from the module.

Versions of the 52610 are also available as a different3U VPX (Model 53610), 6U VPX (Models 57610 and58610 dual density), XMC (Model 71610), x8 PCIe (Model78610), AMC (Model 56610), 6U cPCI (Models 72610and 74610 dual density), and 3U cPCI (Model 73610).













4141414141


Models 5Models 5Models 5Models 5Models 533333616161616111111, 5, 5, 5, 5, 522222616161616111111 3U VPX 3U VPX 3U VPX 3U VPX 3U VPX ●●●●● Models 5761Models 5761Models 5761Models 5761Models 576111111, 5861 6U VPX, 5861 6U VPX, 5861 6U VPX, 5861 6U VPX, 5861 6U VPX ●●●●● Model 71611 XMC Model 71611 XMC Model 71611 XMC Model 71611 XMC Model 71611 XMC ●●●●● Model 78611 PCIe Model 78611 PCIe Model 78611 PCIe Model 78611 PCIe Model 78611 PCIeModel 56611 AMC Model 56611 AMC Model 56611 AMC Model 56611 AMC Model 56611 AMC ●●●●● Models 72611, 74611 6U cPCI Models 72611, 74611 6U cPCI Models 72611, 74611 6U cPCI Models 72611, 74611 6U cPCI Models 72611, 74611 6U cPCI ● ● ● ● ● Model 73611 3U cPCIModel 73611 3U cPCIModel 73611 3U cPCIModel 73611 3U cPCIModel 73611 3U cPCI

Figure 47

Digital I/O: Quad Serial FPDP InterDigital I/O: Quad Serial FPDP InterDigital I/O: Quad Serial FPDP InterDigital I/O: Quad Serial FPDP InterDigital I/O: Quad Serial FPDP Interface with Virface with Virface with Virface with Virface with Virtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGAtex-6 FPGA

VIRTEX-6 FPGA

LX240T, SX315T or SX475T

32 16

ConfigFLASH64 MB

32

DDR3SDRAM512 MB

DDR3SDRAM512 MB

3232

DDR3SDRAM512 MB

DDR3SDRAM512 MB

Memory Banks 1 & 2 Memory Banks 3 & 4DDR3 option 155 DDR3 option 165

RX TX RX TX RX TX RX TX

GTXGTXGTXGTX

CH 1 CH 2 CH 3 CH 4

LVDS

40

FPGAI/O

Option -104

VPX BACKPLANE

GTX

4XGbitSerial

4XGbitSerial

4XGbitSerial

4XGbitSerial

CROSSBARSWITCH

VPX-P1VPX-P2

8X

x8PCIe

FIBER OPTICor COPPERINTERFACE




Model 53611 is a member of the Cobalt family ofhigh-performance XMC modules based on the XilinxVirtex-6 FPGA. A multichannel, gigabit serial interface,it is ideal for interfacing to Serial FPDP data converter boardsor as a chassis-to-chassis data link.

The 53611 is fully compatible with the VITA 17.1Serial FPDP specification. Its built-in data transferfeatures make it a complete turnkey solution. For userswho require application-specific functions, the 53611serves as a flexible platform for developing and deployingcustom FPGA processing IP.

In addition to supporting PCI Express as a nativeinterface, the Model 53611 includes a general-purposeconnector for application-specific I/O.

The Pentek Cobalt Architecture features a Virtex-6FPGA. All of the board’s data and control paths areaccessible by the FPGA, enabling factory-installed func-tions including data transfer and memory control. TheCobalt Architecture organizes the FPGA as a container

for data processing applications where each function existsas an intellectual property (IP) module.

IP modules for DDR3 SDRAM memories, controllersfor data routing and flow control, CRC support, advancedDMA engines, and a PCIe interface complete the factory-installed functions and enable the 53611 to operate as acomplete turnkey solution without developing FPGA IP.

The 53611 is fully compatible with the VITA 17.1Serial FPDP specification. With the capability to support1.0625, 2.125, 2.5, 3.125, and 4.25 Gbaud link ratesand the option for multi-mode and single-mode opticalinterfaces, the board can work in virtually any system.Programmable modes include: flow control in both receiveand transmit directions, CRC support, and copy/loop.

Versions of the 53611 are available as a different 3UVPX (Model 52611), 6U VPX (Models 57611 and 58611dual density), XMC (Model 71611); x8 PCIe (Model78611), AMC (Model 56611), 6U cPCI (Models 72611and 74611 dual density), and 3U cPCI (Model 73611).














4242424242


Figure 48See Page 28

3U VPX Vir3U VPX Vir3U VPX Vir3U VPX Vir3U VPX Virtex-7 Ptex-7 Ptex-7 Ptex-7 Ptex-7 Processor and FMC Carrierrocessor and FMC Carrierrocessor and FMC Carrierrocessor and FMC Carrierrocessor and FMC Carrier

Model 5973FMC

Model 5973 - FMCModel 5973 - FMCModel 5973 - FMCModel 5973 - FMCModel 5973 - FMC

FMCCONNECTOR

10X160

FPGA GigabitSerial I/O

GTX LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

4X

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

VPX BACKPLANE

VPX-P1 VPX-P2 (½)

LVDS GTX

VPX-P0

OPTICALTRANSCEIVER

(Optional)

FPGAGigabitSerial I/O

GTX

12X

VPX-P2 (½)VITA 66.4

The Flexor® Model 5973 is a high-performanceVPX board based on the Xilinx Virtex-7 FPGA. As a stand-alone processor board, it provides an ideal developmentand deployment platform for demanding signal-processingapplications.

The 5973 includes a VITA-57.1 FMC site providingaccess to a wide range of I/O options. When combined withany of Pentek’s analog interface FMCs, it becomes acomplete multichannel data conversion and processingsubsystem suitable for connection to IF, HF or RF portsof a communications or radar system.

The 5973 architecture includes an optional built-ingigabit serial optical interface. Up to 12 high-speed duplexoptical lanes are available on an MTP connector. Withthe installation of a serial protocol in the FPGA, thisinterface enables a high-bandwidth connection between5973s mounted in the same chassis or even over extendeddistances between them.

When integrated with a Pentek FMC, the 5973 isdelivered with factory-installed applications ideallymatched to the board’s analog or digital interfaces.These can include A/D acquisition and D/A waveformplayback engines for simplifying data capture andplayback.

Data tagging and metadata packet generation, inconjunction with powerful linked-list DMA engines,provide a streamlined interface for moving data on andoff the board and identifying data packets withchannel, timing and sample count information.

IP modules for DDR3 SDRAM memories, controllersfor all data clocking and synchronization functions, a testsignal generator, and a PCIe interface complete thefactory-installed functions and enable the 5973 and itsinstalled FMC to operate as a complete turnkey solutionwithout the need to develop any FPGA IP.






4343434343


Figure 49


PCI Express VirPCI Express VirPCI Express VirPCI Express VirPCI Express Virtex-7 Ptex-7 Ptex-7 Ptex-7 Ptex-7 Processor and FMC Carrier - x8 PCIerocessor and FMC Carrier - x8 PCIerocessor and FMC Carrier - x8 PCIerocessor and FMC Carrier - x8 PCIerocessor and FMC Carrier - x8 PCIe


FMCCONNECTOR

10X160

LVDSGTX

FPGALVDSGPIO

PCIeGen. 3 x8

VIRTEX-7 FPGA

VX330T or VX690T

CONFIGFLASH1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

DDR3SDRAM

1 GB

16pairs

32 32 32 32PCIeGen. 3 x8

FPGAConfigBus


MANAGER

Card Edge ConnectorPCIe Gen 3 x8

LVDS GTX

OPTICALTRANSCEIVER

(optional)

FPGAGigabitSerial I/O

GTX

12X

To Second SlotFront Panel

MTP Connector

See page 28

Model 7070 shownwith Model 3312

multichannel A/D &D/A FMC module

The Flexor Model 7070 is a high-performance PCIeboard based on the Xilinx Virtex-7 FPGA. As a stand-alone processor board, it provides an ideal developmentand deployment platform for demanding signal process-ing applications.

The 7070 includes a VITA-57.1 FMC site providingaccess to a wide range of I/O options. When combinedwith any of Pentek’s analog interface FMCs, it becomesa complete multichannel data conversion and processingsubsystem suitable for connection to IF, HF or RF portsof a communications or radar system.

The 7070 architecture includes an optional built-ingigabit serial optical interface. Up to 12 high-speed duplexoptical lanes are available on an MTP connector. Withthe installation of a serial protocol in the FPGA, thisinterface enables a high-bandwidth connection between7070s mounted in the same chassis or even over extendeddistances between them.

When integrated with a Pentek FMC, the 7070 isdelivered with factory-installed applications ideally matchedto the board’s analog or digital interfaces. These caninclude A/D acquisition and D/A waveform playbackengines for simplifying data capture and playback.

Data tagging and metadata packet generation, inconjunction with powerful linked-list DMA engines,provide a streamlined interface for moving data on and offthe board and identifying data packets with channel,timing and sample -count information.

IP modules for DDR3 SDRAM memories, controllersfor all data clocking and synchronization functions, a testsignal generator, and a PCIe interface complete thefactory-installed functions and enable the 7070 andinstalled FMC to operate as a complete turnkeysolution without the need to develop any FPGA IP.




4444444444


Figure 50


4-4-4-4-4-Channel 250 MHz 16-bit A/D, 2-Channel 250 MHz 16-bit A/D, 2-Channel 250 MHz 16-bit A/D, 2-Channel 250 MHz 16-bit A/D, 2-Channel 250 MHz 16-bit A/D, 2-Channel 800 MHz 16-bit D/AChannel 800 MHz 16-bit D/AChannel 800 MHz 16-bit D/AChannel 800 MHz 16-bit D/AChannel 800 MHz 16-bit D/A


TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

250 MHz16-BIT A/D


A/D Clock/Sync Bus

1616

RF In

RFXFORMR

250 MHz16-BIT A/D

16

RF In

RFXFORMR

250 MHz16-BIT A/D

16


FMCCONNECTOR

Control& Status

RFXFORMR

800 MHz16-BIT D/A

DIGITALUPCONVERTER

RF Out

RFXFORMR

D/A Clock/Sync Bus

16

RFXFORMR

RF Out

RFXFORMR

Model 3312FMC

The Flexor Model 3312 is a multichannel, high-speed data converter FMC module. It is suitable forconnection to HF or IF ports of a communications orradar system. It includes four 250 MHz, 16-bit A/Ds,two 800 MHz, 16-bit D/As, programmable clocking,and multiboard synchronization for support of largerhigh-channel-count systems.

When combined with either the Model 5973 3UVPX or Model 7070 PCIe FMC Carrier, the board-setbecomes a turnkey data acquisition and signal generationsolution. For applications that require custom process-ing, the board set is an ideal IP development anddeployment subsystem.

The front end accepts four analog HF or IF inputson front-panel connectors with transformer-coupling intotwo Texas Instruments ADS42LB69 Dual 250 MHz,16-bit A/D converters.

The Model 3312 is shipped with a simple XilinxVivado project for operating the FMC with the XilinxVC707 Evaluation Kit. This project includes IP forinitializing the FMC and confirming data paths, providingthe user with a tested platform for creating their own FPGAIP for operating the FMC.

While users will find the Model 3312 an excellentanalog interface to the VC707, or any compatible FMCcarrier, the true performance of the 3312 can be unlockedonly when used with the Pentek Model 5973 or Model7070 FMC carriers. With factory-installed IP, the board-set provides a turnkey data acquisition subsystem eliminat-ing the need to create any FPGA IP. Installed features includeflexible A/D acquisition, programmable linked-list DMAengines, and a D/A waveform playback IP module.

When used with the 5973 or the 7070, the 3312 features asophisticated D/A waveform playback IP module. A linked-listcontroller allows users to easily play back to the D/As waveformsstored in either on-board or off-board host memory.





4545454545


Figure 51


8-8-8-8-8-Channel 250 MHz 16-bit A/DChannel 250 MHz 16-bit A/DChannel 250 MHz 16-bit A/DChannel 250 MHz 16-bit A/DChannel 250 MHz 16-bit A/D


Model 3316FMC

TIMING BUSGENERATOR


VCXO

250 MHz16-BIT A/D

RF In

RFXFORMRSample Clk /

Reference Clk In A/DClock/SyncBus

16


Control& Status

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

250 MHz16-BIT A/D

RF In

RFXFORMR

16

FMCCONNECTOR

The Flexor Model 3316 is a multichannel, high-speed data converter FMC module. It is suitable forconnection to HF or IF ports of a communications orradar system. It includes four 250 MHz, 16-bit A/Ds,on-board programmable clocking, and multiboardsynchronization for support of larger high-channel-countsystems.

When combined with either the Model 5973 3UVPX or Model 7070 PCIe FMC Carrier, the board-setbecomes a turnkey data acquisition solution. Forapplications that require custom processing, the board-setis an ideal IP development and deployment subsystem

The front end accepts eight analog HF or IF inputson front-panel connectors with transformer-coupling intofour Texas Instruments ADS42LB69 Dual 250 MHz,16-bit A/D converters.

The Model 3316 is shipped with a simple XilinxVivado project for operating the FMC with the Xilinx

VC707 Evaluation Kit. This project includes IP forinitializing the FMC and confirming data paths, providingthe user with a tested platform for creating their own FPGAIP for operating the FMC.

While users will find the Model 3316 an excellentanalog interface to the VC707, or any compatible FMCcarrier, the true performance of the 3316 can be unlockedonly when used with the Pentek Model 5973 or Model7070 FMC carriers. With factory-installed IP, the board-set provides a turnkey data acquisition subsystem eliminat-ing the need to create any FPGA IP. Installed features includeflexible A/D acquisition, programmable linked-list DMAengines, and a metadata packet creator.

When the 3316 is installed on either the 5973 orthe 7070 FMC carrier, the board-set features eight A/DAcquisition IP modules for easily capturing and movingdata. Each module can receive data from any of the eightA/Ds, or a test signal generator.





4646464646


Figure 52

4-4-4-4-4-Channel 500 MHz 16-bit A/D, 4-Channel 500 MHz 16-bit A/D, 4-Channel 500 MHz 16-bit A/D, 4-Channel 500 MHz 16-bit A/D, 4-Channel 500 MHz 16-bit A/D, 4-Channel 2 GHz 16-bit D/AChannel 2 GHz 16-bit D/AChannel 2 GHz 16-bit D/AChannel 2 GHz 16-bit D/AChannel 2 GHz 16-bit D/A



Model 3324FMC

TIMING BUSGENERATOR


VCXO

500 MHz16-BIT A/D

RF In

RFXFORMR

RF In

RFXFORMR

500 MHz16-BIT A/D


A/DClock/SyncBus

RF In

RFXFORMR

500 MHz16-BIT A/D

RF In

RFXFORMR

500 MHz16-BIT A/D


FMCCONNECTOR

Control& Status

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

2 GHz16-BIT D/A

DIGITALUPCONVERT

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

RFXFORMR

RF Out

RFXFORMR

D/AClock/SyncBus

2 GHz16-BIT D/A

2 GHz16-BIT D/A

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

DIGITALUPCONVERT

The Flexor Model 3324 is a multichannel, high-speeddata converter FMC. It is suitable for connection to HF orIF ports of a communications or radar system. It includesfour 500 MHz, 16-bit A/Ds, four 2 GHz, 16-bit D/As,programmable clocking, and multi-board synchroniza-tion for support of larger high-channel-count systems.

When combined with either the Model 5973 3UVPX or Model 7070 PCIe FMC Carrier, the board-setbecomes a turnkey data acquisition solution. Forapplications that require custom processing, the board-setis an ideal IP development and deployment subsystem.

The front end accepts four analog HF or IF inputson front-panel connectors with transformer-coupling intofour 500 MHz, 16-bit A/D converters.

The Model 3324 is shipped with a simple Xilinx Vivadoproject for operating the FMC with the Xilinx VC707Evaluation Kit. This project includes IP for initializing theFMC and confirming data paths, providing the user with atested platform for creating their own IP for operating the FMC.

While users will find the Model 3324 an excellentanalog interface to the VC707 or any compatible FMCcarrier, the true performance of the 3324 can be unlockedonly when used with the Pentek Model 5973 or Model7070 FMC carriers. With factory-installed IP, the board setprovides a turnkey data acquisition and signal generationsubsystem, eliminating the need to create any FPGA IP.Installed features include flexible A/D acquisition engines, D/Awaveform playback engines, programmable linked-listDMA engines, and a metadata-packet creator.

The board-set features four A/D Acquisition IP Modulesfor easily capturing and moving data. Each module can receivedata from any of the four A/Ds, a test signal generator or fromthe D/A waveform playback IP module in loopback mode.

When used with a Pentek FMC carrier, the 3324features four sophisticated D/A waveform playback IPmodules. A linked-list controller allows users to easilyplay back via the D/As waveforms stored in either on-board or off-board host memory.





4747474747


Figure 53


44444-----ChChChChChannelannelannelannelannel 2 2 2 2 25050505050 MHz MHz MHz MHz MHz A/DA/DA/DA/DA/D, 2-, 2-, 2-, 2-, 2-Channel 800 MHz D/A - 3U VPXChannel 800 MHz D/A - 3U VPXChannel 800 MHz D/A - 3U VPXChannel 800 MHz D/A - 3U VPXChannel 800 MHz D/A - 3U VPX

FlexorSet Model 5973-312FlexorSet Model 5973-312FlexorSet Model 5973-312FlexorSet Model 5973-312FlexorSet Model 5973-312

PCIe INTERFACE

D/AWAVEFORMPLAYBACKIP MODULE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

toD/A

GigabitSerial I/OPCIe

FPGAGPIO

D/A loopback

DETAILS OF VIRTEX-7 FPGA IPINSTALLED IN MODEL 5973-312DETAILS OF VIRTEX-7 FPGA IPINSTALLED IN MODEL 5973-312



DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX



DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

8X 4X 32

A/DACQUISITIONIP MODULES

2 & 3

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D AcqModule 1

toA/D AcqModule 2

toA/D AcqModule 3

toA/D AcqMod 4 &D/A Mod

See page 28

Model 5973-312

Model 5973-312 is a member of the Flexor family ofhigh-performance 3U VPX boards based on the XilinxVirtex-7 FPGA.

As a FlexorSetTM integrated solution, the Model3312 FMC is factory-installed on the 5973 FMC carrier.The required FPGA IP is installed and the board set isdelivered ready for immediate use.

The delivered FlexorSet is a multichannel, high-speeddata converter and is suitable for connection to the HF orIF ports of a communications or radar system. Its built-indata capture features offer an ideal turnkey solution as well asa platform for developing and deploying custom FPGA-processing IP.

It includes four 250 MHz, 16-bit A/Ds, one digitalupconverter, two 800 MHz, 16-bit D/As, and four banksof memory. In addition to supporting PCIe Gen. 3 as anative interface, the Model 5973-312 includes optionalcopper and optical connections to the Virtex-7 FPGA forcustom I/O.

When delivered as an assembled board set, the 5973-312includes factory-installed applications ideally matched tothe board’s analog interfaces. The functions include four A/Dacquisition IP modules for simplifying data capture and datatransfer. Each of the four acquisition IP modules contains IPmodules for DDR3 SDRAM memories.

The 5973-312 features a sophisticated D/A waveformplayback IP module. A linked-list controller allows users toeasily play back to the D/As waveforms stored in either on-board or off-board host memory. Parameters includinglength of waveform, delay from playback trigger, waveformrepetition, etc. can be programmed for each waveform. Upto 64 individual link entries can be chained together tocreate complex waveforms with a minimum of programming.

A controller for all data clocking and synchronizationfunctions, a test signal generator, and a PCIe interfacecomplete the factory-installed functions and enable the5973-312 to operate as a turnkey solution without theneed to develop any FPGA IP.

http://pentek.com/products/Detail.cfm?Model=5973-312




4848484848


Figure 54


88888-----ChChChChChannelannelannelannelannel 2 2 2 2 25050505050 MHz MHz MHz MHz MHz A/DA/DA/DA/DA/D with Vir with Vir with Vir with Vir with Virtex-7 FPGA - 3U VPXtex-7 FPGA - 3U VPXtex-7 FPGA - 3U VPXtex-7 FPGA - 3U VPXtex-7 FPGA - 3U VPX


PCIe INTERFACE

fromA/D Ch 1

PCIe

8X








METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

toMem

Bank 1

toMem

Bank 1

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MEMORYCONTROLMUX MUX MUX

INPUT MULTIPLEXER

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

TESTSIGNAL

GENERATOR

8XFPGAGPIO

32MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D Acq

Mod 1 & 2

toA/D Acq

Mod 3 & 4

toA/D Acq

Mod 5 & 6

toA/D Acq

Mod 7 & 8

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

fromA/D Ch 5

fromA/D Ch 6

fromA/D Ch 7

fromA/D Ch 8


3 - 7

GigabitSerial I/O

4X

See page 28

Model 5973-316


As a FlexorSet integrated solution, the Model 3316FMC is factory-installed on the 5973 FMC carrier. Therequired FPGA IP is installed and the board set is deliveredready for immediate use.

The delivered FlexorSet is a multichannel, high-speeddata converter and is suitable for connection to the HF orIF ports of a communications or radar system. Its built-indata capture features offer an ideal turnkey solution as wellas a platform for developing and deploying customFPGA-processing IP.

It includes eight A/Ds and four banks of memory. Inaddition to supporting PCIe Gen. 3 as a native interface,the Model 5973-316 includes optional copper and opticalconnections to the Virtex-7 FPGA for custom I/O.

When delivered as an assembled board set, the5973-316 includes factory-installed applications ideallymatched to the board’s analog interfaces. The functionsinclude eight A/D acquisition IP modules for simplifyingdata capture and data transfer.

Each of the eight acquisition IP modules contains IPmodules for DDR3 SDRAM memories. A controllerfor all data clocking and synchronization functions, atest signal generator, and a PCIe interface complete thefactory-installed functions and enable the 5973-316 tooperate as a turnkey solution without the need to developany FPGA IP.

For applications that require specialized functions,users can install their own custom IP for data processing.Pentek GateFlow® FPGA Design Kits include all of thefactory-installed modules as documented source code.Developers can integrate their own IP with the Pentekfactory-installed functions or use the GateFlow kit tocompletely replace the Pentek IP with their own.





4949494949


88888-----ChChChChChannelannelannelannelannel 2 2 2 2 25050505050 MHz MHz MHz MHz MHz A/DA/DA/DA/DA/D with Digital Downconver with Digital Downconver with Digital Downconver with Digital Downconver with Digital Downconverters - 3U VPXters - 3U VPXters - 3U VPXters - 3U VPXters - 3U VPX

Figure 55

See page 28

Model 5973-317

PCIe INTERFACE

fromA/D Ch 1

PCIe

8X








METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

MUX MUX MUX




INPUT MULTIPLEXER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

DDC CORE DDC CORE DDC CORE

TESTSIGNAL

GENERATOR


8XFPGAGPIO

32MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D Acq

Mod 1 & 2

toA/D Acq

Mod 3 & 4

toA/D Acq

Mod 5 & 6

toA/D Acq

Mod 7 & 8

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

fromA/D Ch 5

fromA/D Ch 6

fromA/D Ch 7

fromA/D Ch 8


3 - 7

GigabitSerial I/O

4X





The delivered FlexorSet is a multichannel, high-speeddata converter with programmable DDCs (DigitalDownconverters) and is suitable for connection to theHF or IF ports of a communications or radar system. Itsbuilt-in data capture features offer an ideal turnkey solutionas well as a platform for developing and deploying customFPGA-processing IP.

The Model 5973-317 includes eight A/Ds and fourbanks of memory. In addition to supporting PCIe Gen. 3as a native interface, it includes optional copper and opticalconnections to the Virtex-7 FPGA for custom I/O.


Within each A/D Acquisition IP Module is a powerfulDDC IP core. Each DDC has an independent 32-bittuning frequency setting that ranges from DC to ƒs, whereƒs is the A/D sampling frequency. Each DDC can haveits own unique decimation setting, supporting as many aseight different output bandwidths for the board. Decimationscan be programmed from 2 to 65,536 providing a wide rangeto satisfy most applications.

The decimating filter for each DDC accepts aunique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*ƒs/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% outputbandwidth is better than 100 dB.





5050505050


Figure 56


44444-----ChChChChChannelannelannelannelannel 500500500500500 MHz MHz MHz MHz MHz 16-bit 16-bit 16-bit 16-bit 16-bit A/DA/DA/DA/DA/D, 4-, 4-, 4-, 4-, 4-Channel 2 GHz 16-bit D/A - 3U VPXChannel 2 GHz 16-bit D/A - 3U VPXChannel 2 GHz 16-bit D/A - 3U VPXChannel 2 GHz 16-bit D/A - 3U VPXChannel 2 GHz 16-bit D/A - 3U VPX


PCIe INTERFACE

D/AWAVEFORMPLAYBACK

IP MODULE 4

D/AWAVEFORMPLAYBACK

IP MODULE 1

FromA/D Ch 1

FromA/D Ch 2

FromA/D Ch 3

FromA/D Ch 4

ToD/A Ch 4

ToD/A Ch 1

ToD/A Ch 2

GigabitSerial I/OPCIe

FPGAGPIO

D/A loopback

D/A loopback




DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX



DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUXMUX



toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROL

MEMORYCONTROL

8X 4X32


2 & 3

2 goes toMem Bank 1

3 goes toMem Bank 2

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

To A/D AcqModules 1 & 2


To D/A PlaybackModules 1 & 2


D/AWAFEFORMPLAYBACK

IP MODULES2 & 3

2 goes toMem Bank 3

3 goes toMem Bank 4

ToD/A Ch3

Model 5973-324

See page 28



The delivered FlexorSet is a multichannel, high-speeddata converter and is suitable for connection to the HF orIF ports of a communications or radar system. Its built-indata capture and playback features offer an ideal turnkeysolution as well as a platform for developing and deploy-ing custom FPGA-processing IP.

It includes four 500 MHz, 16-bit A/Ds, four digitalupconverters, four 2 GHz, 16-bit D/As, and four banks ofmemory. In addition to supporting PCIe Gen. 3 as a nativeinterface, the Model 5973-324 includes optional copper andoptical connections to the Virtex-7 FPGA for custom I/O.

When delivered as an assembled board set, the 5973-324includes factory-installed applications ideally matched tothe board’s analog interfaces. The functions include fourA/D acquisition IP modules for simplifying data captureand data transfer. Each of the four acquisition IP modulescontains IP modules for DDR3 SDRAM memories.

The 5973-324 features four sophisticated D/A waveformplayback IP modules. A linked-list controller allows usersto easily play back to the D/As waveforms stored in eitheron-board or off-board host memory. Parameters includinglength of waveform, delay from playback trigger, waveformrepetition, etc. can be programmed for each waveform. In eachplayback module, up to 64 individual link entries can bechained together to create complex waveforms with a minimumof programming.

A controller for all data clocking and synchronizationfunctions, a test signal generator, and a PCIe interface completethe factory-installed functions and enable the 5973-324 to operateas a turnkey solution without the need to develop any FPGA IP.





5151515151


Figure 57

44444-----ChChChChChannelannelannelannelannel 2 2 2 2 25050505050 MHz MHz MHz MHz MHz A/DA/DA/DA/DA/D, 2-, 2-, 2-, 2-, 2-Channel 800 MHz D/A - x8 PCIeChannel 800 MHz D/A - x8 PCIeChannel 800 MHz D/A - x8 PCIeChannel 800 MHz D/A - x8 PCIeChannel 800 MHz D/A - x8 PCIe


PCIe INTERFACE

D/AWAVEFORMPLAYBACKIP MODULE

fromA/D Ch 1

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

toD/A

PCIeFPGAGPIO

D/A loopback




DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX



DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUX


toMem

Bank 1

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

8X 32


2 & 3

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D AcqModule 1

toA/D AcqModule 2

toA/D AcqModule 3

toA/D AcqMod 4 &D/A Mod

See page 28

Model 7070-312

Model 7070-312 is a member of the Flexor family ofhigh-performance PCIe boards based on the XilinxVirtex-7 FPGA.


The delivered FlexorSet is a multichannel, high-speeddata converter and is suitable for connection to the HF orIF ports of a communications or radar system. Its built-indata capture features offer an ideal turnkey solution as well asa platform for developing and deploying custom FPGA-processing IP.

It includes four 250 MHz, 16-bit A/Ds, one digitalupconverter, two 800 MHz, 16-bit D/As, and four banks ofmemory. In addition to supporting PCIe Gen. 3 as a nativeinterface, the Model 7070-312 includes optional copperand optical connections to the Virtex-7 FPGA for custom I/O.

When delivered as an assembled board set, the 7070-312includes factory-installed applications ideally matched tothe board’s analog interfaces. The functions include four A/Dacquisition IP modules for simplifying data capture and datatransfer. Each of the four acquisition IP modules containsIP modules for DDR3 SDRAM memories.

The 7070-312 features a sophisticated D/A waveformplayback IP module. A linked-list controller allows usersto easily play back to the D/As waveforms stored in eitheron-board or off-board host memory. Parameters includinglength of waveform, delay from playback trigger, waveformrepetition, etc. can be programmed for each waveform. Up to64 individual link entries can be chained together to createcomplex waveforms with a minimum of programming.

A controller for all data clocking and synchronizationfunctions, a test signal generator, and a PCIe interfacecomplete the factory-installed functions and enable the7070-312 to operate as a turnkey solution without theneed to develop any FPGA IP.






5252525252


Figure 58


88888-----ChChChChChannelannelannelannelannel 2 2 2 2 25050505050 MHz MHz MHz MHz MHz A/DA/DA/DA/DA/D with Vir with Vir with Vir with Vir with Virtex-7 FPGA - x8 PCIetex-7 FPGA - x8 PCIetex-7 FPGA - x8 PCIetex-7 FPGA - x8 PCIetex-7 FPGA - x8 PCIe


PCIe INTERFACE

fromA/D Ch 1

PCIe

8X








METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATOR

toMem

Bank 1

toMem

Bank 1

toMem

Bank 4

MEMORYCONTROL

MEMORYCONTROL

MEMORYCONTROLMUX MUX MUX

INPUT MULTIPLEXER

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

DATAPACKING& FLOW

CONTROL

TESTSIGNAL

GENERATOR

8XFPGAGPIO

32MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D Acq

Mod 1 & 2

toA/D Acq

Mod 3 & 4

toA/D Acq

Mod 5 & 6

toA/D Acq

Mod 7 & 8

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

fromA/D Ch 5

fromA/D Ch 6

fromA/D Ch 7

fromA/D Ch 8


3 - 7

See page 28

Model 7070-316



The delivered FlexorSet is a multichannel, high-speeddata converter and is suitable for connection to the HF orIF ports of a communications or radar system. Its built-indata capture features offer an ideal turnkey solution aswell as a platform for developing and deploying customFPGA-processing IP.



Each of the eight acquisition IP modules containsIP modules for DDR3 SDRAM memories. A controllerfor all data clocking and synchronization functions, atest signal generator, and a PCIe interface complete thefactory-installed functions and enable the 7070-316 tooperate as a turnkey solution without the need todevelop any FPGA IP.

For applications that require specialized functions,users can install their own custom IP for data processing.Pentek GateFlow FPGA Design Kits include all of thefactory-installed modules as documented source code.Developers can integrate their own IP with the Pentekfactory-installed functions or use the GateFlow kit tocompletely replace the Pentek IP with their own.





5353535353


88888-----ChChChChChannelannelannelannelannel 2 2 2 2 25050505050 MHz MHz MHz MHz MHz A/DA/DA/DA/DA/D with Digital Downconver with Digital Downconver with Digital Downconver with Digital Downconver with Digital Downconverters - x8 PCIeters - x8 PCIeters - x8 PCIeters - x8 PCIeters - x8 PCIe

See page 28

Model 7070-317



PCIe INTERFACE

fromA/D Ch 1

PCIe

8X








METADATAGENERATOR

METADATAGENERATOR

METADATAGENERATORto

MemBank 1

MEMORYCONTROL

toMem

Bank 1

MEMORYCONTROL

toMem

Bank 4

MEMORYCONTROL

MUX MUX MUX




INPUT MULTIPLEXER

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

DDCDEC: 2 TO 65536

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

POWERMETER &

THRESHOLDDETECT

DDC CORE DDC CORE DDC CORE

TESTSIGNAL

GENERATOR


8XFPGAGPIO

32MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32

toA/D Acq

Mod 1 & 2

toA/D Acq

Mod 3 & 4

toA/D Acq

Mod 5 & 6

toA/D Acq

Mod 7 & 8

fromA/D Ch 2

fromA/D Ch 3

fromA/D Ch 4

fromA/D Ch 5

fromA/D Ch 6

fromA/D Ch 7

fromA/D Ch 8


3 - 7

Figure 59



The delivered FlexorSet is a multichannel, high-speeddata converter with programmable DDCs (DigitalDownconverters) and is suitable for connection to theHF or IF ports of a communications or radar system. Itsbuilt-in data capture features offer an ideal turnkey solutionas well as a platform for developing and deploying customFPGA-processing IP.



Within each A/D Acquisition IP Module is a powerfulDDC IP core. Each DDC has an independent 32-bittuning frequency setting that ranges from DC to ƒs, whereƒs is the A/D sampling frequency. Each DDC can haveits own unique decimation setting, supporting as many aseight different output bandwidths for the board. Decimationscan be programmed from 2 to 65,536 providing a wide rangeto satisfy most applications.

The decimating filter for each DDC accepts aunique set of user-supplied 18-bit coefficients. The 80%default filters deliver an output bandwidth of 0.8*ƒs/N,where N is the decimation setting. The rejection ofadjacent-band components within the 80% outputbandwidth is better than 100 dB.





5454545454


Figure 60


44444-----ChChChChChannelannelannelannelannel 500500500500500 MHz MHz MHz MHz MHz 16-bit 16-bit 16-bit 16-bit 16-bit A/DA/DA/DA/DA/D, 4-, 4-, 4-, 4-, 4-Channel 2 GHz 16-bit D/A - x8 PCIeChannel 2 GHz 16-bit D/A - x8 PCIeChannel 2 GHz 16-bit D/A - x8 PCIeChannel 2 GHz 16-bit D/A - x8 PCIeChannel 2 GHz 16-bit D/A - x8 PCIe


PCIe INTERFACE

D/AWAVEFORMPLAYBACK

IP MODULE 4

D/AWAVEFORMPLAYBACK

IP MODULE 1

FromA/D Ch 1

FromA/D Ch 2

FromA/D Ch 3

FromA/D Ch 4

ToD/A Ch 4

ToD/A Ch 1

ToD/A Ch 2

PCIeFPGAGPIO

D/A loopback

D/A loopback




DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX



DATAPACKING& FLOW

CONTROL

METADATAGENERATOR

MUX

INPUT MULTIPLEXER

DATAUNPACKING

& FLOWCONTROL

DATAUNPACKING

& FLOWCONTROL

TESTSIGNAL

GENERATOR

MUXMUX



toMem

Bank 1

MEMORYCONTROL

toMem

Bank 2

MEMORYCONTROL

toMem

Bank 4

toMem

Bank 3

MEMORYCONTROL

MEMORYCONTROL

8X32


2 & 3

2 goes toMem Bank 1

3 goes toMem Bank 2

MemoryBank 4

32MemoryBank 3

32MemoryBank 2

32MemoryBank 1

32





D/AWAFEFORMPLAYBACK

IP MODULES2 & 3

2 goes toMem Bank 3

3 goes toMem Bank 4

ToD/A Ch3

Model 7070-324

See page 28

Model 7070-324 is a member of the Flexor familyof high-performance PCIe boards based on the XilinxVirtex-7 FPGA.


The delivered FlexorSet is a multichannel, high-speeddata converter and is suitable for connection to the HF orIF ports of a communications or radar system. Its built-indata capture and playback features offer an ideal turnkeysolution as well as a platform for developing and deploy-ing custom FPGA-processing IP.

It includes four 500 MHz, 16-bit A/Ds, four digitalupconverters, four 2 GHz, 16-bit D/As, and four banks ofmemory. In addition to supporting PCIe Gen. 3 as a nativeinterface, the Model 7070-324 includes optional copper andoptical connections to the Virtex-7 FPGA for custom I/O.

When delivered as an assembled board set, the 7070-324includes factory-installed applications ideally matched tothe board’s analog interfaces. The functions include four A/Dacquisition IP modules for simplifying data capture and datatransfer. Each of the four acquisition IP modules contains IPmodules for DDR3 SDRAM memories.

The 7070-324 features four sophisticated D/A waveformplayback IP modules. A linked-list controller allows usersto easily play back to the D/As waveforms stored in eitheron-board or off-board host memory. Parameters includinglength of waveform, delay from playback trigger, waveformrepetition, etc. can be programmed for each waveform. In eachplayback module, up to 64 individual link entries can bechained together to create complex waveforms with aminimum of programming.

A controller for all data clocking and synchronizationfunctions, a test signal generator and a PCIe interface complete thefactory-installed functions and enable the 7070-324 to operate as aturnkey solution without the need to develop any FPGA IP.





5555555555


Figure 61


Model 8266 Model 8266 Model 8266 Model 8266 Model 8266

PC Development System for PCIe Cobalt, Onyx and Flexor BoardsPC Development System for PCIe Cobalt, Onyx and Flexor BoardsPC Development System for PCIe Cobalt, Onyx and Flexor BoardsPC Development System for PCIe Cobalt, Onyx and Flexor BoardsPC Development System for PCIe Cobalt, Onyx and Flexor Boards

The Model 8266 is a fully-integrated PC develop-ment system for Pentek Cobalt, Onyx and Flexor PCIExpress software radio, data acquisition, and I/O boards.It was created to save engineers and system integratorsthe time and expense associated with building and testing adevelopment system that ensures optimum performanceof Pentek boards.

A fully-integrated system-level solution, the 8266provides the user with a streamlined out-of-the-boxexperience. It comes preconfigured with Pentek hardware,drivers and software examples installed and tested to allowdevelopment engineers to run example applications outof the box.

Pentek ReadyFlow drivers and board supportlibraries are preinstalled and tested with the 8266.ReadyFlow includes example applications with fullsource code, a command line interface for custom

control over hardware, and Pentek’s Signal Analyzer, afull-featured analysis tool that continuously displays livesignals in both time and frequency domains.

Built on a professional 4U rackmount workstation,the 8266 is equipped with the latest Intel processor,DDR3 SDRAM and a high-performance motherboard.These features accelerate application code developmentand provide unhindered access to the high-bandwidthdata available with Cobalt, Onyx and Flexor analog anddigital interfaces. The 8266 can be configured with64-bit Windows or Linux operating systems.

The 8266 uses a 19” 4U rackmount chassis thatis 21” deep. Enhanced forced-air ventilation assuresadequate cooling for Pentek boards. A 1000-W powersupply guarantees more than enough power foradditional boards.

Model 8266





5656565656




Figure 62

3U OpenVPX Development System for Cobalt, Onyx and Flexor Boards3U OpenVPX Development System for Cobalt, Onyx and Flexor Boards3U OpenVPX Development System for Cobalt, Onyx and Flexor Boards3U OpenVPX Development System for Cobalt, Onyx and Flexor Boards3U OpenVPX Development System for Cobalt, Onyx and Flexor Boards

Model 8267

The Model 8267 is a fully-integrated, 3U OpenVPXdevelopment system for Pentek Cobalt, Onyx and Flexorsoftware radio, data acquisition, and I/O boards. It wascreated to save engineers and system integrators the timeand expense associated with building and testing a develop-ment system that ensures optimum performance ofPentek boards.


Pentek ReadyFlow drivers and board support librariesare preinstalled and tested with the 8267. ReadyFlowincludes example applications with full source code, acommand line interface for custom control over

hardware, and Pentek’s Signal Analyzer, a full-featuredanalysis tool that continuously displays live signals inboth time and frequency domains.

Built on a professional 4U rackmount workstation,the 8267 is equipped with the latest Intel i7 processor,DDR3 SDRAM and a high-performance single-boardcomputer. These features accelerate application codedevelopment and provide unhindered access to the high-bandwidth data available with Cobalt, Onyx and Flexoranalog and digital interfaces. The 8267 can be config-ured with 64-bit Windows or Linux operating systems.

The 8267 uses a 19” 4U rackmount chassis that is12” deep. Nine VPX slots provide ample space for anSBC, a switch card and multiple Pentek boards. Enhancedforced-air ventilation assures adequate cooling for allboards and dual 250-W power supplies gurantee morethan adequate power for all installed boards.





5757575757


Figure 63



6U OpenVPX Development System for Cobalt and Onyx Boards6U OpenVPX Development System for Cobalt and Onyx Boards6U OpenVPX Development System for Cobalt and Onyx Boards6U OpenVPX Development System for Cobalt and Onyx Boards6U OpenVPX Development System for Cobalt and Onyx Boards

Model 8264

with 6U OpenVPX Boards

The Model 8264 is a fully-integrated, 6U OpenVPXdevelopment system for Pentek Cobalt and Onyx soft-ware radio, data acquisition, and I/O boards. It was createdto save engineers and system integrators the time andexpense associated with building and testing a develop-ment system that ensures optimum performance ofPentek boards.


Pentek ReadyFlow drivers and board supportlibraries are preinstalled and tested with the 8264. Ready-Flow includes example applications with full source code,a command line interface for custom control over

hardware, and Pentek’s Signal Analyzer, a full-featuredanalysis tool that continuously displays live signals inboth time and frequency domains.

Built on a professional 6U rackmount workstation,the 8264 is equipped with the latest Intel i7 processor,DDR3 SDRAM and a high-performance single-boardcomputer. These features accelerate application codedevelopment and provide unhindered access to the high-bandwidth data available with Cobalt and Onyx analogand digital interfaces. The 8264 can be configured with64-bit Windows or Linux operating systems.

The 8264 uses a 19” 6U rackmount chassis that is12” deep. Nine VPX slots provide ample space for anSBC, a switch card and multiple Pentek boards. Enhancedforced-air ventilation assures adequate cooling for allboards and dual 500-W power supplies gurantee morethan adequate power for all installed boards.





5858585858


ReferenceIn

Control

PCI INTERFACE

Clock Out1

Clock Out2

Clock Out3

Clock Out4

Clock Out5

Clock Out6

Clock Out7

Clock Out8

CLOCKSYNTHESIZER

AND JITTERCLEANER

A

1÷÷ 2÷ 4÷ 8÷16

QUADVCXO

A

CLOCKSYNTHESIZER

AND JITTERCLEANER

B

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

C

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

D

1÷÷ 2÷ 4÷ 8÷16

Supports:any In to any Out,any In to multiple

Outs

CROSSBAR

SWITCH

In

In

In

In

Out

Out

Out

Out

Out

QUADVCXO

B

QUADVCXO

C

QUADVCXO

D

32 PCI TO PCIeBRIDGE

x4 PCIe x4 PCIe

VPX BACKPLANE

Model 5790


except the PCIe-to-PCIe Switch

Block Diagram,PCIe

Gen. 2 x4

VPX-P1

PCIe-to-PCIeSWITCH



Figure 64

Multifrequency Clock SynthesizerMultifrequency Clock SynthesizerMultifrequency Clock SynthesizerMultifrequency Clock SynthesizerMultifrequency Clock Synthesizer

Model 58906U VPX

double density

Model 5890 6U VPX generates 16 synthesized clocksignals suitable for driving A/D and D/A converters inhigh-performance real-time data acquisition and softwareradio systems. The clocks offer exceptionally low phase noiseand jitter to preserve the signal quality of the data converters.These clocks are synthesized from on-board quad VCXOsand can be phase-locked to an external reference signal.

The 5890 uses eight Texas Instruments CDC7005clock synthesizer and jitter cleaner devices. Each CDC7005 ispaired with a dedicated VCXO to provide the base frequencyfor the clock synthesizer. Each of the eight VCXOs can beindependently programmed to generate one of eightfrequencies between 50 MHz and 700 MHz.

The CDC7005 can output the selected frequencyof its associated VCXO, or generate submultiples usingdivisors of 2, 4, 8 or 16. The eight CDC7005’s can outputup to five frequencies each. The 5890 can be programmed toroute any of these 40 frequencies to the board’s 10 outputdrivers.

The CDC7005 includes phase-locking circuitrythat locks the frequency of its associated VCXO to an inputreference of 5 MHz to 100 MHz.

Front panel SMC connectors supply synthesized clockoutputs driven from the clock output drivers. This supportsa single identical clock to all outputs or up to ten differentclocks to various outputs. With four independent quadVCXOs and each CDC7005 capable of providing up tofive different submultiple clocks, a wide range of clockconfigurations is possible. In systems where more than 10different clock outputs are required simultaneously, multiple5890’s can be used and phase-locked with the 5 MHz to100 MHz system reference.

Versions of the 5890 are also available as a 6U VPXboard (Model 5790 single density), 3U VPX board (Model5390), PMC (Model 7191), PCIe board (Model 7890),AMC (Model 5690) PCI board (Model 7690), 6U cPCI(Models 7290 and 7290D dual density), and 3U cPCI(Model 7390).

Models 5890, 5790 6U VPX Models 5890, 5790 6U VPX Models 5890, 5790 6U VPX Models 5890, 5790 6U VPX Models 5890, 5790 6U VPX ●●●●● Model 5390 3U VPX Model 5390 3U VPX Model 5390 3U VPX Model 5390 3U VPX Model 5390 3U VPX ●●●●● Model 7190 PMC Model 7190 PMC Model 7190 PMC Model 7190 PMC Model 7190 PMC ●●●●● Model 7890 PCIe Model 7890 PCIe Model 7890 PCIe Model 7890 PCIe Model 7890 PCIeModel 5690 AMC Model 5690 AMC Model 5690 AMC Model 5690 AMC Model 5690 AMC ●●●●● Model 7690 PCI Model 7690 PCI Model 7690 PCI Model 7690 PCI Model 7690 PCI ● ● ● ● ● Models 7290, 7290D 6U cPCI Models 7290, 7290D 6U cPCI Models 7290, 7290D 6U cPCI Models 7290, 7290D 6U cPCI Models 7290, 7290D 6U cPCI ●●●●● Model 7390 3U cPCI Model 7390 3U cPCI Model 7390 3U cPCI Model 7390 3U cPCI Model 7390 3U cPCI







http://pentek.com/products/Detail.cfm?Model=7290D





5959595959


ReferenceIn

Control

PCI INTERFACE

Clock Out1

Clock Out2

Clock Out3

Clock Out4

Clock Out5

Clock Out6

Clock Out7

Clock Out8

CLOCKSYNTHESIZER

AND JITTERCLEANER

A

1÷÷ 2÷ 4÷ 8÷16

PROGRAMVCXO

A

CLOCKSYNTHESIZER

AND JITTERCLEANER

B

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

C

1÷÷ 2÷ 4÷ 8÷16

CLOCKSYNTHESIZER

AND JITTERCLEANER

D

1÷÷ 2÷ 4÷ 8÷16

Supports:any In to any Out,any In to multiple

Outs

CROSSBAR

SWITCH

In

In

In

In

Out

Out

Out

Out

Out

PROGRAMVCXO

B

PROGRAMVCXO

C

PROGRAMVCXO

D

32 PCI TO PCIeBRIDGE

PCI EXPRESS SWITCHPEX 8648

x4 PCIe

4XGbit

Serial

4XGbit

Serial

4XGbit

Serial

4XGbit

Serial

VPX BACKPLANE

CROSSBARSWITCH

VPX-P1

24 lanes / 6 portseach configurableas x1/x4/x8/x16

24

Figure 65

Model 5391 3U VPX Model 5391 3U VPX Model 5391 3U VPX Model 5391 3U VPX Model 5391 3U VPX ●●●●● Models 5791, 5891 6U VPX Models 5791, 5891 6U VPX Models 5791, 5891 6U VPX Models 5791, 5891 6U VPX Models 5791, 5891 6U VPX ● ● ● ● ● Model 7191 PMC Model 7191 PMC Model 7191 PMC Model 7191 PMC Model 7191 PMC ●●●●● Model 7891 PCIe Model 7891 PCIe Model 7891 PCIe Model 7891 PCIe Model 7891 PCIeModel 5691 AMC Model 5691 AMC Model 5691 AMC Model 5691 AMC Model 5691 AMC ●●●●● Model 7691 PCI Model 7691 PCI Model 7691 PCI Model 7691 PCI Model 7691 PCI ● ● ● ● ● Model 7291 6U cPCI Model 7291 6U cPCI Model 7291 6U cPCI Model 7291 6U cPCI Model 7291 6U cPCI ●●●●● Model 7391 3U cPCI Model 7391 3U cPCI Model 7391 3U cPCI Model 7391 3U cPCI Model 7391 3U cPCI

Model 5391 generates up to eight synthesized clocksignals suitable for driving A/D and D/A converters inhigh-performance real-time data acquisition and softwareradio systems. The clocks offer exceptionally low phase noiseand jitter to preserve the signal quality of the data converters.These clocks are synthesized from programmable VCXOsand can be phase-locked to an external reference signal.

The 5391 uses four Texas Instruments CDC7005 clocksynthesizer and jitter cleaner devices. Each CDC7005 is pairedwith a dedicated VCXO to provide the base frequency forthe clock synthesizer. Each of the four VCXOs can beindependently programmed to a desired frequency between50 MHz and 700 MHz with 32-bit tuning resolution.

The CDC7005 can output the programmed frequencyof its associated VCXO, or generate submultiples usingdivisors of 2, 4, 8 or 16. The four CDC7005’s can outputup to five frequencies each. The 5391 can be programmed toroute any of these 20 frequencies to the board’s fiveoutput drivers.

The CDC7005 includes phase-locking circuitrythat locks the frequency of its associated VCXO to an inputreference of 5 MHz to 100 MHz.

Eight front panel SMC connectors supply synthesizedclock outputs driven from the five clock output drivers.This supports a single identical clock to all eight outputs orup to five different clocks to various outputs. With fourprogrammable VCXOs and each CDC7005 capable ofproviding up to five different submultiple clocks, awide range of clock configurations is possible. In systemswhere more than five different clock outputs are requiredsimultaneously, multiple 5391’s can be used and phase-locked with the 5 MHz to 100 MHz system reference.

Versions of the 5391 are also available as 6U VPX(Models 5791 and 5891 with dual density), PMC(Model 7191), PCIe board (Model 7891), AMC (Model5691), PCI board (Model 7691), 6U cPCI (Models 7291and 7291D dual density), or 3U cPCI (Model 7391).

PPPPProgrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizerrogrammable Multifrequency Clock Synthesizer

Model 53913U VPX







http://pentek.com/products/Detail.cfm?Model=7291D






6060606060


Figure 66

Model 5292 3U VPX Model 5292 3U VPX Model 5292 3U VPX Model 5292 3U VPX Model 5292 3U VPX ●●●●● Models 5792, 5892 6U VPX Models 5792, 5892 6U VPX Models 5792, 5892 6U VPX Models 5792, 5892 6U VPX Models 5792, 5892 6U VPX ● ● ● ● ● Model 7192 PMC/XMC Model 7192 PMC/XMC Model 7192 PMC/XMC Model 7192 PMC/XMC Model 7192 PMC/XMC ●●●●● Model 7892 PCIe Model 7892 PCIe Model 7892 PCIe Model 7892 PCIe Model 7892 PCIeModel 5692 AMC Model 5692 AMC Model 5692 AMC Model 5692 AMC Model 5692 AMC ●●●●● Models 7292, 7492 6U cPCI Models 7292, 7492 6U cPCI Models 7292, 7492 6U cPCI Models 7292, 7492 6U cPCI Models 7292, 7492 6U cPCI ●●●●● Model 7392 3U cPCI Model 7392 3U cPCI Model 7392 3U cPCI Model 7392 3U cPCI Model 7392 3U cPCI

High-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution BoardHigh-Speed Synchronizer and Distribution Board


PLL&

DIVIDER

Gate / Trigger Out

Sample Clk /Reference

Clk InMUX

ClkIn

RefIn

:N

PROGRAMMABLEVCXO

Clock /Calibration Out

:N

BUFFER&

PROGRAMDELAYS

Clk/RefIn

Sync OutReference Clk Out

TWSI Control InReference Clk In *

Gate / Trigger OutSync OutReference Clk Out

MUX

Trig/GateIn

SyncIn

TWSICONTROL



Gate / Trigger In

Sync In

�Sync 3

�Sync 2

�Sync 1

�Sync 4

* For 71640 A/D calibration

The Model 5292 High-Speed Synchronizer andDistribution Board synchronizes multiple Pentek Cobaltor Onyx modules within a system. It enables synchronoussampling and timing for a wide range of multichannelhigh-speed data acquisition, DSP, and software radioapplications. Up to four modules can be synchronizedusing the 5292, with each receiving a common clockalong with timing signals that can be used for synchro-nizing, triggering and gating functions.

Model 5292 provides three front panel MMCXconnectors to accept input signals from external sources:one for clock, one for gate or trigger and one for a synchro-nization signal. Clock signals can be applied from anexternal source such as a high-performance sine-wavegenerator. Gate/trigger and sync signals can come froman external system source. In addition to the MMCXconnector, a reference clock can be accepted through thefirst front panel µSync output connector, allowing asingle Cobalt or Onyx board to generate the clock forall subsequent boards in the system.

The 5292 provides four front panel µSync outputconnectors, compatible with a range of high-speedPentek Cobalt and Onyx modules. The µSync signalsinclude a reference clock, gate/trigger and sync signals and aredistributed through matched cables, simplifying systemdesign. The 5292 features a calibration output specifi-cally designed to work with the 52640 or 527403.6 GHz A/D module and provide a signal reference forphase adjustment across multiple D/As.

The 5292 supports all high-speed models in the Cobaltand Onyx families including the 52630/52730 1 GHz A/Dand D/A 3U VPX, the 52640/52741 3.6 GHz A/D 3UVPX and the 52670/52771 Four-channel 1.25 GHz,16-bit D/A 3U VPX.

Versions of the 5292 are also available as 6U VPX(Models 5792 and 5892 dual density), PMC/XMC(Model 7192), PCIe board (Model 7892), AMC (Model5692), 6U cPCI (Models 7292 and 7492 dual density),and 3U cPCI (Model 7392).












6161616161


Model 5294 3U VPX Model 5294 3U VPX Model 5294 3U VPX Model 5294 3U VPX Model 5294 3U VPX ●●●●● Models 5794, 5894 6U VPX Models 5794, 5894 6U VPX Models 5794, 5894 6U VPX Models 5794, 5894 6U VPX Models 5794, 5894 6U VPX ● ● ● ● ● Model 7194 PMC/XMC Model 7194 PMC/XMC Model 7194 PMC/XMC Model 7194 PMC/XMC Model 7194 PMC/XMC ●●●●● Model 7894 PCIe Model 7894 PCIe Model 7894 PCIe Model 7894 PCIe Model 7894 PCIeModel 5694 AMC Model 5694 AMC Model 5694 AMC Model 5694 AMC Model 5694 AMC ●●●●● Models 7294, 7494 6U cPCI Models 7294, 7494 6U cPCI Models 7294, 7494 6U cPCI Models 7294, 7494 6U cPCI Models 7294, 7494 6U cPCI ●●●●● Model 7394 3U cPCI Model 7394 3U cPCI Model 7394 3U cPCI Model 7394 3U cPCI Model 7394 3U cPCI

High-Speed Clock GeneratorHigh-Speed Clock GeneratorHigh-Speed Clock GeneratorHigh-Speed Clock GeneratorHigh-Speed Clock Generator

Figure 67

FREQUENCYSYNTHESIZER

OVENSTABlLIZED

OSCILLATOR

Clock Out 1

ReferenceClock In

Clock Out 2

frequency setby board option

Clock Out 4

REFERENCECLOCK

IN

SAMPLECLOCK

OUT

POWERSPLITTER

ReferenceClock Out

Clock Out 3


Model 5294 High-Speed Clock Generator providesfixed-frequency sample clocks to Cobalt and Onyxboards in multiboard systems. It enables synchronoussampling, playback and timing for a wide range ofmultichannel high-speed data acquisition and softwareradio applications.

The Model 5294 uses a high-precision, fixed-frequency,PLO (Phase-Locked Oscillator) to generate an outputsample clock. The PLO accepts a 10 MHz referenceclock through a front panel SMA connector. The PLOlocks the output sample clock to the incoming reference.A power splitter then receives the sample clock anddistributes it to four front panel SMA connectors.

The 5294 is available with sample clock frequenciesfrom 1.4 to 2.0 GHz.

In addition to accepting a reference clock on the frontpanel, the 5294 includes an on-board 10 MHzreference clock. The reference is an OCXO (Oven-Controlled Crystal Oscillator), which provides anexceptionally precise frequency standard with excellentphase noise characteristics.

The 5294 is a standard 3U VPX board. The boarddoes not require programming and the VPX P1 or P2connector is used solely for power. The board can beoptionally configured with a PCIe-style 6-pin powerconnector allowing it to be used in virtually any chassisor enclosure.

Versions of the 5294 are also available as a 6U VPX(Models 5794 and 5894 with dual density), PMC/XMC(Model 7194), PCIe board (Model 7894), AMC(Model 5694), 6U cPCI (Models 7294 and 7494 dualdensity), and 3U cPCI (Model 7394).












6262626262


High-Speed System Synchronizer UnitHigh-Speed System Synchronizer UnitHigh-Speed System Synchronizer UnitHigh-Speed System Synchronizer UnitHigh-Speed System Synchronizer Unit

Model 9192 - RModel 9192 - RModel 9192 - RModel 9192 - RModel 9192 - Rackmountackmountackmountackmountackmount

PLL&

DIVIDER

Gate / Trigger Out

Sample Clk /Reference

Clk InMUX

ClkIn

RefIn

:N

PROGRAMMABLEVCXO

Clock Out 1

:N

BUFFER&

PROGRAMDELAYS

ClkRefIn

Sync OutReference Clk Out

TWSI Control InReference Clk In *


MUX

Trig/GateIn

SyncIn

TWSICONTROL


Gate / Trigger In

Sync In

�Sync 2

�Sync 1

�Sync 12

* For 71640 A/D calibration

�Sync 3through

�Sync 11

Clock Out 2

Clock Out 12

CLOCKSPLITTER

Clock Out 3throughClock Out 11

External Clk In

MUX

USB-TO-TWSIINTERFACE

USB

Model 9192

Model 9192 Rackmount High-Speed SystemSynchronizer Unit synchronizes multiple Pentek Cobalt orOnyx boards within a system. It enables synchronoussampling and timing for a wide range of multichannelhigh-speed data acquisition, DSP, and software radioapplications. Up to twelve boards can be synchronizedusing the 9192, each receiving a common clock alongwith timing signals that can be used for synchronizing,triggering and gating functions.

Model 9192 provides four rear panel SMA connec-tors to accept input signals from external sources: twofor clock, one for gate or trigger and one for a synchro-nization signal. Clock signals can be applied from anexternal source such as a high-performance sine-wavegenerator. Gate/trigger and sync signals can come from anexternal system source. In addition to the SMA connector,a reference clock can be accepted through the first rearpanel µSync output connector, allowing a single Cobaltor Onyx board to generate the clock for all subsequentboards in the system.

Figure 68

The 9192 provides four rear panel µSync outputconnectors, compatible with a range of high-speed PentekCobalt and Onyx boards. The µSync signals include areference clock, gate/trigger and sync signals and are distrib-uted through matched cables, simplifying system design.

The 9192 features twelve calibration outputsspecifically designed to work with the xx640 or xx7413.6 GHz A/D modules and provides a signal referencefor phase adjustment across multiple D/As.

The 9192 allows programming of operation parametersincluding: VCXO frequency, clock dividers, and delays thatallow the user to make timing adjustments on the gate andsync signals. These adjustments are made before they are sentto buffers for output through the µSync connectors.

The 9192 supports all high-speed models in the Cobaltfamily including the xx630 1 GHz A/D and D/A , the xx6403.6 GHz A/D and the xx670 Four-channel 1.25 GHz, 16-bitD/A. The 9192 also supports high-speed models of the Onyxfamily.






6363636363


High-Speed Recording Systems

Talon® High-Speed Recording Systems eliminate thetime and risk associated with new technology systemdevelopment. With increasing pressure in both the defenseand commercial arenas to get to the market first, today’ssystem engineers are looking for more complete off-the-shelfsystem offerings.

Out of the box, these systems arrive complete witha full-featured virtual operator control panel ready forimmediate data recording and/or playback operation.

Because they consist of modular COTS board-levelproducts and the flexible Pentek SystemFlow® software, theyare easily scalable to larger multichannel data acquisitionand recording applications requiring aggregate recordingrates of up to 5.0 GB/sec or more.

Ready-to-Run Recording Systems

Depending on model, the Pentek offerings are fullyintegrated systems featuring a range of A/D, D/A or digitalI/O resources with high-speed disk arrays.

While these systems are built on a Windows work-station and not an OpenVPX backplane, they are presentedin this section because they can easily satisfy a broadspectrum of recording needs. Furthermore, users caneasily install postprocessing and analysis tools to operateon the recorded data which are stored in the familiarNTFS format.

RTV Recording Systems areexcellent value for under

$20,000

RTS Recording Systems aredesigned for commercial

applications

RTR Recording Systems aredesigned for harsh

environments

RTX Recording Systems aredesigned for extreme

environments

TTTTTalonalonalonalonalon High-Speed RHigh-Speed RHigh-Speed RHigh-Speed RHigh-Speed Recording Systems: Flexible and Deployable Solutionsecording Systems: Flexible and Deployable Solutionsecording Systems: Flexible and Deployable Solutionsecording Systems: Flexible and Deployable Solutionsecording Systems: Flexible and Deployable Solutions

ANALOG RECORDERS

DIGITAL RECORDERS

Recording Systems Form Factors

Pentek’s High-Speed Recording Systems are available asLab Systems, Portable Systems, Rugged, and Extreme Systems.

RTV and RTS Lab Systems are housed in a 19-in. rack-mountable chassis in a PC server configuration. They aredesigned for commercial applications in a lab or office environ-ment.

RTR Portable Systems are available in a small briefcase-sized enclosures with integral LCD display and keyboard.They, too, provide a PC server configuration and are designedfor harsh environment field applications where size and weight isof paramount importance.

RTR Rugged Rackmount Systems are housed in a 19-in.rugged rack-mountable chassis. They are built to surviveshock and vibration and they target operation in harshenvironments and remote locations that may be unsuitablefor humans.

RTX Extreme Systems are available in a rackmountchassis designed to military specs. They are designed tooperate under extreme environmental conditions usingforced-air or conduction-cooling to draw heat from systemcomponents.

RTX Rackmountsystem

RTS Lab system

RTR Rackmountsystem

RTR Portable System


http://www.pentek.com/selectguide/REC_SelectGuide.cfm

http://www.pentek.com/selectguide/REC_DigSelectGuide.cfm


6464646464


PPPPPentek SystemFlow Rentek SystemFlow Rentek SystemFlow Rentek SystemFlow Rentek SystemFlow Recording Sofecording Sofecording Sofecording Sofecording Software for Analog Rtware for Analog Rtware for Analog Rtware for Analog Rtware for Analog Recordersecordersecordersecordersecorders

Figure 69

Signal Viewer

Recorder Interface Hardware Configuration

The Pentek SystemFlow Recording Software for AnalogRecorders provides a rich set of function libraries and toolsfor controlling all Pentek analog high-speed real-timerecording systems. SystemFlow software allows developersto configure and customize system interfaces and behavior.

The Recorder Interface shows a system block diagramand includes configuration, record, playback and statusscreens, each with intuitive controls and indicators. Theuser can easily move between screens to set configurationparameters, control and monitor a recording, play backa recorded signal and monitor board temperatures andvoltage levels.

The Hardware Configuration screen provides asimple and intuitive means for setting up the systemparameters. The configuration screen shown here, allowsuser entries for input source, center frequency, decima-tion, as well as gate and trigger information. All

parameters contain limit-checking and integrated helpto provide an easier-to-use out-of-the-box experience.

The SystemFlow Signal Viewer includes a virtualoscilloscope and spectrum analyzer for signal monitoringin both the time and frequency domains. It is extremelyuseful for previewing live inputs prior to recording, andfor monitoring signals as they are being recorded to helpensure successful recording sessions. The viewer can alsobe used to inspect and analyze the recorded files after therecording is complete.

Advanced signal analysis capabilities include automaticcalculators for signal amplitude and frequency, secondand third harmonic components, THD (total harmonicdistortion) and SINAD (signal to noise and distortion).With time and frequency zoom, panning modes and dualannotated cursors to mark and measure points of interest,the Signal Viewer can often eliminate the need for a separateoscilloscope or spectrum analyzer in the field.


http://www.pentek.com/systemflow/systemflow.cfm


6565656565


PPPPPentek SystemFlow Rentek SystemFlow Rentek SystemFlow Rentek SystemFlow Rentek SystemFlow Recording Sofecording Sofecording Sofecording Sofecording Software for Digital Rtware for Digital Rtware for Digital Rtware for Digital Rtware for Digital Recordersecordersecordersecordersecorders

Figure 70

The SystemFlow Main Interface for Digital Record-ers shows a block diagram of the system and provides theuser with a control interface for the recording system. Itincludes Configuration, Record, Playback, and Statusscreens, each with intuitive controls and indicators. Theuser can easily move between screens to set configurationparameters, control and monitor a recording, and play backa recorded stream.

The Configure screen presents operational systemparameters including temperature and voltages. Parametersare entered for each input or output channel specifyingUDP or TCP protocol, client or server connection, theIP address and port number. All parameters contain limit-checking and integrated help to provide an easier-to-useout-of-the-box experience.

The Record screen allows you to browse a folder andenter a file name for the recording. The length of therecording for each channel can be specified in megabytesor in seconds. Intuitive buttons for Record, Pause andStop simplify operation. Status indicators for eachchannel display the mode, the number of recorded bytes,and the average data rate. A Data Loss indicator alertsthe user to any problem, such as a disk- full condition.

By checking the Master Record boxes, any combina-tion of channels in the lower screen can be grouped forsynchronous recording via the upper Master Record screen.The recording time can be specified, and monitoringfunctions inform the operator of recording progress.

Record Screen

Main Interface Hardware Configuration


http://www.pentek.com/systemflow/systemflow.cfm


6666666666


AnalogInput

AnalogOutput

200 MHz16-bit A/D

DIGITALDOWN-

CONVERTERDecimation:2 to 65,536

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

4 TB DATA STORAGE

DATA DRIVES DATA DRIVES


MODEL RTV 2601

USB

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput

GPSAntenna(Optional)

800 MHz16-bit D/A

DIGITALUP-

CONVERTERDecimation:2 to 65,536

Figure 71

Model RTV 2601 Model RTV 2601 Model RTV 2601 Model RTV 2601 Model RTV 2601

200 MS/sec RF/IF R200 MS/sec RF/IF R200 MS/sec RF/IF R200 MS/sec RF/IF R200 MS/sec RF/IF Rackmount Rackmount Rackmount Rackmount Rackmount Recorderecorderecorderecorderecorder

The Talon RTV 2601 is a turnkey multibandrecording and playback system used for recording andreproducing signals with bandwidths up to 80 MHz.The RTV 2601 uses a 16-bit, 200 MHz A/D converterto provide real-time sustained recording rates to disk ofup to 400 MB/sec. The A/D is complemented with a16-bit 800 MHz D/A that provides the ability to reproducesignals captured in the field.

The RTV 2601 comes in a 4U 19 in. rackmountpackage that is 22.75 in. deep. Signal I/O is provided inthe rear of the unit, while the hot-swappable data drivesare available at the front. Air is pulled through the systemfrom front to back allowing it to operate at ambienttemperatures from 5 to 35 deg C.

The RTV 2601 includes a programmable digitaldownconverter so users can configure the system to capturesignals with frequencies as low as 300 kHz and as high as700 MHz. Corresponding signal bandwidths range from

a few kilohertz to 80 MHz. A digital upconverter andD/A produce an analog output matching the recordedIF signal frequency.

The system includes a built-in sample clocksynthesizer programmable to any desired frequencyfrom 10 MHz to 200 MHz. This clock synthesizer can belocked to an external 10 MHz reference clock and hasexcellent phase noise characteristics. Alternately, the usercan supply an external sample clock to drive the A/D andD/A converters. The RTV 2601 also supports externaltriggering, allowing users to trigger a recording or playbackon an external signal.

The RTV 2601 includes the Pentek SystemFlow record-ing software. SystemFlow features a Windows-based GUIthat provides a simple means to configure and control therecorder. Optionally, a GPS or IRIG receiver card can besupplied with the system for accurate time stamping ofrecorded data.

Model RTV 2601






6767676767


Figure 72

Model RTV 2602 Model RTV 2602 Model RTV 2602 Model RTV 2602 Model RTV 2602

Serial FPDP RSerial FPDP RSerial FPDP RSerial FPDP RSerial FPDP Rackmount Vackmount Vackmount Vackmount Vackmount Value Ralue Ralue Ralue Ralue Recorderecorderecorderecorderecorder

Model RTV 2602

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

4 TB DATA STORAGE



MODEL RTV 2602

USB

GigabitEthernet

Keyboard

Mouse

VideoOutput


ChannelsIn / Out Serial

FPDP

The Talon RTV 2602 Serial FPDP Value Recorder isdesigned to provide a low-cost solution to users looking tocapture and play back multiple Serial FPDP streams. Itcan record up to four Serial FPDP channels to the built-in 4 TB RAID consisting of cost-effective, enterprise-classHDD storage. It is a complete turnkey recording system,ideal for capturing any type of streaming sources. Theseinclude live transfers from sensors or data from othercomputers and is fully compatible with the VITA 17.1specification.

The RTV 2602 comes in a 4U 19 in. rack-mountpackage that is 22.75 in. deep. Signal I/O is provided inthe rear of the unit, while the hot-swappable data drivesare available in the front. Air is pulled through the systemfrom front to back to allow operation at ambienttemperatures from 5o to 35o C.

The RTV 2606 can be populated with up to four SFPconnectors supporting Serial FPDP over copper, single-

mode, or multi-mode fiber, to accommodate all popularSerial FPDP interfaces. It is capable of both receiving andtransmitting data over these links and supports real-timedata storage to disk.

Programmable modes include flow control in bothreceive and transmit directions, CRC support, and copy/loop modes. The system is capable of handling 1.0625,2.125, 2.5, 3.125 and 4.25 GBaud link rates. Up to fourchannels can be recorded simultaneously with an aggregaterecording rate of up to 400 MB/sec.

Optionally, a GPS or IRIG receiver card can besupplied with the system providing accurate time stampingof recorded data. Additionally, the GPS receiver deliversGPS position information that can be recorded along withthe input signals.

The RTV 2602 includes the Pentek SystemFlowrecording software which features a Windows-based GUI.






6868686868


Figure 73

USB

GigabitEthernet

Aux VideoVGA Output

MODEL RTR 2726

ChannelsIn

ChannelsOut

200 MHz16-bit A/D

DIGITAL DOWNCONVERTERDEC: 2 to 64K

800 MHz16-bit D/A

DIGITAL UPCONVERTER

INT: 2 to 512K

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

HIGH RESOLUTIONVIDEO DISPLAY

RAID DATA STORAGE



Model RTR 2726A RModel RTR 2726A RModel RTR 2726A RModel RTR 2726A RModel RTR 2726A Rugged Pugged Pugged Pugged Pugged Pororororortabletabletabletabletable ● ● ● ● ● Model RTS 2706 RModel RTS 2706 RModel RTS 2706 RModel RTS 2706 RModel RTS 2706 Rackmount Lackmount Lackmount Lackmount Lackmount Lab ab ab ab ab ● ● ● ● ● Model RTR 2746 RModel RTR 2746 RModel RTR 2746 RModel RTR 2746 RModel RTR 2746 RuggeduggeduggeduggeduggedRRRRRackmount ackmount ackmount ackmount ackmount ●●●●● Model RTX 2766 Extreme R Model RTX 2766 Extreme R Model RTX 2766 Extreme R Model RTX 2766 Extreme R Model RTX 2766 Extreme Rackmount ackmount ackmount ackmount ackmount ● ● ● ● ● Model RTX 2786 ½ AModel RTX 2786 ½ AModel RTX 2786 ½ AModel RTX 2786 ½ AModel RTX 2786 ½ ATRTRTRTRTR

The Talon RTR 2726A is a turnkey, multiband recordingand playback system that allows the user to record andreproduce high-bandwidth signals with lightweight, portableand rugged packages. This model provides aggregaterecording rates of up to 3.2 GB/sec and is ideal for theuser who requires both portability and solid perfor-mance in a compact recording system.

The RTR 2726A is supplied in a small footprint portablepackage measuring only 16.0" W x 6.9" D x 13.0" Hand weighing just less than 30 pounds.

With measurements similar to small briefcases, thisportable workstation includes Intel Core i7 processors,high-resolution 17" LCD monitors, and up to 15.3 TBof SSD storage.

A/D sampling rate, DDC decimation and bandwidth,D/A sampling rate and DUC interpolation are among

the GUI-selectable system parameters, that provide fully-programmable systems capable of recording and reproducinga wide range of signals.

Included with this system is Pentek’s SystemFlowrecording software. Built on a Windows 7 Professionalworkstation with high performance Intel Core i7 processor, thesystem allows the user to install post-processing andanalysis tools to operate on the recorded data. Theyrecord data to the native NTFS file system, providingimmediate access to the data. Custom configurationscan be stored as profiles and later loaded when needed,so users can select preconfigured settings with a single click.

Versions of the RTR 2726A are also available as aRackmount Lab unit (Model RTS 2706), Rugged Rackmount(Model RTR 2746), Extreme Rackmount (ModelRTX 2766).

200 MS/sec RF/IF 200 MS/sec RF/IF 200 MS/sec RF/IF 200 MS/sec RF/IF 200 MS/sec RF/IF RRRRRugged Pugged Pugged Pugged Pugged Pororororortable table table table table RRRRRecorderecorderecorderecorderecorder

Model RTR 2726A


http://pentek.com/products/Detail.cfm?Model=2726A







6969696969


22222555550 MS/sec0 MS/sec0 MS/sec0 MS/sec0 MS/sec RF/IF RF/IF RF/IF RF/IF RF/IF R R R R Rugged Rugged Rugged Rugged Rugged Rackmount Rackmount Rackmount Rackmount Rackmount Recorderecorderecorderecorderecorder

Figure 74

Model RTR 2750Model RTR 2750Model RTR 2750Model RTR 2750Model RTR 2750

ChannelsIn 250 MHz

16-bit A/D

DIGITALDOWN-

CONVERTERDecimation:2 to 65536

MODEL RTR 2750

USB

GigabitEthernet

PS/2KeyboardPS/2Mouse

VideoOutput

GPS Antenna(Optional)

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

RAID DATA STORAGE



Model RTR 2750

The Talon RTR 2750 is a turnkey recording systemthat provides phase-coherent recording of 16 indepen-dent input channels. Each input channel includes a250 MHz 16-bit A/D and an FPGA-based digital down-converter with programmable decimations from 2 to65536, thereby providing the ability to capture RFsignals with bandwidths up to 100 MHz.

With options for AC- or DC-coupled input channels,RF signals up to 700 MHz in frequency can be sampledand streamed to disk in real-time at sustained aggregaterecording rates up to 8 GB/sec in a 4U rackmountsolution.

Designed to operate under conditions of vibrationand extended operating temperatures, the RTR 2750 isideal for military, airborne and field applications thatrequire a rugged system. The hot-swappable solid statestorage drives provide the highest level of performance

under harsh conditions and allow for quick removal of mission-critical data.

A/D sampling rates, DDC decimations and trigger settingsare among the selectable system parameters, providing a systemthat is simple to configure and operate. An optional GPStime and position stamping facility allows the user to time-stamp each acquisition as well as track the location of asystem in motion.

For users who wish to create a custom user interfaceor to integrate the Talon recording system into a largerapplication, a C-callable API is also provided as part ofSystemFlow. Source code and examples are supplied toallow for a quick and simple integration effort.

Data can be off-loaded through gigabit Ethernet portsor USB 3.0 ports. Additionally, data can be copied tooptical disk, using the 8X double layer DVD±R/RW drive.






7070707070


Figure 75

Model RTS 2707 RModel RTS 2707 RModel RTS 2707 RModel RTS 2707 RModel RTS 2707 Rackmount Lackmount Lackmount Lackmount Lackmount Lab ab ab ab ab ● ● ● ● ● Model RTR 2727 RModel RTR 2727 RModel RTR 2727 RModel RTR 2727 RModel RTR 2727 Rugged Pugged Pugged Pugged Pugged PororororortabletabletabletabletableModel RTR 2747 RModel RTR 2747 RModel RTR 2747 RModel RTR 2747 RModel RTR 2747 Rugged Rugged Rugged Rugged Rugged Rackmount ackmount ackmount ackmount ackmount ●●●●● Model RTX 2767 Extreme R Model RTX 2767 Extreme R Model RTX 2767 Extreme R Model RTX 2767 Extreme R Model RTX 2767 Extreme Rackmountackmountackmountackmountackmount

500 MS/sec RF/IF R500 MS/sec RF/IF R500 MS/sec RF/IF R500 MS/sec RF/IF R500 MS/sec RF/IF Rackmount Lackmount Lackmount Lackmount Lackmount Lab Rab Rab Rab Rab Recorderecorderecorderecorderecorder

The Talon RTS 2707 is a turnkey, multiband record-ing and playback system for recording and reproducinghigh-bandwidth signals. The RTS 2707 uses 12-bit,500 MHz A/D converters and provides agregate recordingrates up to 1.6 GB/sec.

The RTS 2707 uses Pentek’s high-powered Virtex-6-based Cobalt modules, that provide flexibility in channelcount, with optional digital downconversion capabilities.Optional 16-bit, 800 MHz D/A converters with digitalupconversion allow real-time reproduction of recordedsignals.

A/D sampling rates, DDC decimations and band-widths, D/A sampling rates and DUC interpolations areamong the GUI-selectable system parameters, providinga fully-programmable system capable of recording andreproducing a wide range of signals. Optional GPS timeand position stamping allows the user to record thiscritical signal information.

The RTS 2707 includes the SystemFlow RecordingSoftware. SystemFlow features a Windows-based GUIthat provides a simple means to configure and control therecorder.

The RTS 2707 is configured in a 4U 19" rack-mountable chassis, with hot-swappable data drives, frontpanel USB ports and I/O connectors on the rear panel.Systems are scalable to accommodate multiple chassis toincrease channel counts and aggregate data rates.

Multiple RAID levels, including 0, 1, 5, 6, 10 and50, provide a choice for the required level of redundancy.The hot-swappable HDDs provide storage capacities ofup to 100 TB in a single 6U chassis.

Versions of the RTS 2707 are available as RuggedPortable (Model RTR 2727), Rugged Rackmount (ModelRTR 2747), and Extreme Rackmount (Model RTX 2767).

Model RTS 2707

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

RAID DATA STORE



MODEL RTS 2707

USB 2.0

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput


ChannelsIn

ChannelsOut

DIGITAL DOWN-CONVERTERDEC: 2 to 64K

800 MHz16-bit D/A

Up to 4Channels

500 MHz12-bit A/D

or400 MHz14-bit A/D

Up to 4Channels

DIGITAL UP-CONVERTERINT: 2 to 64K

es

6-

s

-

a-








7171717171


Figure 76

Model RTR 2748 R Model RTR 2748 R Model RTR 2748 R Model RTR 2748 R Model RTR 2748 Rugged Rugged Rugged Rugged Rugged Rackmount ackmount ackmount ackmount ackmount ●●●●● Model RTR 2728 RModel RTR 2728 RModel RTR 2728 RModel RTR 2728 RModel RTR 2728 Rugged Pugged Pugged Pugged Pugged PororororortabletabletabletabletableModel RTX 2768 Extreme RModel RTX 2768 Extreme RModel RTX 2768 Extreme RModel RTX 2768 Extreme RModel RTX 2768 Extreme Rackmountackmountackmountackmountackmount

1 GS/sec RF/IF R1 GS/sec RF/IF R1 GS/sec RF/IF R1 GS/sec RF/IF R1 GS/sec RF/IF Rugged Rugged Rugged Rugged Rugged Rackmount Rackmount Rackmount Rackmount Rackmount Recorderecorderecorderecorderecorder

MODEL RTR 2748

USB

GigabitEthernet

Keyboard

Mouse

VideoOutput


ChannelIn

ChannelOut

1 GHz16-bitD/A

1 GHz12-bitA/D

ChannelIn

ChannelOut

1 GHz16-bitD/A

1 GHz12-bitA/D

(Optional)

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

RAID DATA STORAGE



Model RTR 2748

The Talon RTR 2748 is a turnkey recording and playbacksystem that allows users to record and reproduce signalswith bandwidths up to 500 MHz. The RTR 2748 can beconfigured as a one- or two-channel system to providereal-time aggregate recording and playback rates up to4.0 GB/sec to an array of solid-state drives.

The RTR 2748 uses Pentek’s high-powered Virtex-6-based Cobalt boards that provide the data streamingengine for the high-speed A/D converters. A built-insynchronization module is provided to allow for multi-channel phase-coherent operation. GPS time and positionstamping is optionally available.

The RTR 2748 includes the SystemFlow RecordingSoftware. SystemFlow features a Windows-based GUIthat provides a simple means to configure and controlthe system. Custom configurations can be stored as profilesand later loaded when needed, allowing the user to selectpreconfigured settings with a single click.

Built on a Windows 7 Professional workstation,the RTR 2748 allows the user to install post-processingand analysis tools to operate on the recorded data. TheRTR 2748 records data to the native NTFS file systemthat provides immediate access to the recorded data.

Data can be off-loaded via gigabit Ethernet ports, orUSB 2.0 and USB 3.0 ports. Additionally, data can becopied to optical disk, using the 8X double layerDVD±R/RW drive.

Because SSDs operate reliably under conditions of shockand vibration, the RTR 2748 performs well in ground, ship-borne and airborne environments. The drives can be easilyremoved or exchanged during a mission to retrieve the data.

Versions of the RTR 2748 are also available as aRugged Portable (Model RTR 2728), and ExtremeRackmount (Model RTX 2768).







7272727272


Figure 77

Model RTX 2769 Extreme R Model RTX 2769 Extreme R Model RTX 2769 Extreme R Model RTX 2769 Extreme R Model RTX 2769 Extreme Rackmount ackmount ackmount ackmount ackmount ●●●●● Model RTR 2729A RModel RTR 2729A RModel RTR 2729A RModel RTR 2729A RModel RTR 2729A Rugged Pugged Pugged Pugged Pugged PororororortabletabletabletabletableModel RTR 2749 RModel RTR 2749 RModel RTR 2749 RModel RTR 2749 RModel RTR 2749 Rugged Rugged Rugged Rugged Rugged Rackmountackmountackmountackmountackmount

Channel 1In 3.6 GHz

(1 Channel)or

1.8 GHz(2 Channel)12-Bit A/D

MODEL RTX 2769

Keyboard

Mouse

VideoOutput


Channel 2In

USB

GigabitEthernet

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

RAID DATA STORAGE



Model RTX 2769

3.6 GS/sec Ultra W3.6 GS/sec Ultra W3.6 GS/sec Ultra W3.6 GS/sec Ultra W3.6 GS/sec Ultra Wideband RF/IF Extreme Rideband RF/IF Extreme Rideband RF/IF Extreme Rideband RF/IF Extreme Rideband RF/IF Extreme Rackmount Rackmount Rackmount Rackmount Rackmount Recorderecorderecorderecorderecorder

The Talon RTX 2769 is a turnkey system that is built tooperate under harsh conditions. Designed to withstandhigh vibration and operating temperatures, the RTX2769 is intended for military, airborne and UAV applicationsrequiring a rugged system.

Aimed at recording high-bandwidth signals, the RTX 2769uses 12-bit, 3.6 GHz A/D converters. It can be configuredas a one- or two-channel system and can record sampled data,packed as 8-bit- or 16-bit-wide consecutive samples(12-bit digitized samples residing in the 12 MSBs of the16-bit word). A high-speed RAID array provides anaggregate streaming recording rate to disk of 4.8 GB/sec.

The RTX 2769 uses Pentek’s high-powered Virtex-7-based Onyx boards that provide the data streaming enginefor the high-speed A/D converters. Channel and packingmodes as well as gate and trigger settings are among theselectable system parameters, providing completecontrol over this ultra wideband recording system.

Built on a Windows 7 Professional workstation,the RTX 2769 allows the user to install post-processingand analysis tools to operate on the recorded data. TheRTX 2769 records data to the native NTFS file systemthat provides immediate access to the recorded data.

The Talon RTX 2769 uses a shock- and vibration-isolated inner chassis and solid-state drives to assure reliabil-ity under harsh conditions. Developed by Pentek to enhancethe operation of Extreme recorders, up to four front-panelremovable QuickPacTM drive canisters are provided, eachcontaining up to eight SSDs. Fastened with four thumbscrews,each drive canister can hold up to 7.6 TB of data storageand allows for quick and easy removal of mission-critical datawith a minimum of down time.

Versions of the RTX 2769 are available as a RuggedPortable (Model RTR 2729A), and Rugged Rackmount(Model RTR 2749).







7373737373


Model RTS 2715 R Model RTS 2715 R Model RTS 2715 R Model RTS 2715 R Model RTS 2715 Rackmount Lackmount Lackmount Lackmount Lackmount Lab ab ab ab ab ●●●●● Model RTR 2755 R Model RTR 2755 R Model RTR 2755 R Model RTR 2755 R Model RTR 2755 Rugged Rugged Rugged Rugged Rugged RackmountackmountackmountackmountackmountModel RTX 2775 Extreme RModel RTX 2775 Extreme RModel RTX 2775 Extreme RModel RTX 2775 Extreme RModel RTX 2775 Extreme Rackmountackmountackmountackmountackmount

Figure 78

10-10-10-10-10-Gigabit Ethernet RGigabit Ethernet RGigabit Ethernet RGigabit Ethernet RGigabit Ethernet Rackmount Rackmount Rackmount Rackmount Rackmount Recorderecorderecorderecorderecorder

ChannelsIn / Out

Ethernet

MODEL RTS 2715

USB

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput


INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

RAID DATA STORAGE



The Talon RTS 2715 is a turnkey rackmount lab record-ing system for storing one or two 10-gigabit Ethernet (10GbE)streams. It is ideal for capturing any type of streaming sourcesincluding live transfers from sensors or data from other computersand supports both TCP and UDP protocols. Using highly-optimized disk storage technology, the system achievesaggregate recording rates up to 1.6 GB/sec.

Two rear panel SFP+LC connectors for 850 nm multi-mode or single-mode fibre cables, or CX4 connectors for coppertwinax cables accommodate all popular 10 GbE interfaces.Optional GPS time and position stamping accuratelyidentifies each record in the file header.

The RTS 2715 includes the SystemFlow RecordingSoftware. SystemFlow features a Windows-based GUI(Graphical User Interface) that provides a simple andintuitive means to configure and control the system.Custom configurations can be stored as profiles and later

loaded as needed, allowing the user to select preconfiguredsettings with a single click.

Built on a server-class Windows 7 Professionalworkstation, the RTS 2715 allows the user to installpost-processing and analysis tools to operate on therecorded data. The RTS 2715 records data to the nativeNTFS file system, providing immediate access to thedata.

The RTS 2715 is configured in a 4U or 5U 19" rack-mountable chassis, with hot-swap data drives, front panelUSB ports and I/O connectors on the rear panel. Systemsare scalable to accommodate multiple chassis to increasechannel counts and aggregate data rates.

Versions of the RTS 2715 are also available as RuggedRackmount (Model RTR 2755), and Extreme Rackmount(Model RTX 2775).

Model RTS 2715







7474747474


Figure 79

Serial FPDP RSerial FPDP RSerial FPDP RSerial FPDP RSerial FPDP Rugged Pugged Pugged Pugged Pugged Pororororortable Rtable Rtable Rtable Rtable Recorderecorderecorderecorderecorder

Model RTR 2736A R Model RTR 2736A R Model RTR 2736A R Model RTR 2736A R Model RTR 2736A Rugged Pugged Pugged Pugged Pugged Pororororortable table table table table ●●●●● Model RTS 2716 R Model RTS 2716 R Model RTS 2716 R Model RTS 2716 R Model RTS 2716 Rackmount Lackmount Lackmount Lackmount Lackmount LabababababModel RTR 2756 RModel RTR 2756 RModel RTR 2756 RModel RTR 2756 RModel RTR 2756 Rugged Rugged Rugged Rugged Rugged Rackmount ackmount ackmount ackmount ackmount ● ● ● ● ● Model RTX 2776 Extreme RModel RTX 2776 Extreme RModel RTX 2776 Extreme RModel RTX 2776 Extreme RModel RTX 2776 Extreme Rackmountackmountackmountackmountackmount

RAID DATA STORAGE



MODEL RTR 2736

USB

GigabitEthernet

PS/2Keyboard

PS/2Mouse

VideoOutput


ChannelsIn / Out Serial

FPDP

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

The system includes the SystemFlow RecordingSoftware. SystemFlow features a Windows-based GUIthat provides a simple and intuitive means to configureand control the system. Custom configurations can bestored as profiles and later loaded as needed, allowing theuser to select preconfigured settings with a single click.

The RTR 2736A is configured in portable, lightweightchassis with hot-swap SSDs, front panel USB ports andI/O connections on the side panel. It is built in extremelyrugged, 100% aluminum alloy unit, reinforced with shockabsorbing rubber corners and impact-resistant protectiveglass. Using vibration- and shock-resistant SSDs, thesystem is designed to operate reliably as a portable fieldsystem in harsh environments.

Versions of the RTR 2736A are also available as aRackmount Lab unit (Model RTS 2716), RuggedRackmount (Model RTR 2756), and Extreme Rackmount(Model RTX 2776).

Model RTR 2736A

The Talon RTR 2736A is a complete turnkey record-ing system designed to operate under conditions of shockand vibration. It records and plays back multiple serialFPDP data streams in a rugged, lightweight portablepackage. It is ideal for capturing any type of streamingsources including live transfers from sensors or data fromother computers and is fully compatible with the VITA17.1 specification. Using highly-optimized disk storagetechnology, this system achieves aggregate recording ratesup to 3.2 GB/sec.

The system can be populated with up to eight SFPconnectors supporting Serial FPDP over copper, single-mode,or multi-mode fiber, to accommodate all popular serial FPDPinterfaces. It is capable of receiving and transmitting dataover these links and supports real-time data storage to disk.The system is capable of handling 1.0625, 2.125, 2.5,3.125 and 4.25 GBaud link rates supporting data transferrates of up to 420 MB/sec per serial FPDP link.








7575757575


Figure 80

LLLLLVDS Digital I/O Extreme RVDS Digital I/O Extreme RVDS Digital I/O Extreme RVDS Digital I/O Extreme RVDS Digital I/O Extreme Rackmount Rackmount Rackmount Rackmount Rackmount Recorderecorderecorderecorderecorder

Model RTX 2778 Extreme R Model RTX 2778 Extreme R Model RTX 2778 Extreme R Model RTX 2778 Extreme R Model RTX 2778 Extreme Rackmount ackmount ackmount ackmount ackmount ● ● ● ● ● Model RTS 2718 RModel RTS 2718 RModel RTS 2718 RModel RTS 2718 RModel RTS 2718 Rackmount Lackmount Lackmount Lackmount Lackmount LabababababModel RTR 2738 RModel RTR 2738 RModel RTR 2738 RModel RTR 2738 RModel RTR 2738 Rugged Pugged Pugged Pugged Pugged Pororororortable table table table table ● ● ● ● ● Model RTR 2758 RModel RTR 2758 RModel RTR 2758 RModel RTR 2758 RModel RTR 2758 Rugged Rugged Rugged Rugged Rugged Rackmountackmountackmountackmountackmount

Model RTX 2778

32-bitData In

32-bitLVDS I/ORecord

Interface

MODEL RTX 2778

Keyboard

Mouse

VideoOutput


Clock

Data Valid

Data Suspend

32-bitData Out Optional

32-bitLVDS I/OPlaybackInterface

Clock

Data Valid

Data Suspend

USB

GigabitEthernet

INTELPROCESSOR

SYSTEM DRIVEDDR

SDRAM

HOST PROCESSOR

RUNNING SYSTEMFLOW

RAID DATA STORAGE



The Talon RTX 2778 is a turnkey record and playbacksystem that is built to operate under harsh conditions.Designed to withstand high vibration and operating tempera-tures, the RTX 2778 is intended for military, airborneand UAV applications requiring a rugged system.

The RTX 2778 records and plays back digital datausing the Pentek Model 78610 LVDS digital I/O board.Using highly optimized disk storage technology, the systemachieves aggregate recording rates of up to 1.0 GB/sec.

The RTX 2778 utilizes a 32-bit LVDS interfacethat can be clocked at speeds up to 250 MHz. It includesData Valid and Suspend signals and provides the abilityto turn these signals on and off as well as control their polarity.

The RTX 2778 includes the SystemFlow Record-ing Software. SystemFlow features a Windows-basedGUI (Graphical User Interface) that provides a simplemeans to configure and control the system.

Built on a Windows 7 Professional workstation,the RTX 2778 allows the user to install post-processingand analysis tools to operate on the recorded data. TheRTX 2778 records data to the native NTFS file system,providing immediate access to the recorded data.

The Talon RTX 2778 uses a shock- and vibration-isolated inner chassis and solid-state drives to assure reliabil-ity under harsh conditions. Developed by Pentek to enhancethe operation of Extreme recorders, up to four front-panelremovable QuickPacTM drive canisters are provided, eachcontaining up to eight SSDs. Fastened with four thumbscrews,each drive canister can hold up to 7.6 TB of data storageand allows for quick and easy removal of mission-critical datawith a minimum of down time.

Versions of the RTX 2778 are also available as aRackmount Lab unit (Model RTS 2718), RuggedPortable (Model RTR 2738), and Rugged Rackmount(Model RTR 2758).








7676767676


LLLLL-Band OpenVPX Signal P-Band OpenVPX Signal P-Band OpenVPX Signal P-Band OpenVPX Signal P-Band OpenVPX Signal Processing Systemrocessing Systemrocessing Systemrocessing Systemrocessing System


The Cobalt Model 53690 VPX L-Band RF Tunertargets reception and processing of digitally-modulatedRF signals such as satellite television and terrestrialwireless communications. The 53690 requires only anantenna and a host computer to form a complete L-bandSDR development platform.

This system receives L-Band signals between 925 MHzand 2175 MHz directly from an antenna. Signals abovethis range such as C Band, Ku Band and K band can bedownconverted to L-Band through an LNB (Low NoiseBlock) downconverter installed in the receiving antenna.

The Maxim Max2112 L-Band Tuner IC features alow-noise amplifier with programmable gain from 0 to65 dB and a synthesized local oscillator programmablefrom 925 to 2175 MHz. The complex analog mixertranslates the input signals down to DC. Basebandamplifiers provide programmable gain from 0 to 15 dBin steps of 1 dB. The bandwidth of the baseband lowpassfilters can be programmed from 4 to 40 MHz . TheMaxim IC accommodates full-scale input levels of -50 dBmto +10 dbm and delivers I and Q complex baseband outputs.

Figure 81

The complex I and Q outputs are digitized by two200 MHz 16-bit A/D converters operating synchronously.

The Virtex-6 FPGA is a powerful resource forrecovering and processing a wide range of signalswhile supporting decryption, decoding, demodulation,detection, and analysis. It is ideal for intercepting ormonitoring traffic in SIGINT and COMINTapplications. Other applications that benefit includemobile phones, GPS, satellite terminals, military telem-etry, digital video and audio in TV broadcasting satellites,and voice, video and data communications.

This L-Band signal processing system is ideal as afront end for government and military systems. Its smallsize adderesses space-limited applications. Besides theModel 53690, ruggedized options are available fromPentek with the Models 71690 XMC module and theModel 57690 6U VPX board to address UAV applicationsand other severe environments.

Development support for this system is provided bythe Pentek ReadyFlow board support package for Windows,Linux and VxWorks. Also available is the Pentek GateFlowFPGA Design Kit to support custom algorithm development.

VPXBackplane

Analog Digital

IL-Band

x8 PCIe

x8 PCIe

LNA

Analog Local

Oscillator

Synthesizer

Q

Baseband AmpsAnalog Mixer

Analog Mixer

I

AnalogLowpass

FilterA/D

A/D

FPGA

VPX P1Slot 1

VPX P1Slot 2

OpenVPXCPU

Board

VIRTEX-6

RF Input Q

MaximMAX2112

Pentek 53690 3U VPX Board

LowpassFilter

Analog

FP A

FP B

DP02

DP01

EP01

EP02

FPC

DP01


7777777777


Figure 82


8-8-8-8-8-Channel OpenVPX Beamforming SystemChannel OpenVPX Beamforming SystemChannel OpenVPX Beamforming SystemChannel OpenVPX Beamforming SystemChannel OpenVPX Beamforming System

Two Model 53661 boards are installed in slots 1 and2 of an OpenVPX backplane, along with a CPU boardin slot 3. Eight dipole antennas designed for receiving2.5 GHz signals feed RF Tuners containing low noiseamplifiers, local oscillators and mixers. The RF Tunerstranslate the 2.5 GHz antenna frequency signal downto an IF frequency of 50 MHz.

The 200 MHz 16-bit A/Ds digitize the IF signalsand perform further frequency downconversion to baseband,with a DDC decimation of 128. This provides I+Q complexoutput samples with a bandwidth of about 1.25 MHz. Phaseand gain coefficients for each channel are applied tosteer the array for directionality.

The CPU board in VPX slot 3 sends commandsand coefficients across the backplane over two x4 PCIelinks, or OpenVPX “fat pipes”.

The first four signal channels are processed in theupper left 53661 board in VPX slot 1, where the 4-channelbeamformed sum is propagated through the 4X AuroraSum Out link across the backplane to the 4X Aurora SumIn port on the second 53661 in slot 2. The 4-channel localsummation from the second 53661 is added to the propa-gated sum from the first board to form the complete 8-channelsum. This final sum is sent across the x4 PCIe link to theCPU card in slot 3.

Assignment of the three OpenVPX 4X links on theModel 53661 boards is simplified through the use of acrossbar switch which allows the 53661 to operate witha wide variety of different backplanes.

Because OpenVPX does not restrict the use of serialprotocols across the backplane links, mixed protocolarchitectures like the one shown are fully supported. ➤

VPX P1

Slot 1

EP02

EP01

DP01

FP C

VPX P1

Slot 2

VPX P1

Slot 3 CPU

EP02

EP01

DP01

FPC

x4 PCIe

x4 PCIe

200 MHz

16-bit A/D

DDC 4G + Phase

PCIe

x4

I/F

200 MHz16-bit A/D

200 MHz

16-bit A/D

200 MHz

16-bit A/D

AURORA

BEAMFORMSUMMATION

DDC 3

G + Phase

DDC 2G + Phase

DDC 1

G + Phase

4X Sum In

4X Sum Out

Model 53661

x4 PCIe

200 MHz

16-bit A/D

DDC 4

G + Phase

PCIe

x4

I/F

200 MHz16-bit A/D

200 MHz

16-bit A/D

200 MHz

16-bit A/D

AURORA

BEAMFORMSUMMATION

DDC 3

G + Phase

DDC 2

G + Phase

DDC 1

G + Phase

4X Sum In

4X Sum Out

x4 PCIe

Model 53661

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

RF Tuner

FP B

FP A

DP01

DP02

OpenVPX

CPUBoard

VPXBACKPLANE

4X Aurora


7878787878



Figure 83

8-8-8-8-8-Channel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo systemChannel OpenVPX Beamforming Demo system

➤➤➤➤➤ Beamforming Demo System

The beamforming demo system is equipped with aControl Panel that runs under Windows on the CPUboard. It includes an automatic signal scanner to detectthe strongest signal frequency arriving from a testtransmitter. This frequency is centered around the50 MHz IF frequency of the RF downconverter. Oncethe frequency is identified, the eight DDCs are setaccordingly to bring that signal down to 0 Hz forsummation.

The control panel software also allows specifichardware settings for all of the parameters for the eightchannels including gain, phase, and sync delay.

An additional display shows the beam-formed pattern ofthe array. This display is formed by adjusting the phaseshift of each of the eight channels to provide maximum

sensitivity across arrival angles from -90O to +90O

perpendicular to the plane of the array.

The classic 7-lobe pattern for an ideal 8-elementarray for a signal arriving at 0O angle (directly in front ofthe array) is shown above. Below the lobe pattern is apolar plot showing a single vector pointing to thecomputed angle of arrival. This is derived from identify-ing the lobe with the maximum response.

An actual plot of a real-life transmitter is also shownfor a source directly in front of the display. In this casethe perfect lobe pattern is affected by physical objects,reflections, cable length variations and minor differencesin the antennas. Nevertheless, the directional informationis computed quite well. As the signal source is moved leftand right in front of the array, the peak lobe moves withit, changing the computed angle of arrival.

This demo system is available online at Pentek. Ifyou are interested in viewing a live demonstration, pleaselet us know of your interest by clicking on this link:

Beamforming Demo.

Beamforming Demo Control Panel Theoretical 7-lobe Beamforming Patern Real-Life Beamforming Patern

http://www.pentek.com/go/bfdemo

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