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Fabrication of ultrahigh density metal–cell–metal crossbar memory devices with only two

cycles of lithography and dry-etch procedures

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2013 Nanotechnology 24 245303

(http://iopscience.iop.org/0957-4484/24/24/245303)

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Nanotechnology 24 (2013) 245303 (9pp) doi:10.1088/0957-4484/24/24/245303

Fabrication of ultrahigh densitymetal–cell–metal crossbar memorydevices with only two cycles oflithography and dry-etch procedures

B Y Zong1,2, J Y Goh2,3, Z B Guo2,4, P Luo2, C C Wang2, J J Qiu2, P Ho2,Y J Chen2, M S Zhang2 and G C Han2

1 Temasek Laboratories, National University of Singapore, #09-02, 5A Engineering Drive 1, 117411,Singapore2 Data Storage Institute, Agency for Science, Technology and Research (A*STAR), DSI Building,5 Engineering Drive 1, 117608, Singapore3 National Junior College, 37 Hillcrest Road, 288913, Singapore4 Core Labs, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900,Saudi Arabia

E-mail: tslzb@nus.edu.sg and baoyuzong@hotmail.com

Received 17 January 2013, in final form 19 April 2013Published 20 May 2013Online at stacks.iop.org/Nano/24/245303

AbstractA novel approach to the fabrication of metal–cell–metal trilayer memory devices wasdemonstrated by using only two cycles of lithography and dry-etch procedures. The fabricatedultrahigh density crossbar devices can be scaled down to ≤70 nm in half-pitch withoutalignment issues. Depending on the different dry-etch mechanisms in transferring high andlow density nanopatterns, suitable dry-etch angles and methods are studied for the transfer ofhigh density nanopatterns. Some novel process methods have also been developed to eliminatethe sidewall and other conversion obstacles for obtaining high density of uniform metallicnanopatterns. With these methods, ultrahigh density trilayer crossbar devices (∼2× 1010 bitcm−2-kilobit electronic memory), which are composed of built-in practical magnetoresistivenanocells, have been achieved. This scalable process that we have developed provides therelevant industries with a cheap means to commercially fabricate three-dimensional highdensity metal–cell–metal nanodevices.

(Some figures may appear in colour only in the online journal)

1. Introduction

Smaller miniature devices with higher capacities or morefunctions are the trend in the extremely competitive electronicproducts market, e.g. in hard disk drives, thumb drives, mobilephones, and the integrated circuit (IC) chip industries [1, 2].To improve the capacity or function of the miniature devices,much higher density and finer nanopatterns are required. Forexample, to achieve a high capacity of more than 1 Tb in−2

memory, the pitch of the storage bits should be <30 nm [3].The fabrication process of high density fine nanopatterns

is critical in the production of miniature nanodevices [4].Conventional resist lithography and dry-etch are usually usedin the fabrication process. This process provides a cost-effective and feature-scalable preparation of nanostructurescompared to other methods (e.g. self-alignment), andmatches the different shape and size requirements of thenanodevices [5, 6]. Thus, this process is widely used inthe production of commercial nanodevices nowadays [7].To fabricate trilayer metal-electrode/magnetoresistive (MR)cell/metal-electrode memory devices, each layer (includingthe metallic nanocell layer) typically requires one cycle

10957-4484/13/245303+09$33.00 c© 2013 IOP Publishing Ltd Printed in the UK & the USA

Nanotechnology 24 (2013) 245303 B Y Zong et al

of lithography and dry-etch procedures [8]. With thiscommon method, although devices with loosely distributed(usually half-pitch > 200 nm) sub-50 nm feature sizes canbe readily achieved [2, 9], some critical problems arise fromthe fabrication of three-dimensional (3D) devices when thecharacteristic size (e.g. the dimension of electrode arrays)is reduced to less than ≤100 nm for the half-pitch. Forinstance, there are challenges to convert high density resistnanopatterns into smooth device nanostructures, and to defineor locate accurately the fine practical cell nanopillars on thesearray-electrodes with a half-pitch of less than ≤100 nm,etc [10, 11]. Currently, an approach to the fabrication oftrilayers for practical metal–cell–metal memory devices, witha half-pitch less than 100 nm, has not been reported, despitethe increasing demand for the miniature 3D memory devicesand their related manufacturing processes (e.g. the transfer ofhigh density nanopatterns) from the relevant industries [12,13]. Even though resist lift-off and other alternative methods,such as one-step deposition via selective etching of multilayersuperlattice films [14, 15], or the embedding of nanowiresin thin polymer slabs [16], have been employed to preparethin bilayer metal crossbars (usually ≤10 nm in thicknessfor each layer) with an ultrahigh density of ≤100 nmin half-pitch [17], the subsequent fabrication of <100 nmpractical fine metallic cells on each junction of crossbarcircuits to form a commercial memory device remains acritical challenge [17, 18]. Thus, the search for a suitablemethod to fabricate high density multilayer 3D nanodevices,particularly a cost-effective simple way for industry, is ofinterest and in high demand.

Herein, by using a novel method via two cycles oflithography and dry-etch procedures as well as suitable etchmethods during the nanopattern transfer, we demonstrated thesuccessful fabrication of trilayer crossbar memory deviceswith a half-pitch of less than 70 nm through the conventionalcost-effective processes. With the development of simpleprocess skills to shorten the fabrication nanoprocess as wellas to eliminate the transfer defects, practical ultrahigh density3D metal-MR cell-metal crossbar nanodevices were achieved.

2. Experimental methods

In this investigation, a high resolution (≤2 nm) electron-beamnanolithography system (ELS-7000) was used to exposethe high density resist nanopatterns. The resist and devicenanopatterns were configured on SiO2 isolator wafers. Duringthe nanolithography process, the positive e-beam resistZEP(520A) and negative hydrogen silsesquioxane (HSQ)were used. The metallic device films were sputter-depositedon the SiO2 wafer using a thin-film sputter system (MPS-6301-SP). During the transfer of resist to device nanopatternsvia dry-etching, a Microetch ion-beam system (IBE, RF-350)was used. The applied voltage for the IBE system was250–400 V at a frequency of 50 Hz. The developers usedwere ZED-N50 (with ZMD as the rinsing solution) andtetramethylammonium hydroxide for ZEP and HSQ resists,respectively. Resist lift-off was carried out by immersing thesample in Remover PG solution in an ultrasonic bath for

20–30 min. The thickness and images of all nanopatternswere measured using an atomic force microscope (AFM,Dimension 3100) or a field emission scanning electronmicroscope (FESEM, JSM 7401F). The exposure energies ofthe resists and measurement methods for the nanopatterns andMR nanocells were similar to those reported previously [19,20].

3. Results and discussion

The fabrication process for the trilayer metal-MR cell-metal crossbar memory devices was directly achieved fromtraditional scalable lithography and dry-etch processes viasimple novel two-cycle procedures. The successful transfer ofhigh density resist nanopatterns to uniform device nanoarrayswas approached via a careful dry-etch by selecting suitableetch-angles.

Figure 1 illustrates a comparison between the commonconventional method and our developed simple method forthe preparation of a trilayer crossbar device. The commonpreparation method, a process with three cycles of lithographyand dry-etch procedures, usually requires an additional cyclefor the fabrication of nanocells compared to our novel simplemethod. For the fabrication of memory devices with higharray density (e.g. ≤100 nm in half-pitch) by using thecommon method, the existing challenges include (i) locatingrecording cell elements on the fine <100 nm electrodenanoarrays, (ii) converting high density resist nanopatterns tosmooth device nanostructures, and (iii) subsequently locatingthe fine high density top-electrode nanoarrays on the fine<100 nm nanocells.

3.1. Different conversion mechanisms for high and lowdensity device nanofeatures

For the transfer of resist nanopatterns to high density orfine multilayer device nanostructures, ion-beam etch (IBE)was preferred since it used an inert Ar-gas source andproduced a smaller difference in etch-rates for the differentmetallic layers. A better side profile was obtained forthe converted device nanopatterns in comparison to otherdry-etch methods [19, 21]. Based on the nanopattern transfermechanism via IBE etching, the transfer of ultrahigh densitynanopatterns was found to be quite different from that ofloosely distributed nanopatterns during etching. Figures 2(a)and (b) show the comparison for dry-etching low and highdensity resist nanopatterns, respectively. In the dry-etch, afluid etch medium with a stable energy and continuous contactwith the etching position was required for a successful etch.When converting device nanofeatures from high density resistnanopatterns, the closely packed resist patterns hindered theeffective penetration of the etch medium (namely ion-beam)into the trench bottoms. The issue arose due to the reducedion-beam energy after the absorption or shading by the sideor top surfaces of the high density resist nanopatterns. At thesame time, the etched or reflected ion-beam residues couldnot disperse readily or quickly from the narrow patternedtrenches. This situation prohibited the incident etching

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Figure 1. Schematic illustration of (a) the conventional method and (b) our new approach for the fabrication of trilayer nanodevices viathree and two cycles of lithography and dry-etch processes, respectively. The pictures in brackets show the corresponding top views.

Figure 2. Comparison of dry-etching (a) low and (b) high density resist nanopatterns at the minimum etch angle of the ion-beam to thesubstrate. ‘A’ represents the remaining resist residue-patterns while ‘B’ represents the sidewalls attached on the resist residue-patterns afterthe dry-etch. (c) The etch-rates for commonly used bare films with different etch-angles. The etching voltage and current used were 250 Vand 0.42 mA cm−2, respectively.

medium from reaching the surfaces of the etching metal film(shown in figure 2(b)), which was located at the trench bottomof the resist nanopatterns, hence reducing the etch-rates of thedevice metal films. Moreover, the confined etching-residuescould damage or re-deposit on the sides of the fine resistnanopatterns. The re-deposition enhanced sidewall defects of

the converted device nanopatterns. After etching, the sidewall(B) depicted in figure 2(b) formed a significant portionof the fine resist residue-patterns, which almost entirelywrapped the fine device nanopatterns from two sides. Thiswas quite different from the big and loosely distributed resistpatterns (shown in figure 2(a)). The fine resist residue-patterns

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wrapped by the sidewalls were more difficult to remove duringthe lift-off process due to the difficulty for lift-off solution topenetrate into the resist residues. Thus, during the conversionof high density nanopatterns, there were critical challengesin ensuring that the etch medium moved readily in andout of the resist pattern trenches without severely damagingthe fine resist nanopattern-shapes during dry-etching andminimizing sidewall defects after the etch, etc. Most of suchchallenges were irrelevant during the etch of big sub-micronor loosely distributed fine nanopatterns, as the etch mediumcould readily approach or reflect away from the etchingposition without any obstacles for the loosely distributed finenanopatterns. As such, there was a much lower portion ofsidewalls for the big patterns. Thus, converted fine devicenanofeatures (such as those down to sub-20 nm [2, 9]) arecommonly reported, whereas reported instances of convertedhigh density sub-50 nm device features have been few thus far.Our solutions to these challenges were based on these analysesof the etching natures and mechanisms.

3.2. Selection of suitable IBE dry-etch angle and energy

The sidewall defects after the dry-etch and resist lift-offwere a major challenge in the common fabrication method(depicted in figure 1(a)), and the sidewall defects couldexist in both high and low densities of transferred devicenanopatterns, despite there being a better situation for thelow density nanopatterns (as stated above). Figure 3(a) showsthe sidewall defects, which are still significant althoughthey were partially wiped out with residue-free cloths. Toreduce sidewall defects and achieve device nanopatterns witha good profile during IBE etching, the dry-etch angle ofthe ion-beam to the sample surface was critical. A suitableetch angle could prevent the ion-beam (etch medium) andthe reflected residue ion-beam from being fully shaded andconfined by the resist nanopatterns. Figure 2(c) also illustratesthe etch-rates for commonly used materials with respect to thedifferent etch-angles. Table 1 shows the relationship betweenthe minimum (min.) etch angle to the substrate surface andthe gap or height of the resist nanopatterns. To obtain highcontrast device nanopatterns with lower sidewall height, anetch angle smaller than 90◦ was favourable. Experimentalresults showed that there were almost no sidewall defectsby using an etch angle slightly larger than 45◦ for theloosely distributed resist patterns, if there were no shadingand confining for the ion-beam. However, with increase innanopattern density (namely a decrease of the nanopatterngap), the range of dry-etch angles, with respect to the differentheights of resist nanopatterns, became much narrower whenconsidering the shading and reflection of the ion-beam(depicted in figure 2). For example, table 1 illustrates that forresist nanopatterns with a 5 or 50 nm gap and a correspondingheight from 100 to 25 nm, the minimum etch angle wasbetween 87◦–79◦ and 63◦–27◦, respectively. It is noted that90◦ was the maximum etch angle, where the etching ion-beamwas normal to the sample surface. Thus, an optimized dry-etchangle should be used in the nanopattern transfer after furtherconsideration of the device profile, sidewall issue, shading

Table 1. Relationship between the minimum IBE etch angle andthe height or gap of the resist nanopattern.

Min. etch angle,α (deg)

Height of resistnanopatterns, h (nm)

Gap of resistnanopatterns, x (nm)

87 100

586 7584 5079 25

84 100

1082 7579 5068 25

76 100

2572 7563 5045 25

63 100

5056 7545 5027 25

53 100

7545 7534 5018 25

45 100

10037 7527 5014 25

and confining of the ion-beam, and the slight change inetch-rate for the different etch-angles. During the conversionof high density round resist pillars to device nanocells byusing IBE etch, the substrates could be continuously rotatedto achieve a good cell profile, as the reflected ion-beam wasnot confined within the trenches of the high density of resistpillars. However, when converting high density nanoarraysof bottom- or top electrodes on a rotating substrate duringthe dry-etch, the reflected ion-beam, readily confined withinthe trenches of the resist arrays, would damage the fineresist patterns at the high energy, as depicted in figure 3(bi)(top-left image). The top-right image in figure 3(bii) showsthe original fine resist nanopatterns before etching. In thissituation, to prevent the fine resist nanopatterns from damage,it was ascertained that the etching incident and reflectedbeams in the planar surface had to be parallel to the resistarray direction for the effective etching of array bars. Thisprevented the confinement of the reflected residue beamwithin the dense resist nanopatterns. During the dry-etch ofhigh density resist nanopatterns, the shading and absorption ofthe ion-beam energy by the top and side surfaces of the resistpatterns were more significant in terms of unit substrate areaas compared to the loosely distributed nanopatterns. Thus,a higher etching energy (e.g. ion-beam voltage ≥ 230 V)was required. Furthermore, when etching device films ofthe same thickness, a longer time was required for the highdensity resist nanopatterns. As such, for the same dry-etchtime, the etching depth of the device film on one sample

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Figure 3. (a) AFM image of sidewall defects from the common dry-etch and resist lift-off method while the 3 µm× 3 µm inset shows thedevice nanopatterns with treated sidewalls using O2 plasma. (bi) and (bii): FESEM images of the completely damaged (after dry-etching)and the original high density ZEP nanopatterns, respectively. IBE was carried out with the common sample-rotating method; (biii):0.3 mm× 0.3 mm optical image showing an uneven CMP polished portion of a 4′′ wafer while removing the sidewalls; (biv): 1 µm× 1 µmAFM image of Co/Pt/Co pillars after dry-etching without resist lift-off. The scale bars of (bi) and (bii) are 10 nm and 100 nm, respectively.(c) and its inset: AFM images of the converted device nanopatterns of different densities with a ∼5 nm Au film to wrap the ZEP resistnanopatterns for eliminating the sidewalls. The horizontal axis intervals in the left and right images are 1 and 0.25 µm, respectively.(d) AFM image of the converted device nanoarrays, where the gaps were filled with HSQ resist. The inset depicts the dry-etched nanoarraysbefore the HSQ filling. The horizontal axis intervals in the left and right images are 0.20 and 0.25 µm, respectively. (e) Transferred∼100 nm metallic nanocells from resist nanopillars on crossbar circuits. The inset shows the ∼60 nm nanocells on cross-points dry-etchedfrom the crossed resist arrays. (f) AFM image of the slightly lapped device arrays, which were converted from the almost fully dry-etch ofthe resist nanoarrays.

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surface varied with the different density resist nanopatterns.The etching depth in the high density resist nanopatternswas much shallower than that in the loosely distributed resistnanopatterns or bare films. For instance, when etching pureTa film, on which different density resist nanopatterns werelithographed, for 150 s with beam voltage of 350 V and power0.5 mA cm−2 at an etch angle of 86◦, the etched Ta depthwas 46, 42, 35, and 16 nm among resist nanoarrays with ahalf-pitch of 415, 160, 120, and 78 nm, respectively.

3.3. Tackling the defects in nanopattern transfer

Sidewall defects, the complex products of re-deposited metalfilms and burnt/over-cured (aged) resists caused by the highenergy dry-etching, could also result in difficult resist lift-off(as mentioned above) after the etch-transfer of the resistnanopatterns to device nanostructures. They could not bedissolved in solvents and other solutions or fully removed byplasma treatment. The inset (top-right corner) of figure 3(a)shows the remnant sidewalls after O2 plasma treatment for60 s (at 100 W and a gas flow-rate of 50 sccm), forthe nanopatterns in figure 3(a). Accordingly, the sidewallswere difficult to lift off by the usual means of cleaning.Some sidewalls could be removed through the depositionof SiO2 or Al2O3 into the gaps of the device nanopatternsafter the dry-etch, followed by resist lift-off and chemicalmechanical planarization (CMP polishing). However, it washard to achieve a good profile of nanopatterns on the wholewafer surface for the higher sidewalls (usually ≥ the heightof the device nanopatterns). After polishing, some sidewallsremained high at some parts of the wafer surface whilethe sidewalls including device nanopatterns at other partswere polished away (shown in the bottom-left image infigure 3(biii)). A contributing factor was the limitation ofCMP machines, which usually have a ≥8% tolerance errorin polishing uniformity on a wafer (e.g. ≥4′′) surface [22].The difficulty in the resist lift-off was also found when thethickness of the resist nanopatterns was left at less than acertain value after the etch by a high energy ion-beam, dueto the over-cured or burnt fine resist nanopatterns. Hence,in order to minimize the difficulty in resist lift-off, higherresist nanopatterns (namely larger aspect ratio) were requiredusing the common transfer method via dry-etch and lift-offprocedures. This posed a process difficulty for the devicefabrication, as it was hard to achieve a high aspect ratioof ≤70 nm resist nanopatterns, with normal commercialelectron-beam resists, by using a conventional method in thelithography process [20, 23]. As such, the sidewall defectsand difficult lift-off issues were critical obstacles in theconversion of device nanopatterns [23]. This is one majorreason why there has been limited progress reported sofar on practical high density crossbar memory devices withhalf-pitch of ≤100 nm. To overcome the sidewall issuesafter the nanopattern transfer, a few alternative methods toreplace CMP polishing have been reported. For instance, athin layer of Al or Al2O3 film, as an alkaline-soluble interimlayer between the device nanofilm and resist nanopatterns,is reported to be able to eliminate the sidewall defects [24].

After the transfer of nanopatterns, this Al-based film isetched away in an alkaline solution together with the attachedresist residue and sidewalls. However, such an approach wasshown to be only suitable for the device films that possessedhigh tolerance to alkaline solutions. It was unsuitable formultilayer device films containing layers susceptible toalkaline etchants, for example Al, Mg, Zn, Sn, IrMn, Al2O3,ZnO, etc. These layers would be etched away together with theinterim Al film by the alkaline solution. To solve this issue,we developed other novel simple methods, which readilyeliminated the sidewall problems. For example, deposition ofa thin 4–8 nm metal film (e.g. Au, Cr, Ta), by using an e-beamevaporator or low-energy sputtering, before the resist coatingand immediately after the formation of resist nanopatternson the device film via developing, was one means. Afterthe deposition, the thin metal film wrapped the fine resistnanopatterns (any type of e-beam resist) before dry-etching.Figures 3(c) and (a) show the comparison of the etched250–275 nm CoFeB/Al2O3/CoFe nanopatterns, which weretransferred from ZEP resist nanopatterns with and without4–8 nm Au evaporated before IBE dry-etching, respectively.After IBE dry-etching and resist lift-off, it is clear that thesidewalls are prevalent for the magnetic nanopatterns (shownin figure 1(a)) converted from the resist patterns withoutAu coating. On the contrary, when the resist patterns werewrapped by a thin layer of gold, the converted magneticnanopatterns were smooth without sidewall defects (depictedin figure 3(c)). This is because the thin conductive gold filmcould prevent the resist from being burnt during dry-etchingby quickly dissipating the IBE-induced charge and heat.This allowed the resist pattern-residues to readily dissolvein the lift-off solution. Furthermore, when the thin film wasetched into small device structures, the thin metal film locatedbetween the device film and resist residue-patterns could beeasily removed under ultrasonic vibration in solvent duringthe lift-off process after the dry-etch, since the adhesionof the thin metal film to the device film was weak dueto the low-energy deposition, but strong enough to preventthe developer solution (without ultrasonic vibration) frompeeling the whole sheet film on the device film surface in thedeveloping of the resist nanopatterns. The inset of figure 3(c)shows the higher density Co/Pt/Co/Pt nanopatterns (with ahalf-pitch of ∼63 nm) converted using this method.

The sidewall issue could also be mitigated by usingcurable e-beam resists (e.g. HSQ, Al, and Mg based resists),which could be converted to an isolator layer after curing [25].By using dry-etch transfer, the sidewall defects were foundto emerge only after lifting-off the resist pattern-residues.After the dry-etch and before the resist lift-off, there wereno sidewalls exposed as the sidewall metal film was attachedto the sides of the resist patterns. The bottom-right image infigure 3(biv) shows such dry-etched ∼40 nm Co/Pt/Co pillarswith negligible sidewalls. For multilayer device nanopatterns(such as crossbar circuits, where a 5–30 nm thick isolator layerwas usually used to separate the layers), after the transfer ofthe first layer, the sidewall films could be buried by coating thecurable resist again without lifting-off the remaining curableresist nanopatterns after the dry-etch. Hence no sidewall

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defects were present. In addition, the sidewall metal filmattached to the sides of the resist patterns was always lowerthan the surface of resist nanopatterns by using a dry-etchangle smaller than 90◦. Thus, there was no short-circuitingissue after coating the curable resist. The coated resist not onlyacted as the isolator layer after being cured, but also wrappedthe sidewall metal and smoothed the device surface by fillingthe surface pits and gaps among the nanopatterns (even forlarger pitch nanopatterns) after dry-etching. Figure 3(d) shows80 nm nanoarrays in a larger half-pitch of ∼85 nm with thegaps being filled with 85 nm cured HSQ resists, while theinset in the figure (top right) shows the nanopatterns beforethe resist coating. In addition, the thickness of the coatedresist could be adjusted by changing the spin-coating speed orthe resist concentration according to the process requirement.After the coating, the second device layer could be readilyfabricated on the first layer without being affected by thesidewall defects. By using this method, the sidewall defectswere not only readily eliminated, the fabrication process wasalso shortened by abandoning the lift-off procedure for theresist residues after dry-etching. As a result, tri- or multilayerdevices could be easily piled up. For instance, figure 3(e)depicts∼100 nm uniform dry-etched metallic nanocells (withsome resist residues on them) built on crossbar circuitswith a half-pitch of 100 nm × 200 nm. From a physicalgeometry point of view, the membrane devices constructedwith multilayer crossbar-memories can achieve the highestdata storage density in unit volume.

Further investigation results revealed that the sidewalland difficult lift-off issues could also be simply prevented byfully or almost fully converting uniform resist nanopatternsinto device nanopatterns with an accurately calibratedetch-rate. As such, resist nanopatterns and sidewalls wouldalmost be fully etched away during the pattern transfer, whichresulted in the absence of sidewall defects and eliminatedthe procedure of resist lift-off. Moreover, as in the previousmethod, relatively high quality, uniform, and smooth surfacedevice nanopatterns could be achieved due to the removalof the lift-off process and transfer defects. The inset imageof figure 3(e) shows the fine ∼45 nm × 45 nm cells beingdirectly converted by fully etching crossbar HSQ nanopatternsuntil the surface of the cell film. For this method, the requiredheight of the resist nanopatterns could also be lower (withoutrequiring high aspect ratio resist nanopatterns sometimes) incomparison to that used in the common conversion methodvia the dry-etch and lift-off procedures. As no sidewall defectswere present, the uniformity of lapping or CMP polishing forthe removal of the residues on the whole wafer surface afterthe dry-etch could be greatly improved. Thus, this method waseffective in achieving smooth and uniform surfaces of devicenanopatterns on a large area. Figure 3(f) shows an example ofthe converted device nanoarrays after almost fully dry-etchingthe resist nanopatterns, and subsequently slight lapping of thedevice surface to fully remove the resist residues.

3.4. Fabrication of trilayer 3D devices

By using only two cycles of lithography and dry-etchprocesses to fabricate 3D trilayer devices, with reference to

the schematic illustration in figure 1(b), the bottom arrayscontaining cell and bottom electrode films could firstly beconverted from sub-100 nm resist arrays via dry-etching.The conversion proceeded either by fully etching the resistarrays or half-etching and lifting-off high aspect ratio resistnanopatterns wrapped by a 4–8 nm metal film (figure 4(a),from our modified HSQ resist [19]). For the fully dry-etchof resist patterns, the top surfaces of the device arrays(depicted in figure 4(b)) were slightly lapped out subsequentlyafter coating a thin (10–25 nm) SiO2, Al2O3 isolator orcurable HSQ resist layer (to separate the bottom and upperarray circuits). A top-electrode film (20–30 nm) was thensputtered on the clean bottom device arrays and whole wafersurface. Subsequently, another cross-layer of resist arraypatterns was lithographed on the top-electrode film. The topelectrodes and nanocells could be converted from the resistarrays by etching the metallic multilayer device film. Theetching was through the layers of top-electrode and cellfilms till the bottom electrode surface (for retaining bottomelectrodes). As the cell films were etched together with thetop electrodes, the nanocells were formed between two layersof electrode arrays. The cross-points of the two-layer arraysdetermined the cell shapes. Our experimental results criticallyrevealed that with the use of these novel cross-nanoarrays todefine the fine <100 nm cell and top-electrode arrays, thepositions of the fine nanocell and top-electrode nanoarrays(shown in the inset of figure 4(c)) could be readily andaccurately aligned on the high density of fine metallic bottomnanoarray-electrodes, with a half-pitch down to ≤70 nm,without any failure. With these novel procedures, practicalfine nanocells (with multilayer films) were readily fabricatedbetween the high density metallic nanoarrays or crossbarnanocircuits. Once the device was converted, a thin layer ofisolator could be deposited to protect the surface of the device.As such, the complete high density trilayer 3D memorydevice core wrapping practical fine MR nanocells at eachcross point, as depicted in figure 4(c) and its inset, wasfabricated from the two cycles of lithography and dry-etchprocedures. The device in figure 4(c) and the inset wascomposed of two layers of Ta (20 nm) crossbar circuits andembedded magnetic tunnel junction (MTJ) cells (one typeof MR cells) of ∼65 nm at each cross point. A 25 nmAl2O3 layer was used to separate the crossbar circuits witha half-pitch of ∼70 nm. The layer structure of the nanocellsincluded a free layer (CoFeB 2)/tunnelling barrier layer (MgO1)/reference layer (CoFeB 5)/space layer (Ru 0.8)/pinnedlayer (CoFe 3.5)/antiferromagnetic layer (IrMn 8), where alldigital numbers are the thicknesses for each layer in unitsof nanometres. As the magnetization direction of the CoFeBreference layer was fixed by the CoFeB pinned layer throughexchange-coupling, a small external magnetic field, appliedin the film plane, could change the magnetization directionof the CoFeB free layer away from that of the referencelayer. When the magnetization directions in the free andreference layers were parallel, a low resistance state (Rmin,‘0’ state) could be obtained, e.g. ∼21 k� for one MTJ cellin this device (depicted in figure 4(d)). In contrast, when themagnetization directions were antiparallel, a high resistance

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Figure 4. (a) AFM image of high aspect ratio HSQ resist nanoarrays (doped ∼3 nm PtFe nanoparticles) lithographed on top-electrode filmand wrapped by ∼6 nm Au films. (b) AFM image of multifilm device arrays converted from fully etching resist nanoarrays. Duringdry-etching, the ion-beam was parallel to the array direction. (c) FESEM image of a trilayer device wrapping ∼70 nm× 75 nm MTJnanocells at the cross-points (shown in the 0.5 µm× 0.5 µm inset) by using the two cycles of lithography and dry-etch procedures. Thescale bars in (c) are 1 mm. (d) MR curve of a MTJ nanocell.

state (Rmax, ‘1’ state) (e.g. ∼35 k� for the cell) was obtained.The magnetoresistance ratio (namely the on/off ratio) wasdefined by MR% = (Rmax − Rmin)/Rmin, which is about 66%for the memory device shown in figure 4(d). To the best of ourknowledge, the fabrication of such a high density of practicalmemory devices is the first of its kind although it is highlysought after in the data-storage industry.

Further experimental results showed that the crossbardevices, from the simple two cycles of lithography anddry-etch procedures, had the advantage of low contactresistance at the interface between nanocells and topelectrodes. This is because there was a larger and cleanercontact area at the interface as compared to the pit pointcontact of common pillar cells from the common three cycletransfer method. This scalable manufacturing method wasalso evaluated and used for the preparation of devices of lowdensity with any mono- or multifilm-structural cells. It couldalso be used for devices with different sizes, thicknesses, andmaterials (such as semiconductors), since it was relatively

easy to convert nanostructures of semiconductors (e.g. Si) andnon-metallic materials (e.g. AsN and SiN, used in resistiverandom access memory (ReRAM) devices) of differentdensities (particularly in single or a few layers) from theresist nanopatterns via dry-etching. This is the result of thehigher dry etch-rates [24] of semiconductors and non-metallicmaterials compared to the metal and oxide materials used inthis work. Therefore, this simple fabrication method could beused for the preparation of various types of multilayer 3Dnanodevices (e.g. ReRAM, magnetoresistive random accessmemory (MRAM), spintronics and memristor devices), andwould be of great potential for nanodevice industries andtechnologies.

4. Conclusions

In summary, a simple novel manufacturing method toshorten the fabrication process was developed to achieveultrahigh density of practical 3D crossbar nanodevices.

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Nanotechnology 24 (2013) 245303 B Y Zong et al

Through suitable dry-etch angles and energies, as well asdeveloped pattern-transfer methods, the challenges faced inthe transfer of high density nanopatterns and the preparationof trilayer nanodevices has been overcome. The methodologyhas produced 3D crossbar devices with practical metallicnanocells with a new fine scale of ≤70 nm in half-pitch.This fabrication strategy presents a general, cost-effectiveway to fabricate tri- or multilayer metal–cell–metal memorynanodevices, and is possibly capable of catering for densityimprovements in both horizontal and vertical directions tomeet the demands of future data storage and integrated circuitmaps [26, 27].

Acknowledgment

The authors thank Mr S H Soh for his practical support duringthis work.

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