fall 2002 jhu ee787 mmic design student project results...

Fall 2002 JHU EE787 MMIC Design Student Project Results

Supported by TriQuint and Agilent Eesof

Professors Craig Moore and John Penn Low Noise Amplifier—Li Zhimin

Mixer---Jeff Jaso

Medium Power Amplifier—John Brice & Chris Giusto

Post Amplifier—Kerron Duncan & Walter Tates

Frequency Doubler—Ming-Zhi Lai

Voltage Controlled Oscillator—Mark Petty

S-BAND LOW NOISE AMPLIFIER (LNA)

FINAL PROJECT REPORT

December 9, 2002

Zhimin Li

Microwave Monolithic Integrate Circuit (MMIC) Design Course 525.787

Fall 2002 John Hopkins University

2

TABLE OF CONTENTS 1.0 Summary 2.0 Introduction

2.1 Circuit Description 2.2 Design Philosophy 2.3 Trade-offs

3.0 Modeled Performance

3.1 Specification Compliance Matrix 3.2 Predicted Performance

4.0 Schematic Diagrams 5.0 DC analysis 6.0 Test Plan

6.1 Test Equipment 6.2 Turn on Procedure 6.3 S-Parameter Measurement 6.4 Noise Figure Measurement 6.5 IIP3 Measurement

7.0 Conclusion and Recommendations 8.0 Project File 9.0 GDSII (CALMA) Layout file

3

FIGURE 1: CHIP SET FOR THE 2305 – 2360 MHZ WCS AND 2400 – 2497 MHZ ISM

BANDS ......................................................................................................................... 5 FIGURE 2: 300UM DFET DC CURVE ............................................................................... 6 FIGURE 3: INPUT AND OUTPUT STABILITY CIRCLES WITH GAIN AND NOISE CIRCLES .. 7 FIGURE 4: GS GAIN CIRCLE AND NOISE CIRCLE AT F=2.4 GHZ....................................... 8 FIGURE 5: S-PARAMETER PERFORMANCES OF SIMPLIFIED SCHEMATIC LNA (LINEAR

SIMULATION USING 300UM DFET S-PARAMETER FILE) ........................................ 11 FIGURE 6: NOISE FIGURE PERFORMANCE OF SIMPLIFIED SCHEMATIC LNA (LINEAR

SIMULATION USING 300UM DFET S-PARAMETER FILE) ........................................ 11 FIGURE 7: S-PARAMETER PERFORMANCES OF SIMPLIFIED SCHEMATIC LNA (LINEAR

SIMULATION USING 600UM DFET NON-LINEAR TOM3 MODEL) ........................... 12 FIGURE 8: P1DB PERFORMANCE OF SIMPLIFIED SCHEMATIC LNA (HARMONIC

BALANCE SIMULATION USING 600UM DFET NON-LINEAR TOM3 MODEL)........... 12 FIGURE 9: S-PARAMETER PERFORMANCES OF FINAL LAYOUT SCHEMATIC LNA

(LINEAR SIMULATION USING 300UM DFET S-PARAMETER FILE) .......................... 13 FIGURE 10: NOISE FIGURE PERFORMANCE OF FINAL LAYOUT SCHEMATIC LNA

(LINEAR SIMULATION USING 300UM DFET S-PARAMETER FILE) .......................... 13 FIGURE 11: S-PARAMETER PERFORMANCES OF FINAL LAYOUT SCHEMATIC LNA

(LINEAR SIMULATION USING 600UM DFET NON-LINEAR TOM3 MODEL)............. 14 FIGURE 12: P1DB PERFORMANCE OF FINAL LAYOUT SCHEMATIC LNA (HARMONIC

BALANCE SIMULATION USING 600UM DFET NON-LINEAR TOM3 MODEL)........... 14 FIGURE 13: DC BIAS SIMULATION RESULTS ON SIMPLIFIED LNA SCHEMATIC USING

‘ANNOTATE DC SIMULATION’ FUNCTION ............................................................... 15 FIGURE 14: LNA SIMPLIFIED SCHEMATIC WITH S-PARAMETER FILE .......................... 16 FIGURE 15: LNA FINAL LAYOUT SCHEMATIC WITH DFET NON-LINEAR MODEL ......... 17 FIGURE 16: LNA FINAL LAYOUT IN ANACHIP ............................................................. 18 TABLE 1: 600UM DFET DC BIAS POINT .......................................................................... 6 TABLE 2: STABLE FACTOR K AND DELTA ........................................................................ 7 TABLE 3: DESIGN SPEC AND PREDICTED PERFORMANCE ............................................... 9 TABLE 4: DC BIAS SIMULATION RESULTS FOR BOTH STAGES DFET OF LNA .............. 15

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1.0 Summary A Low Noise Amplifier (LNA) operation at S-Band (2.3GHz to 2.5GHz) has been design as part of a project for the MMIC course at the John Hopkins University. The project is a duplex transceiver employing a receive array for the S-Band wireless communications service(WCS) and industrial, scientific, and medical (ISM) frequencies. The LNA is one of the nine unique designs. Each design is contained on a 60 mil square ANACHIP die using the TriQuint TQTRX design process, with vias, 4 mil (100 um) thick wafer and TOM3 FET model in ADS. Agilent Advanced Design Systems (ADS 2002) is used for the design software. The predicted LNA design achieved all design goals including gain greater than 15 dB, noise figure less than 3 dB (1.12dB MAX), input IP3 great than +5dBm (+7dBm), and input/output VSWR 1.5:1. The LNA will be fabricated by TriQuint and tested with in year 2003. 2.0 Introduction A Low Noise Amplifier (LNA) operation at S-Band (2.3GHz to 2.5GHz) has been design as part of a project for the MMIC course at the John Hopkins University. The project is a duplex transceiver employing a receive array for the S-Band wireless communications service (WCS) and industrial, scientific, and medical (ISM) frequencies. The LNA is one of the nine unique designs. Each design is contained on a 60 mil square ANACHIP die using the TriQuint TQTRX design process, with via, 4 mil (100 um) thick wafer and TOM3 FET model in ADS. Figure 1 is a chip set diagram for the 2305 – 2360 MHz WCS and 2400 – 2497 ISM Bands. 2.1 Circuit Description The LNA circuit design was a cascaded two-stage amplifier. 600um DFET (12 fingers X 50um) is used for both stages. In order to achieve a single +5Volt power supply, self-biasing was used for both stages. A series inductor at each source of DFET was used for stabilization. High pass matching networks for input/output ports and inter-stage matching were used for reducing the number of entire chip elements. An active load (300um DFET) for each stage amplifier, which generated 20mA constant bias current, was used for saving chip area. A feedback RC circuit for each stage was added to achieve the better performance of gain, gain ripple and stabilization. 2.2 Design Philosophy Based on its low noise figure and gain characteristics, we choose TriQuint DFET for the LNA design. According to the S-Parameter information of 300um DFET (standard S-parameter file at bias condition Ids=10mA, Vds=2V), two 300um DFETs paralleled together must be used for each stage because of LNA gain and IIP3 issues. From DC curve of 300um DFET, one can see that if Vgs=0V, IDSS=20mA@ Vds=2.5V. See figure 2. 300um DFET active load can be used base on the 300um DFET DC curve for

5

Figure 1: Chip set for the 2305 – 2360 MHz WCS and 2400 – 2497 MHz ISM Bands

6

each stage DC bias. The bias point we chosen for each stage of 600um DFET is same, listed as following Table 1:

Figure 2: 300um DFET DC Curve

First stage Second stage Vds=2.5V Vds=2.5V

Vgs=-0.17V Vgs=-0.17V Ids=20mA Ids=20mA

Table 1: 600um DFET DC bias point

The design process was focused on achieving a stable design, the goals of high gain, low noise figure, high input IP3, lower gain ripple and good input/output port matching across a desired frequency band (2.3GHz to 2.4GHz). First, we need add an inductor to the source pin of DFET to stabilize it. The value, which we found is 2500 pH. Figure 3 shows the input and output stability circles at frequency 2.4GHz in Smith chart. Table 2 shows the stable factor K and ∆ over the frequency range from 500MHz to 5GHz. K>1 and ∆>0, that means the transistor is unconditional stable.

m1VDS=2.500VGS=-0.200000IDS.i=0.011

TriQuint 300um DFET DC Curve

m1VDS=2.500VGS=-0.200000IDS.i=0.011

1 2 3 4 5 6 7 8 90 10

5

10

15

20

0

25

VGS=-2.500VGS=-2.400VGS=-2.300VGS=-2.200VGS=-2.100VGS=-2.000VGS=-1.900VGS=-1.800VGS=-1.700VGS=-1.600VGS=-1.500VGS=-1.400VGS=-1.300VGS=-1.200VGS=-1.100VGS=-1.000VGS=-0.900VGS=-0.800VGS=-0.700

VGS=-0.600

VGS=-0.500

VGS=-0.400

VGS=-0.300

VGS=-0.200

VGS=-0.100

VGS=0.000

VDS

IDS

.i, m

A

m1

7

indep(nscircle) (0.000 to 51.000)

nsci

rcle

indep(gscircle) (0.000 to 51.000)

gsci

rcle

indep(lstabcircle) (0.000 to 51.000)

lsta

bcirc

le

indep(sstabcircle) (0.000 to 51.000)

ssta

bcirc

le

Gain, Noise, Input/Output stability circles

Figure 3: Input and Output stability circles with Gain and Noise Circles

Table 2: Stable factor K and Delta

freq 500.0MHz 1.000GHz 1.500GHz 2.000GHz 2.500GHz 3.000GHz 3.500GHz 4.000GHz

k 1.113 1.086 1.071 1.058 1.045 1.032 1.020 1.010

∆ 1.018 0.651 0.463 0.363 0.297 0.246 0.200 0.155

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Second, in order to achieve as greater gain and lower noise figure as possible, a Gs gain circle and noise circle were drawn on one smith chart. See figure 4. An intersection point between Gs gain circle and noise circle is Γs. Γs = 2.1+j1.15. After Γs was found, an input matching network was calculated using high pass network. The reason using high pass network is to have few chip elements, so that chip area can be saved. The shunt inductor can be used as a part of matching network as well as self-bias inductor.

m1indep(m1)=25gscircle=0.477 / 26.851freq=2.400000GHzimpedance = Z0 * (2.053 + j1.146)

m1indep(m1)=25gscircle=0.477 / 26.851freq=2.400000GHzimpedance = Z0 * (2.053 + j1.146)

indep(gscircle) (0.000 to 51.000)

gsci

rcle

m1

indep(nscircle) (0.000 to 51.000)

nsci

rcle

indep(glcircle) (0.000 to 51.000)

glci

rcle

Figure 4: Gs gain circle and noise circle at f=2.4 GHz

Third, after input matching network was calculated, output matching network need to be calculated as well. In order to provide maximum power transfer to the load, ΓL should equal to S22 conjugate. We found out S22 then the output matching network was calculated. Therefore single stage Low Noise amplifier was designed using 300um DFET S-parameter file. Because we only have 300um DFET S-parameter file, to get 600um DFET, two 300um DFET S-Parameter file need to be paralleled. Now two single 600um DFET low noise amplifiers cascaded together to become one Low Noise Amplifier. The real TriQuint elements that would be required for the layout of final design replaced the ideal elements of the initial LNA design. We call this new one is a simplified schematic since there are no bends, tees MLINs which the final layout need them to finish the chip layout. Do S-Parameter simulation of the simplified low noise amplifier, the simulation result (such as Gain, noise figure, VSWR and DC bias points) will be shown later at Section 3.2 Predicted Performance. This is the linear simulation using S-Parameter file. We need do a linear simulation with non-linear DFET model and harmonic balance non-linear simulation with non-linear DFET model for the non-linear performances of LNA such as P1dB and input IP3. Simply, replaced S-Parameter file by the non-linear model of 600um

9

DFET. Do simulation, the result will be shown later at Section 3.2 Predicted Performance. Regarding layout, the layout process involves interconnection appropriate bends, tees, and MLINs to the optimized LNA design with TriQuint elements. General design guidelines include: keeping the separation as much more as possible between components, sharing vias as many as possible, making sure that a maximum allowable current through a resistor is 1 mA per 1um resistor’s width. After finishing the layout, we need re-simulate the layout schematic (simplified amplifier plus bends, tees and MLINs) , if the simulation result is too much off that of the simplified amplifier schematic, we need re-tune the layout elements until the two simulation results are close enough. 2.3 Trade-offs The major trade-off for designing low noise amplifier is the gain and the noise figure. It is not possible to get maximum gain and minimum noise figure at same time. Therefore, we need trade off the gain and noise figure to get more gain and less noise figure. 3.0 Modeled Performance 3.1 Specification Compliance Matrix Table 2 shows the design specifications and the predicted performance for this LNA.

Table 3: Design Spec and Predicted Performance

Characteristic Spec Goal Simplified

Schematic LNA performance

Final LNA predicted Performance

Frequency 2300 to 2500 MHz 2300 to 2500 MHz 2300 to 2500 MHz Band width > 200 MHz > 200 MHz > 200 MHz Gain > 15 dB 15.5 @ 2.4 GHz 16.5 @ 2.4 GHz Gain ripple ±0.5 dB max < ±0.5 dB < ±0.5 dB Noise figure < 3 dB 1.2 dB 1.2 dB Input IP3 >+5 dBm +7 dBm +7 dBm VSWR, 50 Ohm <1.5:1 input &

output 1.4:1 max 1.6:1 max

Power supply voltage

+5 Volts only +5 Volts only +5 Volts only

Chip size 60 x 60 mil ANACHIP

60 x 60 mil ANACHIP

10

3.2 Predicted Performance The following simulation results show the performances of this low noise amplifier. Figure 5: S-Parameter performances of simplified schematic LNA (linear simulation

using 300um DFET S-Parameter file) Figure 6: Noise figure performance of simplified schematic LNA (linear simulation using

300um DFET S-Parameter file) Figure 7: S-Parameter performances of simplified schematic LNA (linear simulation

using 600um DFET non-linear TOM3 model) Figure 8: P1dB performance of simplified schematic LNA (harmonic balance simulation

using 600um DFET non-linear TOM3 model) Figure 9: S-Parameter performances of final layout schematic LNA (linear simulation

using 300um DFET S-Parameter file) Figure 10: Noise figure performance of final layout schematic LNA (linear simulation

using 300um DFET S-Parameter file) Figure 11: S-Parameter performances of final layout schematic LNA (linear simulation

using 600um DFET non-linear TOM3 model) Figure 12: P1dB performance of final layout schematic LNA (harmonic balance

simulation using 600um DFET non-linear TOM3 model)

11

m 3 freq=2.400GHz dB(S(1,1))= -15.616

m 2 freq=2.300GHz dB(S(2,2))= -18.772

m 1 freq=2.500GHz dB(S(2,1))=15.445

m 8 freq=2.300GHz dB(S(2,1))=16.590

2.2 2.3 2.4 2.5 2.6 2.1 2.7

-20

-15

-10

-5

0

5

10

15

-25

20

freq, GHz

dB(S

(1,1

))

m 3

dB(S

(2,2

))

m 2

dB(S

(2,1

))

m 1 m 8 S -Param e ters

Figure 5: S-Parameter performances of simplified schematic LNA (linear simulation using 300um

DFET S-Parameter file)

m 4f re q = 2 .4 0 0 G H zn f (2 ) = 1 . 2 0 9

m 7f re q = 2 . 4 0 0 G H zN F m i n = 1 . 0 9 3

2 .2 2 .3 2 .4 2 .5 2 .62 .1 2 .7

1 .1 0

1 .1 5

1 .2 0

1 .2 5

1 .3 0

1 .0 5

1 .3 5

fre q , G H z

nf(2

)

m 4

NFm

in

m 7

N o is e F ig u re

Figure 6: Noise figure performance of simplified schematic LNA (linear simulation using 300um


12

m 3 freq=2 .400GHz d B (S(1,1))= -17 .650

m 2 freq=2 .300GHz d B (S(2,2))= -15 .333

m 1 freq=2 .500G H z d B (S(2,1))=16.549

m 8 freq=2 .300G H z d B (S(2,1))=17.778

2 .2 2 .3 2 .4 2 .5 2 .6 2 .1 2 .7

-15

-10

-5

0

5

10

15

-20

20

freq , G H z

dB(S

(1,1

))

m 3

dB(S

(2,2

))

m 2

dB(S

(2,1

))

m 1 m 8 S -P a ram e ter

Figure 7: S-Parameter performances of simplified schematic LNA (linear simulation using 600um

DFET non-linear TOM3 model)

m 1R F p o w e r = 0 . 0 0 0d B m ( V o u t [1 ] ,5 0 ) = 1 5 . 4 9 3

- 1 8 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0- 2 0 2

- 2

0

2

4

6

8

1 0

1 2

1 4

1 6

- 4

1 8

R F p o w e r

dBm

(Vou

t[1],5

0)

m 1

F u n d a m e n ta l O u tp u t P o w e r , d B m @ f= 2 .4 G H z

Figure 8: P1dB performance of simplified schematic LNA (harmonic balance simulation using

600um DFET non-linear TOM3 model)

13

m 1 freq=2.300GHz dB(S(2,1))=15.540 m 2 freq=2.500GHz dB(S(2,1 ))=14.620

m 3 freq=2.400GHz dB(S(2,2))= -22.718 m 4 freq=2.400GHz dB(S(1,1))= -16.675

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.0 2.8

-20

-15

-10

-5

0

5

10

15

-25

20

freq, G H z

dB(S

(1,1

))

m 4

dB(S

(2,1

))

m 1 m 2 dB

(S(2

,2))

m 3

S-Parame ter of Final Layout LNA

Figure 9: S-Parameter performances of final layout schematic LNA (linear simulation using 300um DFET S-Parameter file)

m 5f r e q = 2 .4 0 0 G H zn f ( 2 ) = 1 .1 6 7

m 6f r e q = 2 .4 0 0 G H zN F m i n = 1 . 0 5 7

2 .1 2 .2 2 .3 2 .4 2 .5 2 .6 2 .72 .0 2 .8

1 .0 5

1 .1 0

1 .1 5

1 .2 0

1 .2 5

1 .3 0

1 .3 5

1 .0 0

1 .4 0

f r e q , G H z

nf(2

)

m 5NFm

in

m 6

N o is e F i g u r e o f F i n a l L a y o u t L N A

Figure 10: Noise figure performance of final layout schematic LNA (linear simulation using 300um


14

m 1 freq=2.300GdB(S(2,1))=16.6m 2 freq=2.500GdB(S(2,1 ))=15.8

m 3 freq=2.400GdB(S(2,2))= -22.169 m 4 freq=2.400GdB(S(1,1))= -18.317

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.0 2.8

-20

-15

-10

-5

0

5

10

15

-25

20

freq, G H z

dB(S

(1,1

))

m 4

dB(S

(2,1

))

m 1 m 2 dB

(S(2

,2))

m 3

S -Param e ter of Fina l Layout

Figure 11: S-Parameter performances of final layout schematic LNA (linear simulation using 600um

DFET non-linear TOM3 model)

m 1R F p o w e r=0 .0 0 0d B m (V o ut[1 ],5 0 ) = 1 4 .9 9 6

- 1 8 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0- 2 0 2

- 2

0

2

4

6

8

1 0

1 2

1 4

- 4

1 6

R F p o w e r

dBm

(Vou

t[1],5

0)

m 1

F u n d a m e n ta l O u t p u t P o w e r , d B m

Figure 12: P1dB performance of final layout schematic LNA (harmonic balance simulation using

600um DFET non-linear TOM3 model)

15

4.0 Schematic diagrams and Layout The following schematics are including in this report. Figure 14: LNA simplified Schematic with S-Parameter file Figure 15: LNA final layout schematic with DFET non-linear model Figure 16: LNA final layout in ANACHIP 5.0 DC Analysis Table 4 shows the DC bias simulation results for both stages DFET of LNA. First stage DFET Second stage DFET Vds=2.38 V Vgs=-0.17 V Ids=21.7 mA

Vds=2.38 V Vge=-0.17 V Ids=21.7 mA

Table 4: DC bias simulation results for both stages DFET of LNA

Figure 13 shows DC bias simulation results on simplified LNA schematic using ‘Annotate DC simulation’ function

1.11 uV

1.11 uV

1.11 uV

1.11 uV1.11 uV

1.11 uV

1.11 uV

1.11 uV2.55 V

2.55 V

2.55 V

2.55 V

2.55 V

0 VVout2.55 V2.55 V2.55 V

2.55 V

2.55 V

1.11 uV

2.60 V

2.60 V

2.60 V2.60 V

2.60 V

1.11 uV

2.60 V

2.60 V

2.60 V

2.60 V

2.60 V

4.89 V4.89 V 5 V5 V 5 V 5 V 5 V

206 mV

206 mV

174 mV 174 mV

174 mV174 mV 174 mV

174 mV

0 V

tqtrx_reswR3

type=N-w=10 umR=4700 Ohm

0 Atqtrx_reswR2


0 A

tqtrx_capC5c=0.7 pF

0 A

tqtrx_dindL4Ind=5500pH

21.7 mA

tqtrx_capC10c=20 pF

0 A tqtrx_reswR5

type=NiCrw=20 umR=5 Ohm

21.7 mAtqtrx_reswR6


-21.7 mA


21.7 mA

tqtrx_capC11c=20 pF

0 A

tqtrx_dhsaQ2

Ng=12W=50 um

21.7 mA

-21.7 mA

-508 nA tqtrx_dhsaQ3

Ng=12W=50 um

21.7 mA

-21.7 mA

-508 nA

tqtrx_capC6c=12 pF

0 A

tqtrx_capC2c=12 pF

0 A

tqtrx_capC9c=20 pF

0 A

V_DCSRC1Vdc=5 V

-43.4 mA

tqtrx_capC8c=20 pF

0 A tqtrx_reswR4


21.7 mA

tqtrx_capC1c=20 pF

0 A tqtrx_reswR1


21.7 mA

TermTerm1

Z=ZloadNum=2

0 A

P_1TonePORT1

Freq=RFfreqP=dbmtow(RFpower)Z=50 OhmNum=1

0 A

tqtrx_dhsaQ6

Ng=6W=50 um

21.7 mA

21.7 mA

-21.7 mA

tqtrx_dhsaQ5

Ng=6W=50 um

21.7 mA

21.7 mA

-21.7 mA


21.7 mA

tqtrx_capC7c=1 pF

0 A


508 nA


508 nA

tqtrx_capC3c=1 pF

0 A


21.7 mA

Figure 13: DC bias simulation results on simplified LNA schematic using ‘Annotate DC simulation’

function

16

tqtrx_capC6c=12 pF

tqtrx_capC1c=12 pF

S2PSNP1File="dfet300i10.s2p"

21

Ref

tqtrx_capC8c=1 pF


21

Ref


21

Ref


21

Ref

tqtrx_reswR4


tqtrx_reswR3

type=NiCrw=20 umR=5 Ohm tqtrx_cap

C12c=20 pF

tqtrx_capC10c=20 pF

tqtrx_capC11c=20 pF


tqtrx_capC9c=0.7 pFtqtrx_dind

L8Ind=4500pH


tqtrx_capC7c=1 pF

tqtrx_incNET

Statistical_Info=OnStatistical_Analysis=OffGate_Leakage=Nominaltau_gd=SlowkIs=1.0kCmim=1.0kRni=1.0kRsh=1.0Vp_vari=0

TQTRxNetlist Include

OptionsOptions1

MaxWarnings=10GiveAllWarnings=yesI_RelTol=1e-6V_AbsTol=1e-6 VV_RelTol=1e-6TopologyCheck=yesTemp=16.85

OPTIONS

tqtrx_capC14c=20 pF

tqtrx_reswR6


tqtrx_reswR5


tqtrx_capC13c=20 pF


V_DCSRC1Vdc=5.0 V

tqtrx_dhsaQ2

Ng=6W=50 um

tqtrx_dhsaQ1

Ng=6W=50 um

S_ParamSP1

CalcNoise=yesStep=0.1 GHzStop=2.7 GHzStart=2.1 GHz

S-PARAMETERS

tqtrx_reswR2


TermTerm2

Z=50 OhmNum=2


MeasEqnMeas2

y=vswr(S22)x=vswr(S11)

EqnMeas

TermTerm1

Z=50 OhmNum=1

tqtrx_reswR1


MeasEqnMeas1

gscircle=gs_circle(S, 1.7, 51)sstabcircle=s_stab_circle(S, 51)lstabcircle=l_stab_circle(S, 51)k=stab_fact(S)b=stab_meas(S)glcircle=gl_circle(S, 4, 51)nscircle=ns_circle(0.72, NFmin, Sopt, Rn/50, 51)

EqnMeas


DisplayTemplatedisptemp1"S_Params_Quad_dB_Smith"

TempDisp

Figure 14: LNA simplified Schematic with S-Parameter file

17

tqtrx_sviaV7

tqtrx_mlinTL184

l=18.7 umw=10 um

tqtrx_mlinTL182

l=135 umw=10 um

tqtrx_cornTL183w=10 um

tqtrx_mlinTL181

l=20 umw=10 um

tqtrx_mlinTL86

l=105 umw=10 um


tqtrx_mlinTL88

l=120 umw=10 um

tqtrx_mlinTL178

l=30 umw=10 um

tqtrx_mlinTL177

l=80 umw=10 um

tqtrx_teeTL179

w3=10 umw2=10 umw1=10 um

tqtrx_capC7c=20 pF

tqtrx_mlinTL115

l=110 umw=10 um

tqtrx_mlinTL140

l=140 umw=10 um

tqtrx_mlinTL150

l=130 umw=10 um

tqtrx_mlinTL62

l=80 umw=10 um

tqtrx_teeTL175

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL176

l=20 umw=10 um


tqtrx_mlinTL136

l=27.8 umw=10 um

tqtrx_reswR7


tqtrx_reswR2


tqtrx_mlinTL37

l=44 umw=10 um

tqtrx_reswR5


tqtrx_mlinTL56

l=74 umw=10 um

tqtrx_reswR4


tqtrx_capC10c=0.5 pF

tqtrx_mlinTL119

l=40 umw=10 um


tqtrx_mlinTL159

l=110 umw=10 um


tqtrx_mlinTL173

l=20 umw=80 um

tqtrx_sviaV6

tqtrx_padP6

tqtrx_mlinTL171

l=70 umw=10 um

tqtrx_mlinTL172

l=25 umw=80 um

tqtrx_sviaV5

tqtrx_padP3

tqtrx_padP4

tqtrx_padP8

tqtrx_mlinTL169

l=250 umw=10 um


tqtrx_padP7

tqtrx_mlinTL163

l=140 umw=10 um

tqtrx_mlinTL155

l=225 umw=10 um

tqtrx_mlinTL98

l=127.2 umw=10 um

tqtrx_mlinTL148

l=60 umw=10 um


tqtrx_mlinTL161

l=40 umw=10 um

tqtrx_mlinTL145

l=25 umw=10 um

tqtrx_mlinTL1

l=50 umw=10 um

tqtrx_capC1c=1 pF

tqtrx_teeTL160

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL156

l=80 umw=50 um

tqtrx_mlinTL142

l=120 umw=10 um

tqtrx_mlinTL158

l=25 umw=50 um


tqtrx_padP2


tqtrx_padP1

tqtrx_mlinTL27

l=20 umw=10 um

tqtrx_mlinTL29

l=25 umw=10 um

tqtrx_mlinTL45

l=82 umw=10 um

tqtrx_mlinTL154

l=20 umw=10 um

tqtrx_mlinTL134

l=55 umw=10 um

tqtrx_mlinTL152

l=148 umw=10 um

tqtrx_teeTL153

w3=10 umw2=10 umw1=10 um


tqtrx_mlinTL147

l=450 umw=10 um


tqtrx_cornTL143w=10 umtqtrx_mlin

TL144

l=25 umw=10 um

tqtrx_capC9c=20 pFtqtrx_svia

V3


tqtrx_mlinTL110

l=120 umw=10 umtqtrx_corn

TL139w=10 um

tqtrx_teeTL108

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL121

l=25 umw=10 um


tqtrx_mlinTL133

l=20 umw=10 um

tqtrx_mlinTL131

l=79.2 umw=10 um


tqtrx_mlinTL124

l=700 umw=10 um

tqtrx_dhsaQ4

Ng=6W=50 um

tqtrx_mlinTL126

l=200 umw=10 um

tqtrx_mlinTL128

l=20 umw=10 um


tqtrx_mlinTL129

l=50 umw=10 um

tqtrx_teeTL127

w3=10 umw2=10 umw1=10 um



tqtrx_mlinTL122

l=330 umw=10 um

tqtrx_teeTL120

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL107

l=25 umw=10 um

tqtrx_mlinTL105

l=82 umw=10 um

tqtrx_mlinTL101

l=235 umw=10 um

tqtrx_mlinTL53

l=80 umw=10 um

tqtrx_teeTL111

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL113

l=120 umw=10 um

tqtrx_mlinTL117

l=20 umw=10 um

tqtrx_mlinTL118

l=20 umw=10 um



tqtrx_mrindL5

s=10 umw=10 uml2=230 uml1=230 umn=3.25

tqtrx_mlinTL71

l=20 umw=10 um

tqtrx_dhsaQ3

Ng=12W=50 um

tqtrx_mlinTL52

l=20 umw=10 um

tqtrx_reswR6


tqtrx_mlinTL99

l=50 umw=10 um



tqtrx_capC8c=12 pF

tqtrx_mlinTL103

l=20 umw=10 um

tqtrx_teeTL106

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL104

l=33 umw=10 um

tqtrx_mlinTL109

l=20 umw=10 um


tqtrx_mlinTL50

l=250 umw=10 um


tqtrx_mlinTL48

l=250 umw=10 um

tqtrx_mlinTL96


TL97w=10 um


tqtrx_mlinTL94

l=30 umw=10 um

tqtrx_sviaV2

tqtrx_mlinTL93

l=50 umw=10 um

tqtrx_mlinTL66

l=86 umw=10 um

tqtrx_mlinTL69

l=100 umw=10 um

tqtrx_teeTL92

w3=10 umw2=10 umw1=10 um


tqtrx_mlinTL78

l=50 umw=10 um



tqtrx_mlinTL63

l=100 umw=10 um

tqtrx_mlinTL59

l=20 umw=10 um

tqtrx_capC6c=20 pF

tqtrx_mlinTL67

l=20 umw=10 um

tqtrx_teeTL76

w3=10 umw2=10 umw1=10 um


tqtrx_mlinTL21

l=25 umw=10 um

tqtrx_mlinTL54

l=25 umw=10 um


tqtrx_mlinTL24

l=75 umw=10 um

tqtrx_mlinTL47

l=25 umw=10 um

tqtrx_teeTL46

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL40

l=20 umw=10 um

tqtrx_mlinTL28

l=145 umw=10 um

tqtrx_mlinTL41

l=20 umw=10 um

tqtrx_capC5c=20 pF

tqtrx_mlinTL38

l=75 umw=10 um tqtrx_tee

TL39

w3=10 umw2=10 umw1=10 um

tqtrx_sviaV1

tqtrx_mlinTL36

l=16 umw=10 um

tqtrx_dhsaQ2

Ng=6W=50 um

tqtrx_mlinTL31

l=55 umw=10 um


tqtrx_mlinTL34

l=25 umw=10 umtqtrx_mlin

TL32

l=75 umw=10 um


tqtrx_teeTL30

w3=10 umw2=10 umw1=10 um

tqtrx_capC4c=20 pF

tqtrx_teeTL26

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL25

l=25 umw=10 um

tqtrx_capC3c=1 pF

tqtrx_mlinTL23

l=50 umw=10 um


tqtrx_teeTL20

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL19

l=133 umw=10 um


tqtrx_mlinTL16

l=25 umw=10 um

tqtrx_teeTL15

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL17

l=57 umw=10 um

tqtrx_mlinTL12

l=20 umw=10 um

tqtrx_mlinTL14

l=50 umw=10 um


tqtrx_mlinTL7

l=25 umw=10 um

tqtrx_mlinTL2

l=50 umw=10 um

tqtrx_mlinTL9

l=75 umw=10 um

tqtrx_mlinTL11

l=25 umw=10 um

tqtrx_capC2c=12 pFtqtrx_corn

TL10w=10 um

tqtrx_mlinTL8

l=25 umw=10 um

tqtrx_reswR1


tqtrx_mlinTL6

l=25 umw=10 um tqtrx_dhsa

Q1

Ng=12W=50 um

tqtrx_teeTL5

w3=10 umw2=10 umw1=10 um

Figure 15: LNA final layout schematic with DFET non-linear model

18

Figure 16: LNA final layout in ANACHIP

19

6.0 Test Plan 6.1 Test Equipment The following test equipments or equivalent are necessary to measure the LNA performance:

• Agilent 8510 Network Analyzer • Agilent xxxx Noise figure meter • 5 V DC Power Supply • Synthesized Signal generators to 26 GHz • Power combiner • Spectrum analyzer to 18 GHz • Cascade Model 43 wafer probe station with up to 4 RF probes & 4 DC needle

probes

6.2 Turn On Procedure Extreme caution should be taken when turning on the +5 Volt DC power supply. Make sure the Ground wire is firmly connected on ground PAD before the +5 Volt DC power supply is connected. The required DC voltage and DC current are listed as following:

• The required voltage for the LNA is +5 V DC • The DC current is around 42 mA

6.3 S-Parameter Measurement

• Calibrate the network analyzer from 2 to 2.8 GHz • Position the bias probe on the 5V pad • Position the input probes on the “INPUT” pads • Position the output probes on the “OUTPUT” pads • Make S11, S21, S12, S22 measurements, plot the data and store all data on disk

6.4 Noise figure Measurement

• Calibrate the noise figure meter • Position the bias probe on the 5V pad • Position the input probes on the “INPUT” pads • Position the output probes on the “OUTPUT” pads • Make noise figure measurements and record the data

6.5 Input IP3 testing

• Set f1=2.4 GHz, f2=2.45 GHz

20

• Set each tone power level of output port of power combiner to –10 dBm • Use the spectrum analyzer to measure the delta of power lever between

fundamental frequency and third order frequency • The input IP3 should equal to –10+∆/2 dBm

7.0 Conclusion and Recommendations The LNA design and layout were very successful. It met all the goals. The gain is great than 15 dB over the desired frequency, noise figure is less than 1.3dB much less the spec of 3 dB, and input IP3 is great than +5 dBm. The layout of LNA is so nice and well organized. There is no recommendation. 8.0 Project file The project file has been submitted on 3.5 inch HD diskette 9.0 GDSII (CALMA) Layout file The GDSII layout file has been submitted to instructors

The Design of an S-band Single Balanced Mixer for Starved Diode Operation

Jeffrey Jaso

Johns Hopkins University EE525.787

December 9, 2002

1. Abstract This paper presents the design strategy, simulation results, and final layout of a MMIC S-band single balanced mixer optimized for starved diode operation. The design fits on a 60 mils square die and is to be fabricated using the Triquint Semiconductor TRx process for GaAs. Agilent’s Advanced Design System (ADS) in conjunction with Triquint’s proprietary library was the software tool used for simulation and layout. The RF band of the mixer is 2300-2500MHz; the LO band is 2140-2340MHz; and the IF center frequency is 160MHz. The mixer can be used for both upconversion and downconversion. With a 5V DC bias applied to the diodes and with a 0dBm LO power level, the mixer achieved the following performance:

• Conversion Loss < 10dB • LO VSWR <= 1.6 : 1 • RF VSWR <=2.2 : 1 • IF VSWR < 2.1 : 1 • LO/RF Isolation > 27dB • IF/RF Isolation > 19dB • LO/IF Isolation > 39dB

All prescribed minimum performance specifications were met, and many of the design goals were also achieved.

2. Introduction In selecting the mixer topology the first decision was between double balanced and single balanced approaches. The former affords excellent isolation and good VSWR over a wide bandwidth, but at the expense of greater conversion loss, higher LO drive level, and a more complicated layout due to the ring diode structure. Furthermore, the ring diode structure complicates DC biasing of the diodes. A single balanced mixer, on the other hand, provides moderate isolation, good VSWR over a narrow bandwidth, and low conversion loss—all in a simple structure that lends itself well to DC biasing. Given the emphasis on conversion loss and starved diode operation in this design, coupled with moderate VSWR and isolation requirements, a single balanced approach was the more judicious choice. A single balanced mixer is typically implemented in one of two ways: with a 900 or 1800 hybrid (see Figures 1 and 2)1. While the conversion loss of the two varieties are similar, the LO/RF isolation of the 1800 hybrid is determined mainly by the inherent isolation of the coupler, but the VSWR of the LO and RF ports is mainly set by the VSWR looking into the diode circuitry. The LO/RF isolation of a mixer using a quadrature hybrid, however, is mainly a function of the return loss of the coupler, while the VSWR is dictated by the quality of the terminations at the RF/LO frequencies. An important limitation of the 900 hybrid approach is that it cannot function simultaneously as an upconverter and downconverter. Since this dual capability was an important goal of this design, the 1800 hybrid approach was favored. The inductors provide a DC path to ground as well as an IF return, while the capacitor provides an RF path to ground to allow the diodes to be pumped. To supply DC bias current, the inductors in the actual design are replaced with resistors.

Figure 1: Single Balanced Mixer Using 900 Hybrid

Figure 2: Single Balanced Mixer Using 1800 Hybrid

900

hybrid LO/RF

RF/LORF ground

IF

1800

hybrid LO/RF

RF/LORF ground

IF Σ

∆

3. Specifications and Modeled Performance Table 1 contains the combined specifications for the S-band downconverter and upconverter alongside the modeled performance of the circuit extracted from the final layout. All specifications were met in addition to several of the design goals. The boldfaced results indicate that the design goals were achieved. Figures 3-8 display simulation data for upconversion and downconversion operation at the center frequency and the band edges. Table 1 includes worst-case results. Specs Goal Modeled Results RF Frequency (MHz) 2300 - 2500 N/A 2300 - 2500 LO Frequency (MHz) 2140 - 2340 N/A 2140 - 2340 IF Frequency (MHz) 160 N/A 160 Isolation: LO/RF port (dB) > 10 >=7 27 Isolation: IF/RF (dB) N/A N/A 19 Isolation: LO/IF (dB) N/A N/A 39 Conversion Loss (dB) <= 10 <=7 10 LO power (dBm) <= 7 0 0 VSWR (50 Ω): LO <=2.5:1 <=1.5:1 1.6: 1 VSWR (50 Ω): RF <=2.5:1 <=1.5:1 2.2: 1 VSWR (50 Ω): IF <=2.5:1 <=1.5:1 2.1: 1 DC Bias Voltage (V) 0 -5 N/A 5 Die Size (mil x mil) 60 x 60 60 x 60 60 x 60

Table 1: Specifications and Modeled Results

4. Schematic, Design Notes, and Layout Figure 9 depicts a stripped down version of the final design without transmission line elements. A lumped element realization of a ratrace hybrid designed at the center frequency of the combined RF-LO band (2140 – 2500MHz) performs the function of the balun, with the LO and RF attached to one pair of mutually isolated ports and the two diodes connected to the other pair.2 The 10dB return loss bandwidth of the hybrid is roughly equivalent to the LO/RF band of the mixer. A pair of 30pF DC blocking capacitors (C26 and C27) and one 100pF capacitor allows DC current to flow through the diodes. The current through the diodes is set by the sum of two 1500Ω resistors and the composite DC resistance of the diodes. The optimum DC voltage is 5V. The diodes are overlap diodes rather than FETs with drain and source terminals shorted. A diode width of 80µm resulted in the optimal combination of RF/LO and IF VSWR as well as conversion loss. Two 0.75pF capacitors to ground (C33 and C35) act as simple matching stubs to improve the VSWR at the LO and RF ports. The IF matching network consists of a single series 14nH inductor (L15). In fact, the optimal value would be close to 50nH, but the size of such a component would be prohibitively large. A 500pH inductor (L14) resonates with the bypass capacitor (C29) to provide an RF ground but also to present a high impedance at IF. A 100pF DC blocking capacitor (C30) is placed at the IF port. As large as this value is for a MMIC design, it still represents a compromise since it still appears as a significant impedance at IF. In keeping with the objective of requiring no off-chip components for this design, the largest DC blocking capacitor that could fit was selected. To measure the large signal VSWR at each mixer port, dual directional couplers were placed at each port. Γ was found by calculating the ratio of incident to reflected voltage at the coupled ports of the couplers, and VSWR in turn was determined by the relation: VSWR = (|Γ | + 1)/(| Γ | - 1) The final layout submitted for fabrication appears in Figure 10. Each of the four ports is labeled appropriately. Each signal port is flanked on both sides by ground pads to accommodate test probes. The ratrace coupler occupies the upper half of the chip, with the bottom right consisting of the IF matching network and DC block. Care was taken to keep as much space between inductors as possible to minimize mutual coupling.

5. DC Analysis Figure 11 presents a simplified DC schematic with DC annotations at each node. It is apparent that the DC bias is isolated from the ratrace coupler by the blocking capacitors. With the voltage supply set to 5V, the current flowing through the 80µm diodes is 1.29mA, safely below the maximum 10mA rating of the two 10µm bias resistors. This implies a DC diode resistance of roughly 440Ω. This indicates that the diodes are not fully turned on.

6. Test Plan Figures 12-13 show the test setup for the mixer for upconverter and downconverter operation, respectively. Note that a spectrum analyzer and dual directional coupler need not be present at each port simultaneously. However, whenever a directional coupler is present at a port, each coupled port must be terminated in 50Ω. For upconverter operation, the test plan is as follows:

1. Calibrate: determine insertion loss of directional coupler(s) and cables. 2. Set LO signal generator to midband frequency (2240MHz) and power level such

that 0dBm is present at the LO port. 3. Set IF signal generator to 160MHz and power level such that –10dBm is present

at the IF port. 4. Measure LO+IF, IF, and LO at RF port with spectrum analyzer. Add cable and

coupler losses to calculate conversion loss, LO/RF isolation, IF/RF isolation. Vary bias voltage to obtain optimal values.

5. Calculate VSWR at LO and IF ports: Measure incident and reflected power at respective coupler ports; convert to voltage; and compute gamma and VSWR.

6. Repeat steps 2-5 at lowest LO frequency 2140MHz. 7. Repeat steps 2-5 at highest LO frequency 2340MHz.

(Optional) For downconverter operation, the test plan is as follows:

8. Set LO signal generator to midband frequency (2240MHz) and power level such that 0dBm is present at the LO port.

9. Set RF signal generator to 2400MHz and power level such that –10dBm is present at the RF port.

10. Measure IF, LO, and RF at IF port with spectrum analyzer. Add cable and coupler losses to calculate conversion loss, LO/IF isolation, IF/RF isolation. Vary bias voltage to obtain optimal values.

11. Calculate VSWR at LO and RF ports: Measure incident and reflected power at respective coupler ports; convert to voltage; and compute gamma and VSWR.

12. Repeat steps 2-5 at lowest LO (2140MHz) and RF 2300MHz frequencies. 13. Repeat steps 2-5 at highest LO (2340MHz) and RF 2500MHz frequencies.

Figure 13: Test Setup for Upconverter Operation

Signal Generator

Spectrum Analyzer

Probe

IC on wafer probe station

LO Probe

Dual Directional Coupler

Signal Generator

IF

Spectrum Analyzer

Spectrum Analyzer

DC Supply

0-5V

DC

RF

Figure 14: Test Setup for Downconverter Operation

Signal Generator

Spectrum Analyzer

Probe IC on wafer probe station

LO Probe

Dual Directional Coupler

IF

Spectrum Analyzer

Spectrum Analyzer

Signal Generator

DC Supply

0-5V

DC

RF

Conclusions and Recommendations Even though the MMIC was designed to operate without any necessary external components, the user should take the following precaution. A DC bias at the RF or LO port will not affect the performance of the mixer; however, the RF and LO ports are effectively shorted together at DC. Therefore, a DC blocking capacitor should be used if the user’s LO and/or RF circuitry would present a DC bias to either port. If desired, the IF VSWR can be reduced to below 1.5: 1 with the addition of a 43nH inductor in series with the IF port. The conversion loss will also drop by 0.2dB. Any value up to 43nH will improve the VSWR. In the design of the mixer, prior to incorporating the DC bias a conversion loss less than 7dB was easy to achieve with an LO level of 7dBm. However, the conversion loss specification with DC bias and an LO level of 0dBm was met with little margin to spare. The DC analysis revealed that the diodes are not fully turned on with a 1.29mA bias. However, increasing the current by reducing the value of DC bias resistors lowers the impedance at the diode ports and results in greater conversion loss. This effect can be compensated by the insertion of series RF chokes, IC real estate permitting. A second attempt at this design should investigate this approach, making sure to maintain a symmetrical design to preserve a balanced circuit to ensure high isolation. In other words, the resistance and inductance in the bias path should be divided equally on either side of the diodes, as with the current design. Finally, a layout oversight resulted in the omission of a 0.75pF tuning capacitor at the RF port. The inclusion of this capacitor lowers the RF VSWR to below 1.6: 1 and reduces the conversion loss by 0.5dB.

7. Bibliography 1. Vendelin et al, Microwave Circuit Design: Using Linear and Nonlinear Techniques, John Wiley & Sons, New York, 1990, pp. 536-552. 2. Stephen A. Maas, Nonlinear Microwave Circuits, IEEE Press, New York, 1997, p. 273.

S Band Class F Power Amplifier

John Brice &

Christopher Giusto

Johns Hopkins University MMIC Design

525.787 Fall 2002


Abstract

A MMIC design for an S-Band Class F Power Amplifier has been realized. This design calls for an efficient amplifier with a bandwidth of greater than 200 MHz with a small signal gain of a minimum of 13 dB and a target of 15dB. The design called for a gain ripple of ± 0.5 dB. The output needed should be greater then 20 dBm @ 1 dB compression point. Addition specifications called for a voltage standing wave ratio 1.5 to 1, an efficiency of greater then 20% at the 1 dB compression point. The design had to be fitted on a 60 x 60 mil chip using TriQuint components.


Introduction

Circuit Description:

The circuit was realized first with ideal lumped elements and then with TriQuint components and finally with microstrip line connections. The circuit in figure 6 shows the input match, output match, a harmonic trap, bias circuits, DC feeds, and RF short. The input match was realized with C13 and L1. R1 is a stabilizing resistor used for stability. L1 also is used as a RF block for the gate supply. L4 is the drain RF block. C6 and C7 are capacitor used to short any RF signal which reach the supply. C11 and L16 are used to trap the harmonics. C15 is used to match the load and Block any DC voltage from reaching the load.

Design philosophy:

A 600 um TriQuint GFET was chosen with 6 fingers. This is based on which model gives the closest results to actual performance of the transistors. The GFET model was shown in class to give very good result with the gate bias considered. These transistors were also good power handling transistors.

The bias was chosen to about 25 % of Idss. The voltage was chosen based on limitation of the supply. This gave the bias shown in figure 10. The output was matched using the cripps method in order to maximum power across a 50 ohm load. This value was chosen to be ~10 pF. This value later changed due to tuning. The input match was then chosen to give the best match for the transistors and the output power match. This was realized with a ~59 pF cap and a 3.7 nH inductor (L1). L1 was also used as an RF block for the gate supply. Looking at initial results the design was not stable and the R1 resistor needed to be added in order to stabilize the design. This lowered the gain but also stopped to design from oscillating. In order for the design to provide high efficiency, the drain voltage should look like a square wave and the drain current should look like a triangle. The parallel circuit of C11 and L10 were determined in order to trap or block all harmonics except the fundamental. Two additional components were also used in order to short the second harmonic but it was later removed because the values, which were calculated, were unrealizable. He design suffered efficiency loss and let a small portion of the 2nd harmonic to reach the load. The drain voltage waveforms are shown in figure 12. While the current looks similar to a triangle the voltage looks similar to a square. The waveforms could have been improved but that would require handling higher order harmonics. The design was started from the beginning using TriQuint capacitors and resistors. This was done because the TriQuint resistors and mim capacitor give very good performance agreement with ideal elements except for added

resistance. It was determined that using TriQuint components would help stabilize the design with the added resistance associated with each component as well as give good results. The inductors were chosen after the design was completed. The inductors had to be model in order to give the same performance as the ideal results. This is shown in figure 11. The tuning of the harmonic circuits was done in a similar manor. By tuning the harmonic circuits for VSWR and small signal gain the output waveforms were slightly distorted. This is probably due to the inductances changing from ideal to real and being slightly out of tune with each other. The distortions are shown in figure 12. But upon further examination at marker 22, it is showing that the distortion starts at an RF input power of 11 dBm’s which is around the same point the design reaches the 1 dB compression point.

Trade-offs:

The trade-off for this design was directly associated with which design specifications were the most important. Initially, meeting the 25% was a goal, which could be reached. Efficiencies as high as ~70% were traded off in order to meet small signal gain. Also in order to stable the design the gain suffered. The VSWR was not met and could not be met and meet the other specifications. Also the efficiency suffered because the higher order harmonics were not addressed. This is because additional components would have made the design too large to fit on the 60 x 60 chip requirement. Also additional components would have brought the small signal gain down further. Another keynote is shown in figure 13 that shows that the 2nd harmonic is actually coming through. This is due to the elimination of the last harmonic circuit.

Modeled Performance The following compliance matrix shows the specifications given and our results before and after layout. Specification Pre – Layout Post - Layout Transistor class Class F Yes Yes Frequency 2300 to 2500 MHz Yes Yes Gain 13 dB 12.205 dB 12.297 dB Gain Ripple +/- 0.5 dB 0.052 dB 0.031 dB Power out, @ 1dB 20 dBm 23.78 dBm 23.82 dBm Efficiency 20%, 25% goal 37.175% 37.551% VSWR <1.5:1 >1.5:1 >1.5:1 Supply Voltage +7, -5 Volta Yes Yes Size ANACHIP Yes Yes From the previous matrix you can see that we are meeting the specification for everything except VSWR and Small signal gain. Our VSWR did not meet the spec however the amplifier is not oscillating. We needed to sacrifice VSWR in order to maintain the more important efficiency and power (figure 1, 3). We just missed the gain spec of 13 dB at 12.2 pre - layout and 12.3 post - layout. We were able to maintain an extremely small gain ripple (figure 1, 3). Our efficiency and power level exceeded our goal by over 10% (figure 2,4).

m12freq=2.400GHzdB(S(2,1))=12.205

m13freq=2.300GHzdB(S(2,1))=12.158

m14freq=2.500GHzdB(S(2,1))=12.210

m12freq=2.400GHzdB(S(2,1))=12.205

m13freq=2.300GHzdB(S(2,1))=12.158

m14freq=2.500GHzdB(S(2,1))=12.210

2.2 2.4 2.6 2.82.0 3.0

11.8

11.9

12.0

12.1

12.2

11.7

12.3

freq, GHz

dB(S

(2,1

))

m12m13

m14

2.2 2.4 2.6 2.82.0 3.0

-3.5

-3.0

-2.5

-4.0

-2.0

freq, GHz

dB(S

(1,1

))dB

(S(2

,2))

Figure 1 Pre - layout, small-signal responses. Gain, VSWR.

14 16 18 20 22 2412 26

9

10

11

12

8

13

Fund. Output Power, dBm

m2

m1

Transducer Power Gain, dB

-966.4m

23.78

Gain Compressionbetween markers, dB

Output Powerat Marker m2, dBm

m4RFpower=15.000(LINEAR)=17.060m5

indep(m5)=15.000plot_vs(dB(Vload[1]), RFpower)=13.824

m6RFpower=15.000PAE=37.175

m4RFpower=15.000(LINEAR)=17.060m5

indep(m5)=15.000plot_vs(dB(Vload[1]), RFpower)=13.824

m6RFpower=15.000PAE=37.175

2 3 4 5 6 7 8 9 10 11 12 13 14 151 16

5

10

15

20

25

30

35

0

40

RFpower

(LIN

EA

R)

m4

dB(V

load

[1])

m5

PA

E

m6

Figure 2 Pre – Layout large – signal responses. Power Added Efficiency, Output power at 1 dB compression point.

m12freq=2.400GHzdB(S(2,1))=12.297

m13freq=2.300GHzdB(S(2,1))=12.266

m14freq=2.500GHzdB(S(2,1))=12.282

m12freq=2.400GHzdB(S(2,1))=12.297

m13freq=2.300GHzdB(S(2,1))=12.266

m14freq=2.500GHzdB(S(2,1))=12.282

2.2 2.4 2.6 2.82.0 3.0

11.8

11.9

12.0

12.1

12.2

11.7

12.3

freq, GHz

dB(S

(2,1

))

m12m13 m14

2.2 2.4 2.6 2.82.0 3.0

-4.0

-3.5

-3.0

-2.5

-4.5

-2.0

freq, GHz

dB(S

(1,1

))dB

(S(2

,2))

Figure 3 Post – Layout Small signal responses

14 16 18 20 22 24 12 26

9 10 11 12

8

13

Fund. Output Power, dBm

m2 m1

Transducer Power Gain, dB

-952.2m

23.82

Gain Compression between markers, dB

Output Power at Marker m2, dBm

m4 RFpower=15.000 (LINEAR)=17.154 m5

indep(m5)=15.000 plot_vs(dB(Vload[1]), RFpower)=13.866

m4 RFpower=15.000 (LINEAR)=17.154 m5

indep(m5)=15.000 plot_vs(dB(Vload[1]), RFpower)=13.866

m6 RFpower=15.000 PAE=37.551

2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 16

5

10

15

20

25

30

35

0

40

RFpower

(LINEA

m4

dB(Vload[1])

m5

PAE

m6

Figure 4 Post – Layout large Signal Reponses Schematic Diagrams and Layout Simplified Schematic (pre-layout)

Vload

Vinput

Vs_highVs_low

Vdrain

S_ParamSP1

Step=Stop=3 GHzStart=2 GHz

S-PARAMETERS

HarmonicBalanceHB1

SweepPlan="Coarse"SweepVar="RFpower"UseKrylov=autoOrder[1]=5Freq[1]=RFfreq

HARMONIC BALANCE

VARVAR1

RFpower=1.0Vlow=-1.53 VVhigh=7.0 VZload=50RFfreq=2.4 GHz

EqnVar

I_ProbeIload

TermTerm1

Z=50.0Num=2

P_1TonePORT1


I_ProbeI_input

tqtrx_mrindL4

s=10 umw=7.5 uml2=550 uml1=550 umn=8.5

tqtrx_capC13c=59.6 pF tqtrx_mrind

L16

s=10 umw=35 uml2=50 uml1=50 umn=0.75

tqtrx_mrindL1

s=8.28 umw=18.02 uml2=300 uml1=300 umn=3.75

tqtrx_reswR1


tqtrx_capC15c=10 pF


SweepPlanFine

SweepPlan=UseSweepPlan=Start=11 Stop=16 Step=0.2 Lin=

SWEEP PLAN

SweepPlanCoarse

SweepPlan="Fine"UseSweepPlan=yesStart=1 Stop=11 Step= Lin=8

SWEEP PLAN

PAEPAE1PAE1=pae(Vload,0,Vinput,0,Vs_high,0,Iload.i,I_input.i,Is_high.i,1,1)

PAE



V_DCSRC2Vdc=Vlow

I_ProbeIs_low

tqtrx_incNET



I_ProbeI_Drain

V_DCG3Vdc=Vhigh

I_ProbeIs_high

tqtrx_ghsaQ1

Ng=6W=100 um

Figure 6 Schematic (post-layout)

Vinput

Vload

Vs_low

Vs_high

tqtrx_padP6

tqtrx_mlinTL72

l=40 umw=100 um

tqtrx_sviaV4

I_ProbeI_input

P_1TonePORT1


TermTerm1

Z=50.0Num=2

tqtrx_mlinTL38

l=151.78 umw=10 um


tqtrx_mlinTL39

l=64 umw=10 um

tqtrx_mlinTL26

l=35.535 umw=10 um


tqtrx_mlinTL24

l=54.5 umw=10 um

tqtrx_mlinTL28


TL36w=10 um

tqtrx_teeTL10

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL11

l=25 umw=10 um


tqtrx_mlinTL14

l=25 umw=10 um

tqtrx_teeTL13

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL15

l=25 umw=10 um

tqtrx_mlinTL21

l=60.5 umw=10 um


tqtrx_mlinTL23

l=35.535 umw=10 um

tqtrx_padP1

I_ProbeIload

HarmonicBalanceHB1

SweepPlan="Coarse"SweepVar="RFpower"UseKrylov=autoOrder[1]=5Freq[1]=RFfreq

HARMONIC BALANCESweepPlanCoarse

SweepPlan="Fine"UseSweepPlan=yesStart=1 Stop=11 Step= Lin=8

SWEEP PLAN

SweepPlanFine

SweepPlan=UseSweepPlan=Start=11 Stop=16 Step=0.2 Lin=

SWEEP PLAN S_ParamSP1

Step=Stop=3 GHzStart=2 GHz

S-PARAMETERS

tqtrx_incNET



PAEPAE1PAE1=pae(Vload,0,Vinput,0,Vs_high,0,Iload.i,I_input.i,Is_high.i,1,1)

PAEH B 1 T o n e P s w p S u b _ p a l i bX 2

VARVAR2

_w=15.97_l=100_n=1.5

EqnVar


tqtrx_mlinTL82

l=15 umw=10 um

VSWRVSWR1VSWR1=vswr(S11)

VSWR

VSWRVSWR2VSWR2=vswr(S22)

VSWR

I_ProbeIs_low

V_DCSRC2Vdc=Vlow

I_ProbeIs_high

V_DCG3Vdc=Vhigh

tqtrx_teeTL2

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL1

l=25 umw=10 um

tqtrx_mlinTL3

l=25 umw=10 um

tqtrx_mlinTL5

l=160 umw=10 um

tqtrx_mlinTL32

l=54 umw=10 um

tqtrx_mlinTL35

l=66 umw=10 um


tqtrx_mlinTL31

l=53 umw=10 um


tqtrx_mrindL1

s=8.28 umw=18.02 uml2=300 uml1=300 umn=3.75

tqtrx_capC15c=10 pF

tqtrx_ghsaQ1

Ng=6W=100 um

tqtrx_reswR1


tqtrx_mlinTL4

l=25 umw=10 um


tqtrx_mlinTL7

l=25 umw=10 um

tqtrx_teeTL9

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL8

l=25 umw=10 um

tqtrx_mlinTL6


TL30w=10 um

tqtrx_padP3

tqtrx_padP2

tqtrx_mlinTL80

l=15 umw=10 um

tqtrx_teeTL56

w3=10 umw2=10 umw1=10 um

tqtrx_mlinTL59

l=30 umw=10 um

tqtrx_mlinTL55

l=127.09 umw=10 um


tqtrx_mlinTL53

l=27.78 umw=10 um


tqtrx_mlinTL81

l=15 umw=10 um

tqtrx_sviaV8

tqtrx_mlinTL40

l=237.25 umw=10 um

tqtrx_teeTL65

w3=10 umw2=10 umw1=10 um

tqtrx_padP4

tqtrx_mlinTL77

l=25 umw=10 um


tqtrx_mlinTL78

l=20.25 umw=10 um


tqtrx_mlinTL66

l=81.25 umw=10 um


tqtrx_mlinTL75

l=40 umw=10 um

tqtrx_mlinTL79

l=30 umw=10 um

tqtrx_mrindL4

s=10 umw=7.5 uml2=550 uml1=550 umn=8.5

tqtrx_mlinTL83

l=15 umw=10 um tqtrx_svia

V7

VARVAR1

RFpower=1.0Vlow=-1.53 VVhigh=7.0 VZload=50RFfreq=2.4 GHz

EqnVar

Figure 7

Final Layout For this layout we tried to keep things simple and use as little space as possible.

Figure 8 DC Analysis The following shows DC schematic (simplified) with bias check.

0 V

0 V 0 V

0 V

0 VVload

0 VVinput

6.13 V

6.13 V

6.13 V

7 V

-1.53 V

0 V

0 V

-1.53 V

-1.53 V

-1.53 V

-1.53 V

7 V7 VVs_high

-1.53 V

-1.53 VVs_low

6.13 VVdrain

I_ProbeIload

0 A

TermTerm1

Z=50.0Num=2

0 AP_1TonePORT1


0 A

I_ProbeI_input

0 A

tqtrx_mrindL4

s=10 umw=7.5 uml2=550 uml1=550 umn=8.5

37.7 mA


0 A

tqtrx_mrindL16

s=10 umw=35 uml2=50 uml1=50 umn=0.75

0 A

tqtrx_mrindL1

s=8.28 umw=18.02 uml2=300 uml1=300 umn=3.75

-30.2 uA

tqtrx_reswR1


0 A tqtrx_capC15c=10 pF

0 A


0 A


0 Atqtrx_capC6c=20.0 pF

0 A

V_DCSRC2Vdc=Vlow

30.2 uA

I_ProbeIs_low

-30.2 uA

I_ProbeI_Drain37.7 mA

V_DCG3Vdc=Vhigh

-37.7 mA

I_ProbeIs_high

37.7 mA

-37.7 mA

tqtrx_ghsaQ1

Ng=6W=100 um

37.7 mA

-37.6 mA

-30.2 uA

Figure 9

BiasVDS=7.000VGS=-1.500000IDS.i=0.041

m2VDS=1.400VGS=0.000000IDS.i=0.175

Use with FET_curve_tracer Schematic Template

BiasVDS=7.000VGS=-1.500000IDS.i=0.041

m2VDS=1.400VGS=0.000000IDS.i=0.175

1 2 3 4 5 6 7 8 90 10

50

100

150

0

200

VGS=-3.000VGS=-2.700VGS=-2.400VGS=-2.100VGS=-1.800VGS=-1.500VGS=-1.200VGS=-0.900VGS=-0.600VGS=-0.300

VGS=0.000

VDS

IDS

.i, m

A

Bias

m2

Figure 10

tqtrx_incNET

Statistical_Info=OnStatistical_Analysis=Of fGate_Leakage=Nominaltau_gd=SlowkIs=1.0kCmim=1.0kRni=1.0kRsh=1.0Vp_vari=0


LL14

R=L=97.30442304 pH

tqtrx_mrindL15

s=10 umw=10 uml2=59 uml1=59 umn=1

S_ParamSP1

Step=Stop=10.0 GHzStart=1.0 GHz

S-PARAMETERS

TermTerm4

Z=50 OhmNum=4

TermTerm3

Z=50 OhmNum=3

TermTerm1

Z=50 OhmNum=1

TermTerm2

Z=50 OhmNum=2

Figure 11

100 200 300 400 500 600 700 8000 900

0

50

100

150

-50

200

2

4

6

8

0

10

time, psec

ts(I

_Dra

in.i)

, mA ts(V

drain), V

Figure 12

m22time=200.0psecRFpower=11.000000ts(Vload)=3.324

m22time=200.0psecRFpower=11.000000ts(Vload)=3.324

100 200 300 400 500 600 700 8000 900

-4

-2

0

2

4

-6

6

-50

0

50

-100

100

time, psec

ts(Iload.i), mAts

(Vlo

ad),

Vm22

Figure 12 Output Waveforms

2.00G 4.00G 6.00G 8.00G 10.0G0.000 12.0G

-150

-100

-50

0

-200

50

Output Spectrum, dBm

Figure 13 Output Spectrum

Test Plan Use Cascade probe station to connect the probes to the RF in and RF out ground signal ground pads. Connect the 7 and –5 volt supplies to the VGG and VDD pads respectfully. Use the VNA 8510 to measure all small signal data. Use a spectrum analyzer along with any needed power meters to measure the large signal aspects. Conclusion

A class f power amplifier has been realized. Due to the chip size and trade offs all of the required specifications were not met. All of the specifications were met but those, which were not met, came reasonable close. The design was simulated, laid out and analyzed. The design does demonstrate classical class F characteristics and exceed our expectation for this project. This project allowed us to grow as RF MMIC designers.

References Steven C. Cripps,”RF Power Amplifiers for Wireless Communications,” Artech House, 1999, chapters 3, 5, 8. Fredrick H. Raab, “Maximum Efficiency and Output of Class-F Power Amplifiers,” IEEE transactions, Vol 49, NO.6, JUNE 2001, pp 1162-1166. A.N. Rudiakova and V.G. Krizhanovski, “Driving Waveforms For Class-F Power Amplifiers,”IEEE MTT-S Digest, 2000, pp 473-476. Moore, Craig and Penn, John. Class Handouts. JHU/APL. 2002.

MMIC Design Project S Band Post Amplifier

By: Kerron Duncan and Walter T. Tates Due Date: 12/09/02

EE525.787

Table of Contents Abstract 3 Introduction 4 Circuit Description Design Philosophy 4 Trade-offs 5 Modeled Performance 6 Specification Compliance Matrix 6 Predicted Performance 6 Schematic Diagrams 7 DC Analysis 8 Test Plan 9 Linear Parameters 9 Power Measurements 9 Conclusion & Recommendations 10

Abstract This report documents the design of a post amplifier for primary use at 2.4GHz and using the Triquint TRx process. The design was produced as part of the MMIC Design Course taught at Johns Hopkins University during the Fall 2002 semester. The post amplifier was designed for use in an S-band wireless communications service (WCS) and industrial, scientific, and medical (ISM) frequencies. The design software used to design the post amplifier was Agilent's Advanced Design System 2002C (ADS). The elements used were custom model elements based on Triquint process. The design was laid out on a 60 x 60 mil Anachip.

INPUT (RF) OUTPUT (RF)

+ 5 V

- 5 V

Introduction Circuit Description The circuit topology selected for the design was a cascaded two-stage amplifier layout, which requires two power supplies (of opposite polarity). The matching networks were designed using lumped element topology. Design Philosophy The design specifications of the post amplifier called for an emphasis to be placed on gain and IP3. In the early stages of this design, a series of ideal case design using both the GFET and DFET transistor models sized at 300 and 500 um. It was determined that the 500 um GFET was the optimal choice device for this sort of application. Due to the gain requirement of 12 dB or more, we decided to use 300 um for the first stage and a 500 um for the second stage. The first step in designing the post amplifier was to determine where the device should be biased. This stage was made fairly simple by utilizing ADS’s Amplifier=> DC and Bias Point Simulations => and FET IV Curves template. For maximum gain, we already had in mind that we wanted to bias the device at IDSS 1/2. By correctly using the template, we determined that we wanted to bias the first stage at: Ids = Idss/2 = 83mA/2 = 41.5mA @ 5 V = Vds, 900 mV = Vgs And the second stage at: Ids = Idss/2 = 138mA/2 = 69mA @ 5 V = Vds, 900 mV = Vgs The next step in the design was to determine the input and output matching circuitry for the first and second stages separately. With the Cripps method in mind, this was process was accomplished through the use of ADS’s Amplifier=>S-parameter Simulations=> S-parameters, noise figure...etc template. Ideal elements were used for the first iteration of designs for each stage. Upon completing the matching networks for each stage, both stages were optimized for optimal gain, output power, and return loss. The results were analyzed using both linear and nonlinear simulated data. The two separate stages were than combined and the overall performance of the amplifier is optimized. After satisfactory performance is obtained using the ideal elements in the combined two-stage design, the ideal elements are replaced by Triquint elements. Special attention was given to the Triquint inductors as have been shown to be lossier than ideal inductors. The final stage of the design process was to shift the design from schematic in layout. The circuit was tweaked and placed element by element into the given 60 x 60 mil anachip frame. Microstrip lines, tees, and vias were substituted for there ideal counterparts.

Trade-offs Two trade-offs considered in the design stemmed from the fact that the design was implemented using a dual-supply bias network. One trade-off considered in the design was that the correct sequencing of turning on/off power supplies was critical to avoid device burnout. Another trade-ff encountered in the design was that of space, since by utilizing two power supplies, we also had to add extra bias inductors.

Modeled Performance Specification Compliance Matrix

Specification Goal Triquint Elements Pre Layout

Final Layout Schematic

Frequency 2300 to 2500 MHz 2300 to 2500 MHz

2300 to 2500 MHz

Bandwidth >200 MHz > 700 MHz > 700 MHz Gain >12 dB 15dB, Goal > 15dB > 15dB Output IP3 > +20 dBm > +22 dBm > +22 dBm VSWR, 50 Ohm <1.5:1 input & output 1.51:input

1.8:1 output 2.1:1:input 1.3:1 output

Supply Voltage +/- 5 Volts; +5 Volts Goal +/- 5 Volts +/- 5 Volts Predicted Performance

m1freq=2.350GHzdB(S(2,1))=15.854

2.1 2.2 2.3 2.4 2.5 2.62.0 2.7

12

13

14

15

16

17

11

18

freq, GHz

dB(S(2,1))

m1

GAIN

m3freq=2.350GHzdB(S(1,1))=-8.907

m2freq=2.350GHzdB(S(2,2))=-16.933

2.1 2.2 2.3 2.4 2.5 2.62.0 2.7

-15

-10

-5

-20

0

freq, GHz

dB(S(1,1))

m3

dB(S(2,2))m2

ISOLUTION

SMALL SIGNAL CHARACTERISTICS LAYOUT TRIQUINT ELEMENTS

- 4 - 2 0 2 4 6 8- 6 1 0

2 4

2 6

2 8

3 0

3 2

3 4

2 2

3 6

R F p o w e r

ipo1

O U T P U T IP 3 V S . I N P U T P O W E R

10 MHz Frequency Spacing

Schematic Diagrams

Vs_low

Vload

TermTerm1

Z=50 OhmNum=1

S_ParamSP1

Step=0.05 GHzStop=3 GHzStart=2 GHz

S-PARAMETERS

tqtrx_incNET1


V_DCSRC7Vdc=Vlow V

I_ProbeIs_low

V_DCSRC5Vdc=Vhigh V

I_ProbeIs_high

tqtrx_ghsaQ2

Ng=6W=83 um

I_ProbeI_Probe3

tqtrx_reswR3


tqtrx_reswR4


tqtrx_capC7c=10 pF

tqtrx_capC5c=10 pF

tqtrx_mrindL20

s=10 umw=10 uml2=325.931 uml1=204.683 umn=3

tqtrx_mrindL19

s=10 umw=10 uml2=325.931 uml1=204.683 umn=3


tqtrx_mrindL1

s=10 umw=10 uml2=250.217058 uml1=110 umn=2

I_ProbeIload

TermTerm2

Z=50 OhmNum=2

tqtrx_reswR1


tqtrx_reswR2


tqtrx_mrindL21

s=10 umw=10 uml2=325.931 uml1=204.683 umn=3

tqtrx_mrindL8

s=10 umw=10 uml2=300.96 uml1=410.4 umn=3

tqtrx_capC1c=10 pF

tqtrx_capC4c=10 pF

tqtrx_mrindL2

s=10 umw=10 uml2=213.6 uml1=277.4 umn=4tqtrx_cap

C3c=1.7 pF

tqtrx_capC2c=10 pF

VARVAR3

Zload=50RFfreq=2.35 GHz

EqnVar

VARVAR1RFpower=-10

EqnVar

VARVAR2

Vlow=-5Vhigh=5

EqnVar

tqtrx_mrindL3

s=10 umw=10 uml2=325.931 uml1=204.683 umn=3

I_ProbeI_Probe2

tqtrx_ghsaQ1

Ng=6W=50 um

DC Analysis

-5 VVs_low

-4.96 V-4.96 V

0 V -849 mV

-849 mV

-849 mV

-849 mV -883 mV

-883 mV-883 mV

-883 mV-883 mV

-883 mV-883 mV

4.82 V

4.82 V

0 V

0 V 0 V4.74 V4.74 V

0 V

4.82 V 4.82 V

4.82 V

4.74 V

4.74 V

4.74 V

5 V

5 V5 V

5 V

5 V

-849 mV

5 V

4.74 V

4.82 V -883 mV

-849 mV

I_ProbeIs_low-26.2 mA

I_ProbeI_Probe2

43.7 mA

tqtrx_mrindL2

0 A

tqtrx_ghsaQ1

Ng=6W=50 um 43.7 mA

-43.7 mA

-5.41 uA

tqtrx_ghsaQ2

Ng=6W=83 um 70.1 mA

-70.1 mA

-8.78 uA tqtrx_capC6c=1.76 pF

0 A

tqtrx_mrindL1

0 A

tqtrx_mrindL20

-13.0 mA

tqtrx_mrindL21

-13.1 mA

tqtrx_reswR3

13.0 mA

tqtrx_mrindL8

0 A

tqtrx_reswR2

13.1 mA

tqtrx_capC2

0 A

tqtrx_reswR4

13.0 mA

tqtrx_mrindL19

-83.1 mA

VARVAR2

Vlow=-5Vhigh=5

EqnVar

VARVAR3

Zload=50RFfreq=2.35 GHz

EqnVar

VARVAR1RFpower=-10

EqnVar

tqtrx_reswR1

13.1 mA

tqtrx_mrindL3

-56.8 mA

I_ProbeIs_high

140 mA

TermTerm1

Z=50 OhmNum=1

0 A

S_ParamSP1

Step=0.05 GHzStop=3 GHzStart=2 GHz

S-PARAMETERS

tqtrx_incNET1


SRC5Vdc=Vhigh V

-140 mA

I_ProbeI_Probe3

70.1 mA

tqtrx_capC7c=10 pF

0 A

tqtrx_capC5c=10 pF

0 A

I_ProbeIload

0 A

tqtrx_capC1c=10 pF

0 A

tqtrx_capC4c=10 pF

0 A

tqtrx_capC3c=1.7 pF

0 A

Test Plan The following items and test procedures are recommended to test the S-band post amplifier Linear Parameters Equipment: Vector network analyzer (Agilent 8510) Probe Station Bias Supplies Procedure:

• Calibrate the network analyzer from 0.45 to 10 GHz • Place the bias probe on the pad of the chip labeled “5V” and “NEG5V”. • Place probe tips on the designated pads. The input port is labeled “IN” and the

output port is labeled “OUT”. • Turn on the two power supplies. • Record data.

Power measurements Equipment: Signal Generator

Spectrum Analyzer Procedure:

• Connect the signal generator probe to the input pad of the amplifier chip, which is the port marked “IN”.

• Connect the spectrum analyzer probe to the output pad of the amplifier chip which is the port marked “OUT”.

• Place the bias probe on the pad of the chip labeled “5V” and “NEG5V”. • Power supplies. • For Pin vs. Pout set the generator to the frequency of interest and sweep the power

up to, but not exceeding, 10 dBm. • Record measurements from spectrum analyzer after each interval.

Conclusion & Recommendations In conclusion, we noted that we could have optimized one stage for VSWR and weighted this goal a little more than the others possibly. However, it would have involved a trade-off in gain (or noise figure). Finally, a more thorough Monte Carlo analysis could have been done in order to make the design more robust and less dependent on device variation.

WCS Band Frequency Doubler Design

Using Triquint TQTRx Process

by

Ming-Zhi Lai

December 2002

JOHNS HOPKINS UNIVERSITY EE525.787 MMIC Design

Instructors: C. Moore, J. Penn

Abstract

WCS BAND FREQUENCY DOUBLER DESIGN

by Ming-Zhi Lai

A balanced frequency doubler MMIC design is presented in this report. Given

the performance requirements, the doubler was designed utilizing Agilent’s

Advanced Design System (ADS) package bundled with Triquint TQTRx design

kit, and was laid out on a 60 x 60 mil Anachip. Along with other designs for the

MMIC design class, the frequency doubler will be part of a chip set for use in the

WCS band transceiver application.

TABLE OF CONTENTS

1 Introduction ..................................................................................................................4 1.1 Circuit Description ........................................................................................4 1.2 Design Philosophy.........................................................................................4 1.3 Trade-Offs.......................................................................................................5

2 Schematic Diagrams ....................................................................................................7 3 Modeled Performance...............................................................................................10

3.1 Specification Compliance Matrix ..............................................................10 3.2 Predicted Performance ...............................................................................11

4 DC Analysis.................................................................................................................19 4.1 Class AB Amplifier ......................................................................................19 4.2 Output Stage Amplifier...............................................................................19

5 Test Plan ......................................................................................................................20 5.1 Test Equipment............................................................................................20 5.2 Test Setup......................................................................................................20 5.3 Test Procedures............................................................................................21

6 Conclusion and recommendation ...........................................................................21

WCS Band Frequency Doubler Design Lai, December 2002

4

1 INTRODUCTION

1.1 Circuit Description

The designed frequency doubler will work at the LO port in the applications

operating under Wireless Communication Service (WCS) band, which is from

2305 to 2360 MHz. The doubler’s input frequency ranges from 1070 to 1170

MHz, and output from 2140 to 2340 MHz.

The schematic consists of three parts, which are the 180-degree hybrid, the

multipliers, and the output stage amplifier. The 180-degree hybrid provides two

output signals, with 180-degree phase difference to each other, feeding to the

frequency multipliers.

The multiplier is a GFET biased at the point close to the pinch-off region of the

FET DC IV curve. Operating at this bias point can generate strong second

harmonic frequency output, and yet keep the higher order frequencies low in

magnitude.

Due to the balanced configuration of design, combine the multiplier outputs

from both branches will ideally eliminate all the odd-order harmonic frequencies.

The second harmonic frequency, along with other weak higher-even-order

components, will be boosted to the desired output power level by the last stage

amplifier.

1.2 Design Philosophy

1.2.1 180 Degree Hybrid

In the beginning phase of the project, there are several approaches to design the

frequency doubler. One of them is to drive the multiplier hard to generate

harmonic components and the filter out unwanted frequencies. The balanced

configuration was adopted because it has the advantage of the simplicity of the


4

circuitry, since the filter stage design could be bypassed. Due to the size

limitation of the anachip and the low operating frequency, the width and line

spacing of the spiral inductors in the hybrid has decreased half to 5 um to

minimize the size and save the chip space. This results in more resistance in the

Triquint inductors, and creates more attenuation of the signal. More

amplification at the output stage is therefore required to compensate the loss

here.

1.2.2 Class AB Amplifier (Multiplier)

The 600 um (100X6) GFET was chosen for use in the multiplier because of its

power handling capability and ability to generate stronger second harmonic

frequency. The GFET is biased at Vgs=-2V and Ids=10mA, which is very close

to the pinch-off region. A 200 ohm shunt resister at the input side is introduced

to provide a connection point for the bias voltage, Vgs.

1.2.3 Output Stage Amplifier

The output stage utilizing another 600 um (100X6) GFET, no input matching

network since this transistor already has –10 dBm S11 without any matching

circuitry, which is already sufficient for our application. Output matching

network has been designed to have better output VSWR, since the output power,

by specification requirement, is not high (0 dBm), and with the VSWR optimized

OMN, this amplifier has a very high power compression point already..

1.3 Trade-Offs

The first trade-off I have encountered in the project is the size of the hybrid and

the loss. Due to the relatively low frequency, the size of the hybrid would be very

remarkably large. With limited space in Anachip, I have to compromise the loss

with the space. In this design project, the loss is two more dB, which can be

easily compensate by either the class AB amplifier or the output stage amplifier.


4

Second would be the trade-off between the power gain and the current. Worries

about the loss in the hybrid make me try to achieve higher power gain at both the

class AB amplifier and the output stage amplifier by using larger GFET (600 um).

This became to be very rewarded in return, with +10 dBm input, this frequency

doubler could achieve +17 dBm output, which is way over the requirement and

failed the specifications. At the same time, the current in the design became very

large, such as in the output stage amplifier, and bias current Ids=110 mA.. As the

result, I should compromise with the gain performance, since the overall

requirement is not hard to achieve.


4

2 SCHEMATIC DIAGRAMS

2.1.1 180 Degree Hybrid Schematic

tqtrx_mrindL1

s=5 umw=5 uml2=179 uml1=300 umn=6

VARVAR1

cap=2.01ind=231

EqnVar

tqtrx_capC2c=cap pF

tqtrx_capC1c=cap pF

tqtrx_capC6c=cap pF

tqtrx_capC5c=2*cap pF

tqtrx_capC4c=2*cap pF

tqtrx_capC3c=cap pF

tqtrx_mrindL4

s=5 umw=5 uml2=ind uml1=ind umn=6.5

tqtrx_mrindL6


tqtrx_mrindL5


TermTerm1

Z=50 OhmNum=1

TermTerm3

Z=50 OhmNum=3

TermTerm2

Z=50 OhmNum=2

tqtrx_reswR1



4

2.1.2 Class AB Amplifier Schematic

vin

vout

CC4C=20 pF

CC1C=20 pF

tqtrx_ghsaQ2

Ng=2W=40 um

TermTerm2

Z=50 OhmNum=2

V_DCSRC1Vdc=5 V

CC3C=12 pF

V_DCSRC2Vdc=-2 V

RR1R=200 Ohm

P_1TonePORT1

Freq=1.12 GHzP=dbmtow(5)Z=50 OhmNum=1

tqtrx_ghsaQ1

Ng=6W=100 um

m1freq=2.240GHzdBm(vout)=1.403


1 2 3 4 50 6

-20

-10

0

-30

10

freq, GHz

dBm

(vou

t)

m1


4

the class AB shows very good second order harmonic frequency output, at the

same time, the higher order harmonics still have at least 30 dBc compression

compare to the fundamental frequency.

2.1.3 Output Stage Amplifier Schematic

voutvin

tqtrx_ghsaQ2

Ng=6W=65 um

tqtrx_ghsaQ3

Ng=6W=100 um

TermTerm2

Z=50 OhmNum=2

CC4C=20 pF

P_1TonePORT1

Freq=2.24 GHzP=polar(dbmtow(-10),0)Z=50 OhmNum=1

CC3C=3.3 pF tqtrx_mrind

L1

s=5 umw=5 uml2=275 uml1=275 umn=2.5

tqtrx_reswR1


CC1C=20 pF

V_DCSRC1Vdc=5.0 V

V_DCSRC2Vdc=-0.6 V

the 600 um (100 x 6) GFET with the active 390 um (65 x 6) GFET load, which

providing 109 mA Ids to have the output stage working as a linear class A

amplifier. Note that there is a stabilized 600 ohm shunt resister on the input side,

and the OMN here is not to optimize output power performance, but just to

achieve better output VSWR.


4

3 MODELED PERFORMANCE

3.1 Specification Compliance Matrix

The compliance matrix summarizes all the design parameters and requirements of

the frequency doubler.

Specification Simulation Result

Input Frequency 1070 – 1170 MHz

Output Frequency 2140 – 2340 MHz

Conversion Loss 3 dB max., 0 dB goal

Input Power +10 dBm

Spurious –

Fundamental 16 dBc min., 25 dBc goal

Spurious – Third 20 dBc min., 30 dBc goal

VSWR (50Ω) 2.5:1 max., 1.5:1 goal

Supply Voltage ± 5 Volts, goal: +5 V only

Size 60 x 60 mil Anachip


4

3.2 Predicted Performance

3.2.1 180 Degree Hybrid Performance

m1freq=1.120GHzdB(S(2,1))=-5.091

m2freq=1.120GHzdB(S(3,1))=-5.111

m1freq=1.120GHzdB(S(2,1))=-5.091

m2freq=1.120GHzdB(S(3,1))=-5.111

0.5 1.0 1.5 2.0 2.50.0 3.0

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB(S

(2,1

))

m1

dB(S

(3,1

))

m2


4

using the smaller width and line spacing inductors turns out to have more

resistance and therefore, the output of the hybrid becomes more lossy. The

phase difference is also off by 2 degree.

m3freq=1.120GHzphase(S(2,1))=-91.333m4freq=1.120GHzphase(S(3,1))=91.888

m3freq=1.120GHzphase(S(2,1))=-91.333m4freq=1.120GHzphase(S(3,1))=91.888

0.5 1.0 1.5 2.0 2.50.0 3.0

-100

0

100

-200

200

freq, GHz

phas

e(S

(2,1

))

m3

phas

e(S

(3,1

))

m4

3.2.2 Class AB Amplifier Performance


4

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60.0 1.8

-1.0

-0.5

0.0

0.5

-1.5

1.0

time, nsec

ts(v

in),

Vts

(vou

t), V

1 2 3 4 50 6

-20

-10

0

-30

10

freq, GHz

dBm

(vou

t)

Connect the 180 degree hybrid and the two class AB amplifiers: v90 and v270

are the outputs from two branches.

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60.0 1.8

-1.5

-1.0

-0.5

0.0

0.5

-2.0

1.0

time, nsec

ts(v

90),

Vts

(v27

0), V

ts(v

in),

V

1 2 3 4 50 6

-60

-40

-20

0

-80

20

freq, GHz

dBm

(vin

)

1 2 3 4 50 6

-20

-10

0

10

-30

20

freq, GHz

dBm

(v90

)

1 2 3 4 50 6

-20

-10

0

10

-30

20

freq, GHz

dBm

(v27

0)


4


m2freq=1.120GHzdBm(vout)=-7.400



1 2 3 4 50 6

-30

-20

-10

0

-40

10

freq, GHz

dBm

(vou

t)

m1

m2

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.60.0 1.8

-0.5

0.0

0.5

1.0

-1.0

1.5

time, nsec

ts(v

out),

Vts

(vin

), V

Combine the outputs of the two class AB amplifiers, all odd-ordered harmonics

should be canceled, however, in out design and simulation, due to the slight

mismatch of the two outcomes, there will be some considerable amount of the

fundamental frequency that will feed into the output stage amplifier.

3.2.3 Output Stage Amplifier Performance


4

m1freq=2.240GHzS(2,2)=0.066 / -149.932impedance = 44.487 - j2.965

m1freq=2.240GHzS(2,2)=0.066 / -149.932impedance = 44.487 - j2.965

f req (400.0MHz to 3.000GHz)

S(2

,2) m1

S(1

,1)

m3RF_pw r=10.000dBm(vout[::,1])=18.916

m3RF_pw r=10.000dBm(vout[::,1])=18.916

-30 -20 -10 0 10-40 20

-30

-20

-10

0

10

-40

20

RF_pwr

dBm

(vou

t[::

,1])

m3

m2RF_pw r=10.000dB_gain=8.916

m2RF_pw r=10.000dB_gain=8.916

-30 -20 -10 0 10-40 20

0

5

10

-5

15

RF_pwr

dB_g

ain

m2

the output stage has very good output VSWR and the input P1dB is at 10 dBm,

and can handle the power up to 18.9 dBm.


4

3.2.4 The Frequency Doubler


4


4







1 2 3 4 50 6

-5

0

5

10

15

-10

20

freq, GHz

dBm

(vou

t)

m1

m2m3


4

4 DC ANALYSIS

4.1 Class AB Amplifier

-2 V

0 Vvout0 V

vin -2.00 V-2.00 V -2.00 V

4.73 V

4.73 V

4.73 V

4.73 V

4.73 V

5 VV_DCSRC1Vdc=5 V

-9.44 mA

P_1TonePORT1

Freq=1.12 GHzP=polar(dbmtow (5),0)Z=50 OhmNum=1

0 A

tqtrx_capC2c=20 pF

0 A

tqtrx_reswR1

type=NiCrw =10 umR=200 Ohm

19.3 uA

V_DCSRC2Vdc=-2.0 V

19.3 uA

tqtrx_ghsaQ1

Ng=6W=100 um

9.44 mA

-9.42 mA

-19.3 uA

tqtrx_capC1c=20 pF

0 A

TermTerm2

Z=50 OhmNum=2

0 A

tqtrx_ghsaQ2

Ng=2W=40 um

9.44 mA 9.44 mA

-9.44 mA

the 600 um GFET is biased under Ids=9.44 mA, Vgs=-2V

4.2 Output Stage Amplifier

-596 mV-596 mV -596 mV

0 V

0 V 0 V

0 Vvout

4.09 V

4.09 V

4.09 V

4.09 V

4.09 V

5 V

0 Vvin

tqtrx_reswR1


6.37 uA

V_DCSRC2Vdc=-0.6 V

6.37 uA

V_DCSRC1Vdc=5.0 V

-110 mA

tqtrx_ghsaQ2

Ng=6W=65 um

110 mA

110 mA

-110 mA

CC4C=20 pF

0 A

TermTerm2

Z=50 OhmNum=2

0 A

tqtrx_mrindL1

s=5 umw=5 uml2=152 uml1=152 umn=5.5

0 A

tqtrx_capC5c=3.3 pF

0 A

P_1TonePORT1

Freq=2.24 GHzP=dbmtow(RF_pwr)Z=50 OhmNum=1

0 A

CC1C=20 pF

0 Atqtrx_ghsaQ3

Ng=6W=100 um

110 mA

-110 mA

-6.37 uA


4

the 600 um GFET is biased at Ids=110 mA, and Vgs=-0.6 V.

5 TEST PLAN

This section of report outlines the test plan and setup configuration to evaluate

the fabricated chipset.

5.1 Test Equipment

Test Equipment

Wafer probe station 1

RF signal generator 1

Spectrum analyzer 1

Network Analyzer 1

DC power supply 1

Digital multi meter 1

5.2 Test Setup

PowerSupply

-5 +5GND

SpectrumAnaly zer

RFGPIB

NetworkAnaly zer

GPIB

Port 1 Port 2

Generator

REFGPIB

RF

DUT

outputinput


4

5.3 Test Procedures

1. Mount the DUT chip on the probe station, apply DC voltage ( ± 5V).

2. Input +10 dBm signal, frequency 1070 MHz, 1120 MHz, and 1170 MHz

(B, M, T), measure the output power with spectrum analyzer, read and

record the values at 2140 MHz, 2240 MHz, and 2340 MHz, respectively.

3. Input +10 dBm signal, frequency 1120 MHz, measure the output power

with spectrum analyzer, read and record the values at 1120 MHz, 2240

MHz, and 3360 MHz, respectively.

4. Using network analyzer, measure the input VSWR/ input return loss.

5. Refer to section 3.1 for test specifications.

6 CONCLUSION AND RECOMMENDATION

The choice of using the balanced design with 180 degree hybrid turned out to

simplified the circuitry a lot. However, the hybrid itself would take as much as

space as the filter stage would take.

More improvement could be done easily done, due to time constraint, I could

only work on the design after the submit ion of the report:

1. I’ve over estimated the effect of the lossy hybrid. The class AB amplifier

and the output stage could be redesigned, to reduce the operation current

and at the same time, meet the gain requirement.

2. The DC bias circuitry could be redesigned and achieve the goal of using

only one DC supply.


4

3. The input VSWR could be tuned to have better performance.

4. The spurious performance can be optimized by tuning the two output

branches of our design.

Course No Course Name Page

525.787.91 Monolithic Microwave Integrated Circuit Design 1(23) Prepared By Email Phone ID Date

Mark F. Petty [email protected] 410-647-6793 12/08/02 Instructors Email Phone T.A Final Project

Craig Moore John Penn

[email protected] [email protected]

443-778-5920 443-778-6814

Nathan Richardson [email protected]

1.12 GHz VCO

An Initial Swing at Controlled Instability

An L - Band VCO

Center Frequency = 1120 MHz

Bandwidth = 100 MHz

A Student Project Designed By Mark F. Petty

For

The Johns Hopkins University – Applied Physics Laboratory Class # 525.787 - Monolithic Microwave Integrated Circuit Design

Instructors:


Fall 2002






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1.12 GHz VCO

ABSTRACT:

This paper describes an L-Band voltage controlled oscillator, VCO, designed for a student’s semester final project for the Johns Hopkins University, Monolithic Microwave Integrated Circuit, MMIC, class # 525.787. This VCO is one of several student designs used to form a “Wireless Communications Service”, WCS, system or an “Industrial, Scientific and Medical”, ISM, system. The computer aided design, CAD, tools used for this project include Agilent’s Advanced Design System, ADS, version 1.5, and MathWork’s Student Edition of Matlab release 12. The VCO’s target of fabrication is TriQuint Semiconductor’s Texas 0.6 µm Gallium Arsenide fab. TriQuint provided the device library used to describe the circuit elements within the VCO. The VCO requirements include: a center frequency of 1170 MHz; a tuning range of +/- 50 MHz; minimum output power of +10dBm, desired output power of +13dBm; supply voltage of +/- 5 volts, desired supply voltage of + 5 volts only; frequency tuning voltage of 0 – 5 volts; output impedance of 50 ohms, nominal; sized to fit on the 60 x 60 mil TriQuint ANACHIP. INTRODUCTION: Sustained oscillation results from, in short, an unstable amplifier. Since the amplifier circuit is a basic building block of electrical circuitry, much work has been performed to predict and prevent the instability of amplifiers. Pozar [1] discusses the derivation of stability circles for the input and output ports of networks, and the “K and ∆” stability parameters. The S-Parameter derived K and ∆ stability parameters are further messaged into centers and radii for source and load stability circles, which are then plotted on Smith Charts. Edwards [2] developed the µ, and µ’, stability parameters which allowed for the direct comparison of the stability in designs. Figure 1 illustrates the common problem of amplifier design, the last piece of the design, the output matching network, OMN, yields a reflection coefficient in the unstable region.

50 Ω IMN

OMN

50 Ω

ΓS

ΓIN

ΓOUT

ΓL

VS

by conjugation

Figure 1. Illustration of the stability problem in designing an amplifier. Tick marks designate stableside of stability circles. Redrawn from Edwards [3].






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1.12 GHz VCO

So, to design an oscillator, simply design an amplifier with an input and/or output reflection coefficient in their corresponding unstable region. Unfortunately it is not that easy. Remember, the above example was designed from the start to yield a stable amplifier, and it resulted in a possible oscillator. Yet, that is still the core of oscillator design methodology, find an unstable amplifier and don’t stabilize it with input and output matching networks. At the core of an oscillator there is an amplifier, and at the core of an amplifier there is an active device. The TriQuint Texas GaAs fabrication process yields three versions of MESFETs, to choose as the active device. A GFET was chosen because the negative gate to source voltage, VGS, allows for easily biasing the transistor with a single power source. The GFET was sized at 600 µm wide to ensure that enough current flow was available to meet the power output spec. A common source amplifier design was chosen for its straightforward simplicity. A MESFET with one terminal grounded reduces to a two-port device. The frequency response of a two-port device, or network is described by its two-port S-Parameters. Two port S-Parameters are readily available from the device manufacturer for many packaged parts or quickly computed by the ADS software for transistors designed as part of a MMIC chip. Multiple S-Parameter described devices, or networks, can be connected and the combined S-Parameters calculated to accurately describe the frequency response of the resultant network. The resultant network for this VCO consists of a resonance generator, and two-port amplifier, and a load, as shown in figure 2.

Figure 2. Loaded two-port network connect to generator.

bG aL

a1

b1 b2

a2

Generator Two-Port Load

ΓG Γ1 Γ2 ΓL

The S-Parameter conditions needed for oscillations are, 1,1,1 2211 =′⋅Γ=′⋅Γ< SSk LG ,

Vendelin [4]. Where 211222112112

2222

211 ,2

1SSSS

SSSS

k ⋅−⋅=∆⋅⋅

∆+−−= . And

1

1111 a

bS =′=Γ .

There are two solutions where the product of two variables equals one. A – Both variables equal one. B – Each variable is the multiplicative inverse of the other. Which means one of these two reflection coefficients, ΓG or Γ1 is greater than one. A reflection coefficient greater than one results from an input impedance with negative resistance. The generator for the VCO contains only passive components, which yield a ΓG < 1. Therefore, Γ1 > 1 or, the input impedance of the two-port amplifier must contain a negative resistance. To begin the design of an oscillator, first meet the condition of negative impedance for the two-port amplifier. Next, design a resonance circuit with an output reflection equal to the input reflection of the two-port amplifier. Third, design an output-matching network to maximize power transfer to the load.






443-778-5920 443-778-6814


1.12 GHz VCO

Inside the two-port amplifier box resides a common-source connected mesfet amplifier. DC power is applied through a parallel L-C resonator to the mesfet’s drain. The resonant frequency of the L-C tank equals the target frequency of the VCO, 1.12 GHz. The TriQuint GaAs process yields devices with good inherent stability. So, add a 10 Ω source resistor to aide in the design of an unstable amp. The shunt source capacitor increases the negative resistance of the circuit, while also increasing the effective capacitance looking into the gate of the transistor, Rhea [5]. The source resistor value also sets the DC operating condition VGS = -0.6 V, since the gate is grounded. The circuit contains approximately 60 mAmps of current flow through the device. A parallel L-C resonance tank serves as the oscillation signal generator. The shunt inductor of the parallel resonator doubles as the DC bias ground for the mesfet’s gate. The resonator’s variable capacitance is constructed with two 100 x 12 µm drain to source shorted mesfet varactors. The tuning voltage connects to the circuit at the drain-source common node between the two mesfets. The gate of one mesfet is grounded and the second gate connects to the inductor and amplifier. The tuning voltage biases both varactor mesfets because both gates are DC connected to ground, one gate is directly grounded and the second gate is grounded through the inductor. As figure 3 shows, include the emitter, feedback, and amplifier input capacitances and the amplifier input inductance to accurately calculate the resonant frequency, f0. Assumed varactor capacitance of 0.55 pF at bias voltage, Vb = 0 V, 0.4 pF at Vb = 1 V, and 0.3 pF at Vb = 2 V. Varactor characterization performed on 300 µm GFET, Penn [6], scale accordingly.

( )LCf

π21

0 = ( ) Hzf 91290 10059.1

1051.210921 ×=

×⋅×=

−−π

Lg

Rg

Cgs

Rin

Rs

Ls

RS CS

Cf

30 pf Ct

Rt

Cv2

Cv1

L 2 kΩ

2.2 pf

9 nH

1.25 pf

20 pf

20.68 pH

0.88 pf

2.2 pf

10 Ω

1.1 pH

9 nH L Ceq 2.51 pF

0.4 Ω

0.93 Ω

1.21 Ω

Figure 3. TriQuint linear GaAs MESFET model incorporated into the L-C resonance calculation.

Design the output-matching network with S11 equal, or as close as possible, to the conjugate of S22 of

the two-port amplifier, for maximum power transfer to the load. Some matching sacrifice may need to be made here due to the practicality of device sizes.






443-778-5920 443-778-6814


1.12 GHz VCO

MODELED PERFORMANCE:

Specifications Compliance Matrix for L-Band Voltage Controlled Oscillator

Specification Pre-Layout Post-Layout Fabbed IC Frequency Range 1070 to 1170 MHz 1056 to 1171 MHz 1012 to 1056 MHz Output Power > +10 dBm

> +13 dBm goal ~ +19 dBm ~ +19 dBm

Control Voltage 0 to 5 Volts 0 to 2 Volts 0 to 0.5 Volts Supply Voltage ± 5 Volts

+ 5 Volts only goal Single +5 Volt Supply

Single +5 Volt Supply

Output Impedance

50 Ω, nominal 50 Ω, nominal 50 Ω, nominal

Size 60x60 mil ANACHIP Fits Fits

Design performance is questionable. Although the pre-layout design meets specs and the goals, the post-layout design fails to meet the specs. The predicted frequency shifts down, out of the specified range. And, the application of tuning voltage greater than approximately 0.5 volts causes the oscillator to fail.

SCHEMATIC DIAGRAMS:

List of the appended schematics and simulations: Biased MESFET Schematic Resonant Tank Input Matching Network Schematic Input Matching Network’s S22 overlaid in the Biased MESFET Source Stability Circles Output Matching Network Schematic Output Matching Network’s S11 conjugate match with the S22 of the Biased MESFET Biased MESFET Instability Simulations IMN and Biased MESFET Schematic IMN and Biased MESFET Start-Up Transient Simulation IMN, Biased MESFET, & OMN Schematic IMN, Biased MESFET, & OMN Start-Up Transient Simulation IMN, Biased MESFET, & OMN Harmonic Balance Pre-Layout Schematic IMN, Biased MESFET, & OMN Harmonic Balance Pre-Layout Simulation IMN, Biased MESFET, & OMN Harmonic Balance Post-Layout Schematic IMN, Biased MESFET, & OMN Harmonic Balance Post-Layout Simulation VCO Layout within 60x60 mil ANACHIP Simplified DC Schematic Annotated with DC Bias Values DC Analysis: DC analysis shows that the source resistor is too thin to carry the ~ 60 mAmps of current. The 10-Ω NiCr resistor needs a width greater than 60 mm. New layout required prior to fabrication.






443-778-5920 443-778-6814


1.12 GHz VCO

TEST PLAN: Apply tuning voltage, to “VTUNE” labeled pad on IC, equal to zero volt first, to discharge the varactor connected mesfets. Next connect the +5 volt supply to “VDD” labeled pad. Connect spectrum analyzer to pad labeled “VOUT”. Compare DC current to predicted current value from the DC analysis above. Compare oscillator output frequency and power with values predicted by Harmonic Balance simulations above. CONCLUSION & RECOMMENDATIONS: With its undersized source resistor this design should NOT be fabricated. If everything else simulated properly after layout it still would not hurt to clean up the layout a little more. The ground- signal-ground probe pads for the VTUNE input are unnecessary because VTUNE is a DC bias voltage. The VDD input trace has an unneeded section between the bend and the input cap. And the ground connection under the varactor mesfet should also be straight. Countless hours were spent trying to understand and bring together the methodologies of several authors’ texts, more than those referenced. The confusion acquired by reading several texts simultaneously, then achieving ADS simulation results in disagreement with that author’s predictions can be summarized by the following passage.

“Although the negative resistance analysis characterizes the conditions leading to oscillation and predicts the oscillation frequency accurately, the author’s experience is that relating the results of the analysis to the noise performance of the oscillator is unreliable. This is a controversial position to take because of the existence of a paper by K. Kurokawa which contains a rigorous analysis of the noise performance of the negative resistance oscillator…” Rhea [7]

Even “experts” still disagree about microwave design.

My goal was to complete a design on a topic that was not discussed in class for the specific reason of testing myself. Unfortunately, I fell short of that goal. Too much time was lost with a too complicated initial design. Because it simulated successfully sometimes while I attempted to dial in the frequency I ignored the overall fragility of the design. I still don’t understand what broke the design when it was transferred from circuit without interconnects to one with interconnects. What parasitic components crippled my design? I hope that the Dorsey Center will be available between semesters so I may have the opportunity to build a better oscillator.

ACKNOWLEDGEMENTS: With corporations demanding experience workers at all levels, and that new hires be productive

immediately upon starting employment. Realistic design oriented courses offered at colleges and universities are the only manner for someone to change their technical career track. It is with sincere gratitude that I thank all those involved in making the Monolithic Microwave Integrated Circuit design course at Johns Hopkins University a reality. My thanks go to instructors Craig Moore and John Penn. To the Agilent Corporation for providing the ADS simulation software. To TriQuint Semiconductor Corporation for providing the GaAs process library and agreeing the fabrication student designs. And to Gray Wray for supporting the ADS tool for a bunch of whining students.






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1.12 GHz VCO

REFERENCES:

1. D. M. Pozar, Microwave Engineering, New York, NY: John Wiley & Sons, 1998, pp. 612-616. 2. M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability using a single

geometrically derived parameter,” IEEE Trans. Microwave Theory Tech., vol. 40, no. 12, pp. 2303-2311, Dec. 1992.

3. M. L. Edwards, S. Cheng, and J. H. Sinsky, “A Deterministic Approach for Designing Conditionally Stable Amplifiers,” IEEE Trans. Microwave Theory Tech., vol. 43, no. 7, pp. 1567-1575, July 1995.

4. G. D. Vendelin, Design of Amplifiers and Oscillators by the S-Parameter Method, New York, NY: John Wiley & Sons, 1982, pp. 132.

5. R. W. Rhea, Oscillator Design and Computer Simulation, Atlanta, GA, Noble, 1990, pp. 67. 6. J. Penn and C. Moore, “Notes for Lecture #4, TriQuint Process Active MMIC Circuit Elements,”

Johns Hopkins University course 525.787.91, pp. 70, Fall 2002. 7. R. W. Rhea, Oscillator Design and Computer Simulation, Atlanta, GA, Noble, 1990, pp. 66.






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1.12 GHz VCO

fall 2002 jhu ee787 mmic design student project results...

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