fee2006 - perugia. a. rivetti a fast large dynamic range shaping amplifier for particle detector...
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![Page 1: FEE2006 - Perugia. A. Rivetti A FAST LARGE DYNAMIC RANGE SHAPING AMPLIFIER FOR PARTICLE DETECTOR FRONT-END A.Rivetti – P Delaurenti INFN – Sezione di Torino](https://reader035.vdocument.in/reader035/viewer/2022062516/56649d835503460f94a697c4/html5/thumbnails/1.jpg)
FEE2006 - Perugia. A. Rivetti
A FAST LARGE DYNAMIC RANGE SHAPING AMPLIFIER FOR PARTICLE
DETECTOR FRONT-END A. Rivetti – P Delaurenti INFN – Sezione di Torino
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FEE2006 - Perugia. A. Rivetti
Project framework
Development of a fast binary read-out chip for Compass at CERN
Chip designed to replace an older ASIC (MAD4) in the RICH upgrade
User requirements:
Preserve the compatibility with the existing read-out
Reduced gain for MPT read-out
Threshold adjustable channel by channel
Hit rate > 5 MHz
Power consumption < 30 mW/channel
From 0.8 um BiCMOS to 0.35 um CMOS
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FEE2006 - Perugia. A. Rivetti
ASIC overview
FE
DACb0
b7
One shot LVDSin
out +
out -
FE
DACb0
b7
One shot LVDSin
out +
out -
FE
DACb0
b7
One shot LVDSin
out +
out -
FE
DACb0
b7
One shot LVDSin
out +
out -
FE
DACb0
b7
One shot LVDSin
out +
out -
FE
DACb0
b7
One shot LVDSin
out +
out -
Variable gain front-end Fast comparator 8 bit DAC Programmable one shot LVDS driver LDO
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FEE2006 - Perugia. A. Rivetti
Front-end building blocks
PreampOTA
BLHVref_blh
-
+Vref_OTA
inVout
PreampOTA
BLHVref_blh
-
+Vref_OTA
inVout
Variable gain preampRail-to-rail output shaperContinuous-time baseline restorer
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FEE2006 - Perugia. A. Rivetti
A typical core amplifier
Commonly used in preamp and shapersSource follower has limited swing Asymmetrical slew-rate
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FEE2006 - Perugia. A. Rivetti
Example of slew-rate requirements
Vout (V)
dt
Fast shaping time require slew rates of the order of 100 V/s.
Example: 2.5 V @ 10 ns peaking time requires 400 V/s.
Particularly critical if off-chip loads have to be driven.
In class A, for 10pF 4mA of bias current0 210 -8 410 -8 610 -8 810 -8 110 -7
0.5
1
1.5
2
2.5
3
0 2 1́0-8 4 1́0-8 6 1́0-8 8 1́0-8 1 1́0-7
-4 1́08
-3 1́08
-2 1́08
-1 1́08
0
1 1́08
dV (V/sec)
time (s)
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FEE2006 - Perugia. A. Rivetti
Better output stages
Vout
Vin
Vbias
Zero Vt devices!
Very simple Class AB Requires special devices No rail-to-rail (Vds,sat+VTH)
Rail-to-rail More complex class AB control No special devices rail-to-rail (2Vds,sat)
Vout
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FEE2006 - Perugia. A. Rivetti
Class AB control circuit
D. M. Montecelli, IEEE JSSC, Vol. SC-21, Dec. 1986Hogervost et al., IEEE JSSC Vol. 29, No. 12, Dec. 1994.
Vout
Vin1
Vin2
IB/2 IB
IBIB/2
Minimum current 0.3 Iq Maximum current >> Iq
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FEE2006 - Perugia. A. Rivetti
Complete op-amp
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FEE2006 - Perugia. A. Rivetti
Simulated slew-rate performance
Output pulse with 10pF load (blue curve) and 100pF output load
time (s)
Out
put v
olta
ge (
Vol
t)
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FEE2006 - Perugia. A. Rivetti
Pulse shape tuning
Out
put v
olta
ge (
Vol
t)
time (s)
Output pulse with 10pF load and reduced compensating capacitors
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FEE2006 - Perugia. A. Rivetti
Critical components
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FEE2006 - Perugia. A. Rivetti
From the literature (1)
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FEE2006 - Perugia. A. Rivetti
From the literature (2)
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FEE2006 - Perugia. A. Rivetti
BLH block diagram
-
+Vref_OTA
Vout
Vref_BLR
From preamp
-
+ Closed loop bufferwith slew rate limitation
Gm stage
Class AB OTA
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FEE2006 - Perugia. A. Rivetti
Behavioral simulation
Optimization driven by an analytical model of the full chain in Mathematica
SR limitation modelled in the time domain
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FEE2006 - Perugia. A. Rivetti
Full circuit model
Analytical model of the full chain to simulate accurately baseline shifts
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FEE2006 - Perugia. A. Rivetti
Baseline drift with Gm-stage only
Analytical model
Baseline drift smaller owing to SR limitation in the Gm-stage (not modelled)
Spice simulation
Simulation with random arrival time
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FEE2006 - Perugia. A. Rivetti
Effect of the buffer
With SR-limited buffer-Spice
Analytical model with SR-limitedBuffer (zoom around baseline)
Without SR-limited buffer-Spice
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FEE2006 - Perugia. A. Rivetti
Gm-stage schematic
Vbias
Vin 1 Vin 2Iout
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FEE2006 - Perugia. A. Rivetti
SR-limited buffer schematic
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FEE2006 - Perugia. A. Rivetti
BLR layout
400 m
200 m
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FEE2006 - Perugia. A. Rivetti
First prototype results
Linearity
Peaking time
ENC 1450 e-@10pF
Credits due to Michela Chiossofor the tests of the chip!
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FEE2006 - Perugia. A. Rivetti
Exploring the critical region
0 fC 900 fC
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FEE2006 - Perugia. A. Rivetti
“Curiosity driven” simulations in 0.13 m
Same class AB topology scaled down to 0.13 m and powered at 1.2 V
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FEE2006 - Perugia. A. Rivetti
Pulse shape with 10 pF and 100 pF loads
10 ns
810 mV
12 ns
895 mV
10 pF output load 100 pF output load
VBLH
inVout
R2
R1
Csh R2/R1=4 Csh=240 fF power = 800 W
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FEE2006 - Perugia. A. Rivetti
Linearity in 0.13 m
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FEE2006 - Perugia. A. Rivetti
Low voltage class AB control
Vout Vin 1
Vin 2
K. J. de Langen, J. H. Huijsing. IEEE JSSC, Vol. 33, No. 10, Oct. 1998.