file number here cpld competition. file number here session objectives review strengths &...
TRANSCRIPT
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CPLD Competition
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Session Objectives
Review Strengths & Weaknesses of key competitors:— Lattice— Vantis— Altera
Highlights areas to attack and win
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Competitor Profile: Vantis (AMD)
Old AMD PLD division— now a separate fabless company— dependent on AMD fabs (+ UMC for FPGA in ‘98)— SPLDs and CPLDs now; announced new ‘VF1’ FPGA line
Minimal software, customer service functions— management focused only on components, not solutions— relies on AMD for process development
Dropped down to 4rd largest PLD company— fell from 3rd in ‘97 behind Lattice— dependent on declining SPLD sales
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Vantis Thrust Products
Mach 4LV: 3.3V Low & Mid density ISP— 32 to 256 macrocells— speeds to 7.5ns (slower than 5V devices)— good JTAG support
Mach 5LV: 3.3V High-density ISP— 128 to 512 macrocells— raw speeds to 7.5ns, but only specific input-output paths— good JTAG support
Other products— 5V versions of Mach4, Mach5— Mach 1,2,3: Low density, some with ISP retrofit
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Vantis Weaknesses (Present)
Clumsy Software— clumsy software developed by 3rd party (MINC)— re-starting in-house SW group (little effect in short term)— poor support for Mach5/LV
High prices due to high cost structure— “0.35um” process has 0.5um feature size
Mach5/LV difficult to achieve speed/utilization— path-dependent delays— block-localized features cause routing difficulties
– power reduction, output enables
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Vantis Weaknesses (Future)
Concern over future plans— will business be sold (and obsoleted)?— reference: Intel PLDs sold to Altera and
obsoleted
Reduced CPLD focus— resources consumed by FPGA launch— slow cost migration, product improvements,
software improvements
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Vantis Attack Points
Attack the software— what is the software roadmap ?
Attack device volume availability— enough priority/capacity from AMD fabs?
Attack Mach5/LV architectural limitations— block-localized power reduction, OEs restricts fitting and
routability— complex 3-tier routing structure, path-dependent timing
Attack technical support— call Vantis, Minc, or ? for routing issues
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Competitor Profile: Lattice
1st with ISP CPLD, but an incomplete solution— pin-locking issues — old fashioned architecture— Non-standard ISP interface (proprietary non-JTAG)
Biggest supplier of ISP CPLDs— several different but similar CPLD families— 1997 CPLD market share is about 20%
Reputation for inadequate software solution
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Lattice Thrust Products ispLSI2000V:
— 3.3v ISP (de-rated 5V parts)— 2032V offers no power savings over same speed 5V 2032— latch-up risk in mixed 3.3V/5V systems— higher cost, slower speed grades than 5V versions
ispLSI1000E/2000— 32 to 192 macrocells— improved routing, but not enough
Other products:— ispLSI3000: large & difficult-to-use (192 to 320 macrocells)— ispLSI6000: 192 macrocells + 4.6 Kbit RAM
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Lattice Weaknesses (Present)
Software performance— hampered by the restrictive silicon architecture— ease of use issues— pin-locking issues — poor routing at high utilization
Restrictive, 6-year old architecture— limited product-term allocation options— no individual output enables (OE)— block-localized clock signals
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Lattice Weaknesses (Future)
Proprietary, non-standard ISP interface (ispLSI1K/2K)— difficult board integration with JTAG components
Limited to CPLD devices only— against industry trend toward a single logic vendor
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Lattice Attack Points
Attack 3.3V IC deficiencies:— latch-up risk (requires significant design effort to compensate)— no or minimal power savings over 5V— slower, higher price
Attack software capability— why can’t use more than 80% device utilization?
Attack EEPROM process roadmap— what is the long-term process migration path?
Lack of JTAG on lead products (ispLSI 1K/2K)
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Competitor Profile: Altera
Largest supplier of CPLDs— note: Flex 8K and 10K are not CPLDs
Company focused on IC/software technology— not focused on solutions or customer support
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Altera Thrust Products Max7000A
— 3.3V ISP— no enhancements over 7000S, only fixes
Max7000S— old Max7000(E), but with ISP— 32 to 256 macrocells
Flex10K— really an FPGA, not “CPLD”
Other products:— Max9000: 300 to 560 macrocells, with ISP— Flex 8K: FPGAs called “CPLDs”
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Altera Weaknesses (Present)
Pin-locking is well-known issue— especially > 100 macrocells— EEPROM-based sparse routing matrix— “2nd time fitting” is not pin-locking
– Altera measures software ability to refit the same design to locked pins– veteran Max7K users burnt by pin-locking problem
7-year-old basic architecture— less flexible vs. XC9500 in product-term allocation— no individual (p-term) output enables— only 2 global clocks
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Altera Weaknesses (Future)
Proprietary EEPROM technology pushed to its limits?— persistent problems with new TSMC fab after 3+ years— slow and problem-prone roll-out of Max7000S
Market trend is for standard design language— move to VHDL erodes AHDL design wins
Architecture problems hidden by software— auto-picks bigger devices to reduce % utilization— error messages say “No” very nicely
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Altera Attack Points Attack AHDL fortress
— no design portability— convert AHDL designs to VHDL— sell Foundation with VHDL upgrade
Attack reliance on old architectures and processes— XC9500 is new technology, new benefits
Attack ISP device availability, quality— sampled defective devices to customers with charge loss problems— 3 year delay on Max7000S family rollout— only 100 program/erase cycles, 10 year data retention
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Reference Materials
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Pin-Locking Comparisons
Xilinx
XC9500
Altera
Max7KS
Lattice
1K/2K/3K
AMD
Mach5
Routability
Function block fan-in
Bi-directional individual product
term allocation
Maximum pterms/MCell
Excellent
36
Yes
90
Good*
36
No
32
Poor
18/24
No
20
Good
32
No
32
Notes: * Increasingly worse with density
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JTAG Comparison
XC9500 Benefits
USERCODE
INTEST
IDCODE
HIGHZ
Version control
JTAGInstruction Capability Altera
Max7KSXilinx
XC9500
Yes
Yes
Yes
Yes
No
No
Yes
No
Latticeisp
AMDMach5
No
No
No
No
No
No
Yes
Yes
Yes Yes* Not in1K/2K
YesExtestSample/PreloadBypass
Basic 1149.1 boundary scan
Notes: * JTAG boundary-scan is NOT available in the 7032S, 7064S, and 7096S.
In-system debug
Device type ID
Tristate pins during test
Built-in version control for pattern tracking Efficient system debugging / diagnosis
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XC9500 = Most Flexible Architecture
Altera
Max7KS
Lattice
1K/2K/3K
AMD
Mach5
Individual set, reset, clock pterms
Individual OE pterm for each pin
3.3v/5v I/O
Number of global clocks
True / complement global clocks
Global set/reset
User programmable grounds
Maximum # pterms per macrocell
Yes
Yes
Yes
3
Yes
Yes
Yes
90
Yes
No
Yes
2
Yes
Reset
No
32
No
No
No
3
1K Only
Reset
No
20
No
No
Yes
4
Yes
No
No
32
Superior pin-locking architecture Enhanced logic capability Efficient logic implementation
Leading-Edge Architecture Benefits
Xilinx
XC9500
Notes: * 7032S is the exception and does NOT provide 3.3v/5v I/O capability.
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Product ComparisonAltera
Max7KS
Lattice
1K/2K/3K
AMD
Mach5Description Macrocell range
Number of user I/O pins
Best tPD
Best fMAX
5V in-system programmable
Pin-locking
Endurance (pgm/erase cycles)
JTAG boundary-scan Number of JTAG instructions
3.3V ISP versions
36 - 288
34 - 192
5ns
125MHz
Yes
Good
10,000
Yes7
2H98
32 - 256
36 - 164
5ns
179MHz
Yes
Fair-Poor
100
7128+ only4*
2Q98
32 - 320
34 - 192
5ns
180MHz
Yes
Poor
10,000
3K only3
2000V
128 - 512
68 - 256
7.5ns
125MHz
Yes
Fair
100
Yes6
MachLV
Notes: * JTAG boundary-scan (1149.1) is NOT available in the Altera 7032S, 7064S, and 7096S.
Xilinx
9500