film deposition in vlsi

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FILM DEPOSITION FILM DEPOSITION

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Contains a full description. Read all other presentations in the "l*" series to get a full understanding of VLSI fab process.* indicates number

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Page 1: Film Deposition in VLSI

FILM DEPOSITIONFILM DEPOSITION

Page 2: Film Deposition in VLSI

Epitaxial growth

Growth of single crystal semiconductor Growth of single crystal semiconductor layer over a single crystal semiconductor layer over a single crystal semiconductor substrate.substrate.

Two types:Two types:Homoepitaxy.Homoepitaxy.Heteroepitaxy.Heteroepitaxy.

Substrate wafer acts as the seed.Substrate wafer acts as the seed. Common techniques:Common techniques:

CVDCVD MBEMBE

Page 3: Film Deposition in VLSI

CVDCVD

Chemical Vapour DepositionChemical Vapour Deposition Method: chemical reaction between Method: chemical reaction between

gaseous compounds.gaseous compounds. In cases gas sources are not available, a

carrier gas such as H2 or N2 is bubbled through the liquid that carries vapors to chamber

Also known as vapour-phase epitaxy.Also known as vapour-phase epitaxy. Two variations:Two variations:

APCVDAPCVD LPCVD.LPCVD.

Page 4: Film Deposition in VLSI

Example of CVD used in fabrication

Dielectrics: HfO2, SiO2, TiO2Gate electrode: polysiliconMetal interconnects: CopperDiffusion Barriers: TiN, TaNContact plugs: Tungsten (W)Silicides

Page 5: Film Deposition in VLSI

Steps involved in CVDSteps involved in CVD

Transportation of reactants to substrate.Transportation of reactants to substrate. Reactor adsorptionReactor adsorption Chemical reaction followed by epitaxial growth.Chemical reaction followed by epitaxial growth. Desorption of gaseous products.Desorption of gaseous products. Transportation of reaction products from reaction Transportation of reaction products from reaction

chamber.chamber.

Page 6: Film Deposition in VLSI

Analyzing CVDAnalyzing CVD Although CVD process is quite

complicated, we can analyze by just considering two important steps: Diffusion of reactants across

boundary layer (Flux J1) Reaction at surface (Flux J2)

Similar to Deal Grove (…recall oxidation!) we can analyze the process at equilibrium J1 = HG(CG – CS) where HG is the

mass transfer coefficient J2 = Ks CS where Ks is the surface

reaction rate

Page 7: Film Deposition in VLSI

In steady state, J1 = J2 If kS << hG , then we have the surface

reaction controlled case If hG << kS, then we have the mass transfer,

or gas phase diffusion, controlled case

Page 8: Film Deposition in VLSI

Silicon CVDSilicon CVD

Main sources:Main sources:Silicon tetrachlorideSilicon tetrachlorideDichlorosilaneDichlorosilaneTrichlorosilaneTrichlorosilaneSilaneSilane

Commonly uses SiClCommonly uses SiCl44high temp. process.high temp. process. Others used because of lower temperature.Others used because of lower temperature.

SiClSiCl4 4 + 2H+ 2H22 Si (solid) + 4HCl (gas) Si (solid) + 4HCl (gas)Accompanying reaction:Accompanying reaction:

SiClSiCl4 4 + Si (solid) + Si (solid) 2SiCl2SiCl2 2 (gas)(gas)

Page 9: Film Deposition in VLSI

Gallium Arsenide CVDGallium Arsenide CVD

Similar to Si CVD process.Similar to Si CVD process.Ga and As dissociates at high Ga and As dissociates at high

temperature.temperature.Use AsUse As44 and GaCl and GaCl33 for both for both

components.components.

Page 10: Film Deposition in VLSI

Metal Organic CVDMetal Organic CVD

For elements:For elements: That do not form stable hydrides and halides.That do not form stable hydrides and halides. That form stable metal-organic compounds.That form stable metal-organic compounds.

Extensively for heteroepitaxial growth.Extensively for heteroepitaxial growth. Major problems with MOCVD has been

carbon contamination and particulates which are detrimental to electrical characteristics (especially for hot-wall reactors); the hazards of the reactor gases is also significant

Page 11: Film Deposition in VLSI

MBEMBE Evaporation of Si (or any other

semiconductor) and desired dopants under very high vacuum (10-8 Torr) and low Temp (4000 - 8000C) . Predominantly used for III-V

semiconductors Atoms or molecules are directed to

heated substrate in ultra high vacuum (UHV)

By utilizing very low growth rates (≈ 1μm/hour) can tailor doping profiles and composition on a monolayer scale.

Page 12: Film Deposition in VLSI

AdvantagesLow deposition tempPrecise control of layer thickness and doping

profile (excellent uniformity)Versatile (used for fabricating heterostructures,

quantum wells, etc) In-situ cleaning and characterization

High temp. baking to decompose native oxygen.Low energy ion beam of inert gas to sputter impurity.

Disadvantage:Expensive (UHV), very slow deposition

Page 13: Film Deposition in VLSI

Lattice matched Lattice matched epitaxy: epitaxy: homoepitaxy.homoepitaxy.

Two cases of Two cases of heteroepitaxy:heteroepitaxy: Lattice matched.Lattice matched. Strained-layer.Strained-layer.

Page 14: Film Deposition in VLSI

Defects in epitaxial layersDefects in epitaxial layers

Defects from substratesDefects from substratesDefects from interface.Defects from interface.Precipitates or dislocation loops.Precipitates or dislocation loops.Misoriented areas of an epitaxial film Misoriented areas of an epitaxial film

(low angle grain boundary)(low angle grain boundary)Edge dislocationEdge dislocation

In heteroepitaxy of two lattice-mismatched In heteroepitaxy of two lattice-mismatched semiconductor.semiconductor.

Page 15: Film Deposition in VLSI

Step CoverageStep Coverage

Relates surface topography of Relates surface topography of deposited film to various steps on deposited film to various steps on substrate.substrate.Conformal step coverage (ideal)Conformal step coverage (ideal)Non-conformal step coverage.Non-conformal step coverage.

Page 16: Film Deposition in VLSI

Dielectric DepositionDielectric Deposition

APCVD, LPCVD, PECVDAPCVD, LPCVD, PECVDPECVD: plasma enhanced reaction.PECVD: plasma enhanced reaction.Energetic ion bombardment.Energetic ion bombardment.High density plasma helps to High density plasma helps to

improve electrical and mechanical improve electrical and mechanical properties.properties.

Page 17: Film Deposition in VLSI

SiOSiO22

Quality not upto that grown by thermal Quality not upto that grown by thermal oxidation.oxidation.

Insulator for multilevel metalization, Insulator for multilevel metalization, masking ion implantation and diffusion.masking ion implantation and diffusion.

Low temperature process: film is formed Low temperature process: film is formed by reacting silane, dopants and oxygen.by reacting silane, dopants and oxygen. Suitable for deposition over Al.Suitable for deposition over Al.

Intermediate temperature process: Intermediate temperature process: decomposition of TEOS.decomposition of TEOS.

At higher temperatures, deposited oxide At higher temperatures, deposited oxide film will be structurally similar to that film will be structurally similar to that grown by thermal oxidation.grown by thermal oxidation.

Page 18: Film Deposition in VLSI

SiSi33NN44

Simple thermal nitridation: slow growth Simple thermal nitridation: slow growth rate, high growth temperature.rate, high growth temperature.

Two methods for deposition:Two methods for deposition:Intermediate temperature LPCVDIntermediate temperature LPCVD

High density stoichiometric film.High density stoichiometric film.Application: device passivation, mask for Application: device passivation, mask for

selective oxidation of Si.selective oxidation of Si.Low temperature plasma assisted CVD.Low temperature plasma assisted CVD.

Lower density non-stoichiometric film.Lower density non-stoichiometric film.Application: final passivation layer.Application: final passivation layer.

Page 19: Film Deposition in VLSI

Metallization - PVDMetallization - PVD

Ti, Al, Cu, TiN, TaNTi, Al, Cu, TiN, TaNMethods:Methods:

EvaporationEvaporationE-beam evaporationE-beam evaporationPlasma spray deposition Plasma spray deposition Sputtering.Sputtering.

Evaporation:Evaporation:Source heated in an evacuated chamber.Source heated in an evacuated chamber.

Page 20: Film Deposition in VLSI

PVD - E-beam evaporationPVD - E-beam evaporation Target material is Target material is

bombarded with an electron bombarded with an electron beam given off by a charged beam given off by a charged tungsten filament under tungsten filament under high vacuum. high vacuum.

The electron beam causes The electron beam causes atoms from the target to atoms from the target to transform into the gaseous transform into the gaseous phase. phase.

They precipitate into solid They precipitate into solid form, coating everything in form, coating everything in the vacuum chamber (within the vacuum chamber (within line of sight) with a thin line of sight) with a thin layer of the anode material.layer of the anode material.

Page 21: Film Deposition in VLSI

PVD - Ion beam sputteringPVD - Ion beam sputtering Ion current and energy adjusted.Ion current and energy adjusted.Other sputtering techniques:Other sputtering techniques:

Magnetron sputteringMagnetron sputteringLong-throw sputteringLong-throw sputteringReactive sputteringReactive sputtering

Page 22: Film Deposition in VLSI

Metallization - CVDMetallization - CVD

Conformal coating.Conformal coating.High throughput.High throughput.LPCVD: conformal step coverage LPCVD: conformal step coverage

over wide range with lower electrical over wide range with lower electrical resistivity.resistivity.

Application: refractory metal Application: refractory metal deposition.deposition.

Page 23: Film Deposition in VLSI

CVD TungstenCVD Tungsten

W: as contact plug and as first-level metal.W: as contact plug and as first-level metal. Source gas: tungsten hexafluoride (WFSource gas: tungsten hexafluoride (WF66))

Can be reduced by Si, HCan be reduced by Si, H22 or SiH or SiH44

WFWF66 + 3H + 3H22 W + 6HF W + 6HF ---- rapid process, ---- rapid process, conformal conformal coverage coverage

2WF2WF66 + 3Si + 3Si 2W + 3SiF 2W + 3SiF44

2WF2WF66 + 3SiH + 3SiH44 2W + 3SiF 2W + 3SiF44 + 6H + 6H22 ---- high ---- high deposition deposition

rate, high densityrate, high density

W CVDW CVD SiH SiH44 reduction followed by H reduction followed by H22 reductionreduction

Page 24: Film Deposition in VLSI

CVD TiNCVD TiN

Diffusion barrier.Diffusion barrier.Can be deposited by sputtering and Can be deposited by sputtering and

CVD.CVD.CVD provides better step coverageCVD provides better step coverageSource : TiClSource : TiCl44

6TiCl6TiCl44 + 8NH + 8NH33 6TiN + 24HCl + N 6TiN + 24HCl + N22

2TiCl2TiCl44 + N + N2 2 + 4H+ 4H22 2TiN + 8HCl 2TiN + 8HCl

2TiCl2TiCl4 4 + 2NH+ 2NH33 + H + H22 2TiN + 8HCl 2TiN + 8HCl

Page 25: Film Deposition in VLSI

TiN-W usage

Page 26: Film Deposition in VLSI

Aluminum MetallizationAluminum Metallization

Aluminum was most popular choice till late 90’sHas low resistivity (2.7μohm-cm)Good adhesion to SiO2Simple deposition (PVD usually)Dry or Wet etch possible

Page 27: Film Deposition in VLSI

Aluminum MetallizationAluminum Metallization

Can be deposited by PVD or CVD.Can be deposited by PVD or CVD.Problems associated: Junction Problems associated: Junction

Spiking, Electro-migration, Spiking, Electro-migration, Low melting point..

Spiking due to eutectic Spiking due to eutectic characteristicscharacteristics

Spikes can short junctions or cause Spikes can short junctions or cause excess leakageexcess leakage

Page 28: Film Deposition in VLSI

Electro-migrationElectro-migration

Transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms

leads to the eventual loss of one or more connections and intermittent failure

Page 29: Film Deposition in VLSI

Copper

Advantages with Copper (Cu)Lower resistivity than Al (1.7) which leads to

reduction in delaysHigher melting point (~1080C) than AlHigher electro migration resistance than

Aluminum Disadvantages / Challenges

Highly reactive or corrosiveDifficult to etchDeposition challengesPoor adhesion to dielectricsHigh diffusivity in Si

Page 30: Film Deposition in VLSI

Solutions to problems with Cu.

Fast diffusion of Cu into Si and SiO2 Poor oxidation/corrosion resistance Poor adhesion to SiO2

Diffusion Barrier / Adhesion Promoter

Difficulty of applying conventional etching technique

Use CMP Damascene process

Page 31: Film Deposition in VLSI

Damascene Process

Pattern dielectric Deposit Cu in the

trenches CMP to remove

excess Cu.

Page 32: Film Deposition in VLSI

Dual Damascene

In this process two layers of inter-metal dielectric are deposited sequentially and after patterning and etching through two layers, Cu is deposited and this is followed by CMP

Page 33: Film Deposition in VLSI

CMP Global planarization. Surface moved against pad containing

slurry. Slurry: thick suspension of solids in liquidParticles in slurry mechanically

abrade the wafer surface and remove materials

Loosened material are either dissolved or swept away.

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