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TFE4180 Semiconductor Manufacturing TechnologyTFE4180 Semiconductor Manufacturing Technology

Film Deposition – Part 3Chapter 11 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda

Spring Semester 2014

Saroj Kumar PatraSemidonductor Manufacturing Technology,

Norwegian University of Science and Technology ( NTNU )

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TFE4180 Semiconductor Manufacturing Technology

Contents

• Plasma-Assisted CVD– Plasma Enhanced CVD (PECVD) [continuation]– High-Density Plasma CVD (HDPCVD)

• Dielectrics and performance– Dielectric constant– Device isolation

• Spin-on-dielectrics– Spin-on-glass (SOG)– Spin-on-dielectrics (SOD)

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TFE4180 Semiconductor Manufacturing Technology

S. Veprek, Thin Solid Films 130, 135 (1985).

K.-T. Rie, E. Menthe, A. Matthews, K. Legg, and J. Chin, MRS Bull. 21(8), 46 (1996).

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TFE4180 Semiconductor Manufacturing Technology

Gap fill in PECVD

The deposition/sputtering-rate ratio(D/S)

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TFE4180 Semiconductor Manufacturing Technology

HDPCVD• High density of mixture of gases at low pressure

that is directed toward the wafer surface in thereaction chamber. The temperature for highaspect ratio gaps ranges of 300 to 400 。

• Density of ions at low pressure is about 10 to 10 ions/

conventional

High density

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TFE4180 Semiconductor Manufacturing Technology

Simultaneous Deposition and Etching

• HDPCVD able to fill high aspect ratio gaps with dielectric material without voids

• deposition:etch(D:E) ratio- typically 3:1

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TFE4180 Semiconductor Manufacturing Technology

Simultaneous Deposition and Etching (cont.)

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TFE4180 Semiconductor Manufacturing Technology

Simultaneous Deposition and Etching (cont.)

HDPCVD with Wafer at Throath of Turbo Pump (Figure 11.22)

To roughing pump

Microwave 2.45 GHz

Electromagnet

Turbopump

Gate valve

Gas shower head

Wafer on electrostatic chuck

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TFE4180 Semiconductor Manufacturing TechnologyTFE4180 Semiconductor Manufacturing Technology

Simultaneous Deposition and Etching (cont.)

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TFE4180 Semiconductor Manufacturing Technology

Dielectrics and Performance: Dielectric constant

Potential low-kDielectric

DielectricConstant

(k)

Gap Fill(m)

CureTemp.(C)

Remarks

FSG (siliconoxyfluoride, SiXOFy)

3.4 – 4.1 <0.35 No issueFSG has almost the same k-value as SiO2 andreliability concern that fluorine will attack andcorrode tantalum barrier metal.

HSQ (hydrogensilsesquioxane) 2.9 <0.10 350 – 450

Silicon-based resin polymer available insolution as Fox (Flowable Oxide) for spin-oncoating application. May require surfacepassivation to reduce moisture absorption.Cure is done in nitrogen.

Nanoporous silica 1.3 – 2.5 <0.25 400

Inorganic material with tunable dielectricconstant that relies on pore density. Increasedporosity reduces mechanical integrity –porous material must withstand polishing,etching and heat treatments withoutdegradation.

Poly(arylene) ether(PAE) 2.6 – 2.8 <0.15 375 – 425 Spin-on aromatic polymer with excellent

adhesion and ability to be polished with CMP.

a-CF (fluorinatedamorphous carbon orFLAC)1

2.8 <0.18 250 – 350

Leading candidate for CVD deposition withhigh density plasma CVD (HDPCVD) toproduce film with good thermal stability andadhesion.

Parylene AF4 (aliphatictetrafluorinated poly-p-xylylene)

2.5 <0.18 420 – 450

CVD film that meets adhesion and viaresistance requirements with need to maintaingas delivery system at 200C to controlparylene precursor flow rate.

1 P. Singer, Technology News: Wafer Processing, Semiconductor International, October, 1998, p. 44.

SiO2 : k = 3,9

ACd

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TFE4180 Semiconductor Manufacturing Technology

Chip Performance2.5

2.0

1.5

1.0

0.5

00 .5 1.0 1.5 2.0

Feature size (m)

Del

ay ti

me

(10

-9se

c)

Interconnect delay (RC)

Gate delay

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TFE4180 Semiconductor Manufacturing Technology

Low-k Dielectric Film RequirementsElectrical Mechanical Thermal Chemical Processing Metallization

Low dielectricconstant Good adhesion Thermal

stabilityResistant: acids

and bases Patternability Low contactresistance

Low dielectricloss Low shrinkage

Low coefficientof thermalexpansion

Etch selectivity Good gap fillLow

electromigration(corrosion)

Low leakage Crack resistant Highconductivity Low impurities Planarization Low stress

voiding

High reliability Low stress No corrosion Low pin hole Hillock (smoothsurface)

Good hardness Low moistureuptake Low particulate

Compatible withbarrier metals (Ta,

TaN, TiN, etc.)

Storage life

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TFE4180 Semiconductor Manufacturing Technology

High-k Dielectric ConstantSiO2 dielectric

Doped polysiliconcapacitor plate

Doped polysiliconcapacitor plate

Buried contactdiffusion

SiO2 dielectric Doped polysiliconcapacitor plate

Doped polysiliconcapacitor plate

Buried contactdiffusion

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TFE4180 Semiconductor Manufacturing Technology

High-k Dielectric Constant

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TFE4180 Semiconductor Manufacturing Technology

Device Isolation

• Local Oxidation (LOCOS)• Shallow Trench Isolation (STI)

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Spin-on-Glass

2) SOG after curing1) Initial SOG gap fill

3) CVD oxide cap

Cap

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TFE4180 Semiconductor Manufacturing Technology

Spin-on-Dielectrics

Major Operation Process Step Parameter

Apply bowl speed 50 rpm

Maximum bowl speed 800 – 1500 rpm

Backside rinse 800 rpm, 5 sec

Topside edge bead removal 1000 rpm, 10 sec

Spin coating

Spin Dry 1000 rpm, 5 sec

Initial soft-bake cure 200C, 60 sec, N2 purgeCure

In-line cure 475C, 60 sec, N2 ambient

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TFE4180 Semiconductor Manufacturing Technology

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