final vlsi pract 08

Experiment No : 01

COMBINATIONAL LOGIC DESIGN USING VHDL

PROBLEM STATEMENT :

Simulation ,synthesis and implementation of the following, using VHDL :

8:1 Multiplexer. Adder Comparator Decoder

THEORY :

8:1 MULTIPLEXER

A Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to single output line. Normally, there are 2n

input lines and n selection lines, whose bit combinations determine which input is selected.

The 8:1 Mux circuit has 8 data input lines, one output and 3 selection lines. The Mux acts like an electronic switch, which selects one of the 8 input sources.Use of multiplexer offers following advantages :

Simplification of logic expression is not required. The IC package count is minimized. Logic design is simplified.

1

8:1MUX

__ __ __ S0 S0 S1 S1 S2 S2

TRUTH TABLE

COMPARATOR

A comparator is a special combinational circuit primarily to compare relative magnitude of two binary no.

Suppose two binary nos. are A and B, then it just tells whether A>B, A=B OR A<B. Depending upon relative magnitude of two no. one of the output will be high. We are comparing two bit nos. We are simplifying the comparator with the help of k map.

S1 S2 S3 Y

0 0 0 A

0 0 1 B

0 1 0 C

0 1 1 D

1 0 0 E

1 0 1 F

1 1 0 G

1 1 1 H

2

2-BitComparator

TRUTH TABLE FOR 2-BIT COMPARATOR

INPUT OUTPUTA1 A0 B1 B0 A>B A=B A<B0 0 0 0 0 1 00 0 0 1 0 0 10 0 1 0 0 0 10 0 1 1 0 0 10 1 0 0 1 0 00 1 0 1 0 1 00 1 1 0 0 0 10 1 1 1 0 0 11 0 0 0 1 0 01 0 0 1 1 0 01 0 1 0 0 1 01 0 1 1 0 0 11 1 0 0 1 0 01 1 0 1 1 0 01 1 1 0 1 0 01 1 1 1 0 1 0

HALF ADDER Digital computer performs various arithmetic operations. The most basic operation, is the addition of 2-binary digits. The simple addition consists of 4-possible elementary operation, namely: 0+0=0 0+1=1 1+0=1 1+1=0The first 3-operations produces a sum whose length is one digit, but when the last operation is performed sum is two digits. The higher & the lower significant bit called sum. The logic ckt. which performs this operation for three bits, (two significant bits & a previous carry) is called full adder.

3

Logic Diagram for Half Adder

FULL ADDER

It consists of 3-i/p’s & 2-o/p’s.Two of i/p’s variables are denoted by A & B , represents the two significant bits to be added . The third I/p Cin , represents the carry from the previous lower significant position.K – map simplification for sum & carry . __ _ _ __ Sum =ABCin + ABCin + ABCin + ABCin

Cout = AB + ACin + BCin

BLOCK SCHEMATIC AND TRUTH TABLE OF FULL ADDER

INPUTS OUTPUTSA B Cin Carry Sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

FULL ADDER

4

Sum

Carry

AB

FULLADDER

SUM

Cin

A

B

Cout

DECODER

A decoder is a combination ckt that converts binary info from i/p line to one of the 2^n o/p lines. If n bit coded information has unused combination the decoder may have less than 2^n i/p.

2:4 DECODER:

Here 2 i/ps are added and decoded into 4 o/p lines. Using select lines each o/p represents one of the min term of 2 i/p variable. The 2 inverters provide complement of i/p’s and each of the four and gate generate one of the min terms.

TRUTH TABLE

X1 X2 D3 D2 D1 D00 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0

5

2:4Decoder

CONCLUSION :

Simulation, synthesis and implementation of the following was done successfully using VHDL :

8:1 Multiplexer. Adder Comparator Decoder

2 BIT Comparator

Code

library IEEE;6

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity Compar2bit is Port ( a : in std_logic_vector(1 downto 0); b : in std_logic_vector(1 downto 0); y1 : out std_logic; y2 : out std_logic; y3 : out std_logic);end Compar2bit;

architecture Behavioral of Compar2bit isbegin

process(a,b) begin if a=b then y1<='1'; y2<='0'; y3<='0'; else if a>b then y2<='1'; y1<='0'; y3<='0'; else y3<='1'; y1<='0'; y2<='0'; end if; end if; end process;

end Behavioral;

RTL Schematic

7

Synthesis Report

8

===================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : compar2bit.ngrTop Level Output File Name : compar2bitOutput Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+

Design Statistics# IOs : 7

Cell Usage :# BELS : 3# LUT4 : 3# IO Buffers : 7# IBUF : 4# OBUF : 3===================================================================Device utilization summary:----- ----------------------

Selected Device : 2s200pq208-5

Number of Slices: 2 out of 2352 0% Number of 4 input LUTs: 3 out of 4704 0% Number of bonded IOBs: 7 out of 144 4%

===================================================================TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information:------------------No clock signals found in this design

Timing Summary:---------------Speed Grade: -5

Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found

9

Maximum combinational path delay: 9.764ns

Timing Detail:--------------All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 9.764ns (Levels of Logic = 3) Source: b<1> Destination: y3

Data Path: b<1> to y3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 3 0.924 1.480 b_1_ibuf (b_1_ibuf) LUT4:i0->o 1 0.653 1.150 _n00071 (y3_obuf) OBUF:i->o 5.557 y3_obuf (y3) ---------------------------------------- Total 9.764ns (7.134ns logic, 2.630ns route) (73.1% logic, 26.9% route)

===================================================================CPU : 6.00 / 6.75 s | Elapsed : 6.00 / 6.00 s -->

Total memory usage is 54372 kilobytes

Test Bench Report

10

-- M:\VLSI\COMPARATOR1-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE 30 JUN 12:35:59 2009-- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY ieee;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;

ENTITY testbench ISEND testbench;

ARCHITECTURE testbench_arch OF testbench IS-- If you get a compiler error on the following line,-- from the menu do Options->Configuration select VHDL 87FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT Compar2bitPORT (

a : in std_logic_vector (1 DOWNTO 0);b : in std_logic_vector (1 DOWNTO 0);y1 : out std_logic;y2 : out std_logic;y3 : out std_logic

);END COMPONENT;

SIGNAL a : std_logic_vector (1 DOWNTO 0);SIGNAL b : std_logic_vector (1 DOWNTO 0);SIGNAL y1 : std_logic;SIGNAL y2 : std_logic;SIGNAL y3 : std_logic;

BEGINUUT : Compar2bitPORT MAP (

a => a,b => b,y1 => y1,y2 => y2,y3 => y3

11

);PROCESS

VARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;

PROCEDURE CHECK_y1(next_y1 : std_logic;TX_TIME : INTEGER

) ISVARIABLE TX_STR : String(1 to 4096);VARIABLE TX_LOC : LINE;

BEGINprocess(a,b)

begin if a=b then y1<='1'; y2<='0'; y3<='0'; else if a>b then y2<='1'; y1<='0'; y3<='0'; else y3<='1'; y1<='0'; y2<='0'; end if; end if; end process;

END;



BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (y2 /= next_y2) THEN

write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns y2="));write(TX_LOC, y2);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_y2);write(TX_LOC, string'(" "));

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TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;



BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (y3 /= next_y3) THEN

write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns y3="));write(TX_LOC, y3);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_y3);write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

BEGIN-- --------------------a <= transport std_logic_vector'("00"); --0b <= transport std_logic_vector'("00"); --0-- --------------------WAIT FOR 100 ns; -- Time=100 nsa <= transport std_logic_vector'("00"); --0b <= transport std_logic_vector'("01"); --1-- --------------------WAIT FOR 100 ns; -- Time=200 nsa <= transport std_logic_vector'("01"); --1b <= transport std_logic_vector'("11"); --3-- --------------------WAIT FOR 100 ns; -- Time=300 nsa <= transport std_logic_vector'("11"); --3b <= transport std_logic_vector'("10"); --2

13

-- --------------------WAIT FOR 100 ns; -- Time=400 nsa <= transport std_logic_vector'("11"); --3b <= transport std_logic_vector'("00"); --0-- --------------------WAIT FOR 100 ns; -- Time=500 nsa <= transport std_logic_vector'("10"); --2b <= transport std_logic_vector'("11"); --3-- --------------------WAIT FOR 100 ns; -- Time=600 nsa <= transport std_logic_vector'("01"); --1b <= transport std_logic_vector'("01"); --1-- --------------------WAIT FOR 150 ns; -- Time=750 ns-- --------------------

IF (TX_ERROR = 0) THEN write(TX_OUT,string'("No errors or warnings"));writeline(results, TX_OUT);ASSERT (FALSE) REPORT

"Simulation successful (not a failure). No problems detected. "SEVERITY FAILURE;

ELSEwrite(TX_OUT, TX_ERROR);write(TX_OUT, string'(

" errors found in simulation"));writeline(results, TX_OUT);ASSERT (FALSE) REPORT

"Errors found during simulation"SEVERITY FAILURE;

END IF;END PROCESS;

END testbench_arch;

CONFIGURATION Compar2bit_cfg OF testbench ISFOR testbench_archEND FOR;

END Compar2bit_cfg; VARIABLE TX_STR : String(1 to 4096);VARIABLE TX_LOC : LINE;

BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (carry /= next_carry) THEN

write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns carry="));write(TX_LOC, carry);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_carry);

14

write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

BEGIN-- --------------------a <= transport '0';b <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=100 nsb <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=200 nsa <= transport '1';b <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=300 nsb <= transport '1';-- --------------------WAIT FOR 150 ns; -- Time=450 ns-- --------------------IF (TX_ERROR = 0) THEN

write(TX_OUT,string'("No errors or warnings"));writeline(results, TX_OUT);ASSERT (FALSE) REPORT





END IF;END PROCESS;

END testbench_arch;CONFIGURATION hfadr_cfg OF testbench IS

FOR testbench_archEND FOR;

END hfadr_cfg;

15

Output Waveform

2 : 4 Decoder16

Code

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity dec24 is Port ( d_in : in std_logic_vector(1 downto 0); d_out : out std_logic_vector(3 downto 0));end dec24;

architecture Behavioral of dec24 is

beginprocess (d_in)begin

if d_in="00" then d_out<="0001"; elsif d_in="01" then d_out<="0010"; elsif d_in="10" then d_out<="0100"; else d_out<="1000" ; end if; end process;

end Behavioral;

RTL Schematic

17

Synthesis Report

18

===================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : dec24.ngrTop Level Output File Name : dec24Output Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+


Cell Usage :# BELS : 4# LUT2 : 4# IO Buffers : 6# IBUF : 2# OBUF : 4===================================================================

Device utilization summary:---------------------------



===================================================================TIMING REPORT




Minimum period: No path found Minimum input arrival time before clock: No path found

19

Maximum output required time after clock: No path found Maximum combinational path delay: 9.884ns


-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 9.884ns (Levels of Logic = 3) Source: d_in<1> Destination: d_out<2>

Data Path: d_in<1> to d_out<2> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 4 0.924 1.600 d_in_1_ibuf (d_in_1_ibuf) LUT2:i0->o 1 0.653 1.150 mdecod_d_out__n00011 (d_out_2_obuf) OBUF:i->o 5.557 d_out_2_obuf (d_out<2>) ---------------------------------------- Total 9.884ns (7.134ns logic, 2.750ns route) (72.2% logic, 27.8% route)

===================================================================CPU : 4.59 / 5.34 s | Elapsed : 5.00 / 5.00 s -->


Test Bench Report

20

-- M:\VLSICOLLEGE\DECODER24-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE JUN 30 12:12:57 2009-- -- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...) LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY ieee;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;



COMPONENT dec24PORT (

d_in : in std_logic_vector (1 DOWNTO 0);d_out : out std_logic_vector (3 DOWNTO 0)

);END COMPONENT;SIGNAL d_in : std_logic_vector (1 DOWNTO 0);SIGNAL d_out : std_logic_vector (3 DOWNTO 0);

BEGINUUT : dec24PORT MAP (

d_in => d_in,d_out => d_out

);PROCESS

VARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;PROCEDURE CHECK_d_out(

next_d_out : std_logic_vector (3 DOWNTO 0);TX_TIME : INTEGER

) ISVARIABLE TX_STR : String(1 to 4096);

21

VARIABLE TX_LOC : LINE;BEGIN

process (d_in)begin if d_in="00" then d_out<="0001"; elsif d_in="01" then d_out<="0010"; elsif d_in="10" then d_out<="0100"; else d_out<="1000" ; end if; end process;

END;BEGIN

-- --------------------d_in <= transport std_logic_vector'("00"); --0-- --------------------WAIT FOR 100 ns; -- Time=100 nsd_in <= transport std_logic_vector'("11"); --3-- --------------------WAIT FOR 100 ns; -- Time=200 nsd_in <= transport std_logic_vector'("10"); --2-- --------------------WAIT FOR 100 ns; -- Time=300 nsd_in <= transport std_logic_vector'("01"); --1WAIT FOR 150 ns; -- Time=450 ns-- --------------------IF (TX_ERROR = 0) THEN

write(TX_OUT,string'("No errors or warnings"));writeline(results, TX_OUT);ASSERT (FALSE) REPORT





END IF;END PROCESS;

END testbench_arch;CONFIGURATION dec24_cfg OF testbench IS

FOR testbench_archEND FOR;

END dec24_cfg; Batch : - A5

22

Output Waveform

Batch : - A5

23

Half Adder

Code



entity hfadr is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic);end hfadr;

architecture Behavioral of hfadr is

beginsum <= a xor b;carry <= a and b;

end Behavioral;

RTL Schematic

24

Synthesis Report

25

===================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : hfadr.ngrTop Level Output File Name : hfadrOutput Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+






===================================================================TIMING REPORT




Minimum period: No path found

26

Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.624ns


-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 9.624ns (Levels of Logic = 3) Source: b Destination: sum

Data Path: b to sum Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 2 0.924 1.340 b_ibuf (b_ibuf) LUT2:i0->o 1 0.653 1.150 mxor_sum_result1 (sum_obuf) OBUF:i->o 5.557 sum_obuf (sum) ---------------------------------------- Total 9.624ns (7.134ns logic, 2.490ns route) (74.1% logic, 25.9% route)

CPU : 5.84 / 6.26 s | Elapsed : 6.00 / 6.00 s -->


Test Bench Report

27

-- M:\VLSICOLLEGE\HALFADDER-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE JUN 30 12:16:44 2009-- -- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY ieee;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;



COMPONENT hfadrPORT (

a : in std_logic;b : in std_logic;sum : out std_logic;carry : out std_logic

);END COMPONENT;

SIGNAL a : std_logic;SIGNAL b : std_logic;SIGNAL sum : std_logic;SIGNAL carry : std_logic;

BEGINUUT : hfadrPORT MAP (

a => a,b => b,sum => sum,carry => carry

28

);

PROCESSVARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;

PROCEDURE CHECK_sum(next_sum : std_logic;TX_TIME : INTEGER


BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (sum /= next_sum) THEN

write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns sum="));write(TX_LOC, sum);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_sum);write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

PROCEDURE CHECK_carry(next_carry : std_logic;TX_TIME : INTEGER



write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns carry="));write(TX_LOC, carry);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_carry);write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;

29

writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

BEGIN-- --------------------a <= transport '0';b <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=100 nsb <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=200 nsa <= transport '1';b <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=300 nsb <= transport '1';-- --------------------WAIT FOR 150 ns; -- Time=450 ns-- --------------------






END IF;END PROCESS;

END testbench_arch;

CONFIGURATION hfadr_cfg OF testbench ISFOR testbench_archEND FOR;

END hfadr_cfg; Batch : - A5

30

Output Waveform

Batch : - A5

31

Full Adder

Code



entity full_adder is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; carry : out std_logic);end full_adder;

architecture dataflow of full_adder is

begin sum <= a xor b xor cin; carry <= (a and b) or (a and cin) or (b and cin);

end dataflow;

RTL Schematic

32

Synthesis Report

33

===================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : full_adder.ngrTop Level Output File Name : full_adderOutput Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+


Macro Statistics :# Xors : 1# 1-bit xor3 : 1





===================================================================TIMING REPORT



34


Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.624ns


-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 9.624ns (Levels of Logic = 3) Source: b Destination: carry

Data Path: b to carry Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 2 0.924 1.340 b_ibuf (b_ibuf) LUT3:i0->o 1 0.653 1.150 carry1 (carry_obuf) OBUF:i->o 5.557 carry_obuf (carry) ---------------------------------------- Total 9.624ns (7.134ns logic, 2.490ns route) (74.1% logic, 25.9% route)

CPU : 0.42 / 0.70 s | Elapsed : 0.00 / 1.00 s -->


35

Test Bench Report-- M:\VLSI\FULL_ADDER-- VHDL Test Bench created by-- HDL Bencher 5.1i-- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY ieee;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;



COMPONENT full_adderPORT (

a : in std_logic;b : in std_logic;cin : in std_logic;sum : out std_logic;carry : out std_logic

);END COMPONENT;SIGNAL a : std_logic;SIGNAL b : std_logic;SIGNAL cin : std_logic;SIGNAL sum : std_logic;SIGNAL carry : std_logic;

BEGINUUT : full_adderPORT MAP (

a => a,b => b,

36

cin => cin,sum => sum,carry => carry

);PROCESS

VARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;

PROCEDURE CHECK_sum(next_sum : std_logic;TX_TIME : INTEGER


BEGIN sum <= a xor b xor cin;

carry <= (a and b) or (a and cin) or (b and cin);

END;PROCEDURE CHECK_carry(

next_carry : std_logic;TX_TIME : INTEGER



write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns carry="));write(TX_LOC, carry);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_carry);write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

BEGIN-- --------------------a <= transport '0';b <= transport '1';cin <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=100 ns

37

a <= transport '1';b <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=200 nsa <= transport '0';b <= transport '1';cin <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=300 nsa <= transport '1';b <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=400 nsa <= transport '0';cin <= transport '0';-- --------------------WAIT FOR 100 ns; -- Time=500 nsa <= transport '1';b <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=600 nsa <= transport '0';b <= transport '0';cin <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=700 nsa <= transport '1';b <= transport '1';-- --------------------WAIT FOR 150 ns; -- Time=850 ns






END IF;END PROCESS;

END testbench_arch;CONFIGURATION full_adder_cfg OF testbench IS

FOR testbench_arch

38

END FOR;END full_adder_cfg;

Output Waveform

39

8 : 1 MUX

Code



entity mux81 is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(2 downto 0); c : out std_logic);end mux81;

architecture Behavioral of mux81 is

begin process(a,b) begin if b="000" then c<=a(0); elsif b="001" then c<=a(1); elsif b="010" then c<=a(2); elsif b="011" then c<=a(3); elsif b="100" then c<=a(4); elsif b="101" then c<=a(5); elsif b="110" then c<=a(6);

else c<=a(7); end if;end process;

end Behavioral;

40

RTL Schematic

41

]

Synthesis Report

=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : mux81.ngrTop Level Output File Name : mux81Output Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+Design Statistics# IOs : 12Macro Statistics :# Multiplexers : 1# 1-bit 8-to-1 multiplexer : 1Cell Usage :# BELS : 7# LUT3 : 4# MUXF5 : 2# MUXF6 : 1# IO Buffers : 12

42

# IBUF : 11# OBUF : 1=========================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5 Number of Slices: 2 out of 2352 0% Number of 4 input LUTs: 4 out of 4704 0% Number of bonded IOBs: 12 out of 144 8% =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 10.635nsTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 10.635ns (Levels of Logic = 5) Source: b<0> Destination: c Data Path: b<0> to c Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 4 0.924 1.600 b_0_ibuf (b_0_ibuf) LUT3:i0->o 1 0.653 0.000 mmux_c_inst_lut3_01 (mmux_c__net0) MUXF5:i0->o 1 0.375 0.000 mmux_c_inst_mux_f5_0 (mmux_c__net2) MUXF6:i0->o 1 0.376 1.150 mmux_c_inst_mux_f6_0 (c_obuf) OBUF:i->o 5.557 c_obuf (c) ---------------------------------------- Total 10.635ns (7.885ns logic, 2.750ns route) (74.1% logic, 25.9% route)=========================================================================

43

CPU : 0.39 / 0.66 s | Elapsed : 0.00 / 1.00 s--> Total memory usage is 55460 kilobytes

Test Bench Report

-- M:\VLSI\MUX81-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE JUN 30 12:36:16 2009-- -- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY ieee;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;ENTITY testbench ISEND testbench;ARCHITECTURE testbench_arch OF testbench IS-- If you get a compiler error on the following line,

44

-- from the menu do Options->Configuration select VHDL 87FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT mux81PORT (

a : in std_logic_vector (7 DOWNTO 0);b : in std_logic_vector (2 DOWNTO 0);c : out std_logic

);END COMPONENT;

SIGNAL a : std_logic_vector (7 DOWNTO 0);SIGNAL b : std_logic_vector (2 DOWNTO 0);SIGNAL c : std_logic;

BEGINUUT : mux81PORT MAP (

a => a,b => b,c => c

);PROCESS

VARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;PROCEDURE CHECK_c(

next_c : std_logic;TX_TIME : INTEGER


BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (c /= next_c) THEN

write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns c="));write(TX_LOC, c);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_c);write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;BEGIN-- --------------------

45

a <= transport std_logic_vector'("00100000"); --20b <= transport std_logic_vector'("010"); --2-- --------------------WAIT FOR 100 ns; -- Time=100 nsa <= transport std_logic_vector'("00010000"); --10b <= transport std_logic_vector'("000"); --0-- --------------------WAIT FOR 100 ns; -- Time=200 nsa <= transport std_logic_vector'("00011000"); --18b <= transport std_logic_vector'("111"); --7-- --------------------WAIT FOR 100 ns; -- Time=300 nsa <= transport std_logic_vector'("11000000"); --C0b <= transport std_logic_vector'("100"); --4-- --------------------WAIT FOR 100 ns; -- Time=400 nsa <= transport std_logic_vector'("11110000"); --F0b <= transport std_logic_vector'("110"); --6-- --------------------WAIT FOR 100 ns; -- Time=500 nsa <= transport std_logic_vector'("10000000"); --80b <= transport std_logic_vector'("101"); --5-- --------------------WAIT FOR 100 ns; -- Time=600 nsa <= transport std_logic_vector'("10000000"); --80b <= transport std_logic_vector'("001"); --1-- --------------------WAIT FOR 100 ns; -- Time=700 nsa <= transport std_logic_vector'("10101010"); --AAb <= transport std_logic_vector'("011"); --3-- --------------------WAIT FOR 150 ns; -- Time=850 ns-- --------------------






END IF;

46

END PROCESS;END testbench_arch;

CONFIGURATION mux81_cfg OF testbench ISFOR testbench_archEND FOR;

END mux81_cfg;

Output Waveform

47

Experiment No : 02

FLIP-FLOP, SHIFT REGISTER, COUNTER

48

PROBLEM STATEMENT :

To design, implement and verify the following using VHDL. Flip-Flop Shift Register Counter

THEORY :

FLIP FLOP

The state of latch or flip flop is switched by change in control input. This momentary change is called a trigger and transition it causes is said to higher flip flop. The D latch will pulses in its control input is essentially flip flop i.e. trigger every time pulse goes to the logic 1 level. As long as pulse input remains in this level, any change in data input will change the output and state of latch.

The problem with latch is that it responds to change in level of clock pulse. There are two ways the latch can be modified to form a flip flop. One way is to employ two latches in special configuration that isolates output of flip flop from being affected while its input is changing. Another way is to produce flip flop that trigger only during signal transition (from 0 to 1 or from 1 to 0) and is disabled during rest of clock pulse duration.

POSITIVE EDGE NEGATIVE EDGE STATE TABLE

GRAPHIC SYMBOL FOR EDGE-TRIGGERED D – FLIP FLOP

SHIFT REGISTER

D Q(t+1) 0 0 1 1

49

D Q _

Clk Q

D Q _

Clk Q

The register capable of shifting its binary information in one or both direstions is called a shift register. The configuration of shift register consists of a chain of flip-flops in cascade with output of one flip-flop connected to the input of the next flip-flop. All the flip-flops receive common clock pulses, which activate the shift from one stage to the next stage. Symbolic representation of different type of data movement in shift register operation:

DATABITS

SHIFT REGISTER (right shift)

SERIAL IN SERIAL OUT SHIFT REGISTER(left shift)

Dout Din

O O O O

CLOCK

We will illustrate the entry of four bit binary number 1111 into the register, beginning with right most bit.

Initially, the register is cleared. So, QA QB QC QD = 0 0 0 050

QA DA

A

QB DB

B

QD DD

D

QC DC

C

a) When data 1111 is applied serially, i.e. left most 1 is applied as DinDin =1 QA QB QC QD = 0 0 0 0 The arrival of first falling clock edge sets the right most flip-flop and saved word becomes: QA QB QC QD = 0 0 0 1

b) Next clock ,QC sets and contents become: QA QB QC QD = 0 0 1 1

c) Next clock, QB sets and contents become: QA QB QC QD = 0 1 1 1

d) Next clock, QA sets and contents become: QA QB QC QD = 1 1 1 1

UP - DOWN SYNCHRONOUS COUNTER.

An up down counter is one that is capable of progressing in increasing order or decreasing order through certain sequence. An up/down counter is also called bidirectional counter. Usually up/down operation of counter is controlled by up/down signal. When this signal is high, counter goes through up sequence i.e. 0,1,2,3….n when goes low, counter follows reverse sequence i.e. n,n-1,n-2,……0 for 3-bit counter these sequence are 0,1,2,3,4,5,6,7 for up operation and 7,6,5,4,3,2,1,0 for down operation.

K-map simplification: Tc = Ud Qb Qa + Ud Qa Qb

Tb = Ud Qa + Ud Qa

Ta = 1

STATE TABLE

CP UP QC QB QA DOWN

0 0 0 0

51

1 0 0 0

2 0 1 1

3 0 1 1

4 1 0 0

5 1 0 0

6 1 1 1

7 1 1 1

STATE TABLE

Up/Down Present State Next State Flip FlopUD Dec Eq QC QB QA QC+1 QB+1 QA+1 TC TB TA

0 0 0 0 0 0 0 1 0 0 10 1 0 0 1 0 1 0 0 1 10 2 0 1 0 0 1 1 0 0 10 3 0 1 1 1 0 0 1 1 10 4 1 0 0 1 0 1 0 0 10 5 1 0 1 1 1 0 0 1 10 6 1 1 0 1 1 1 0 0 10 7 1 1 1 0 0 0 1 1 11 7 1 1 1 1 1 0 0 0 11 6 1 1 0 1 0 1 0 1 11 5 1 0 1 1 0 0 0 0 11 4 1 0 0 0 1 1 1 1 11 3 0 1 1 0 1 0 0 0 11 2 0 1 0 0 0 1 0 1 11 1 0 0 1 0 0 0 0 0 11 0 0 0 0 1 1 1 1 1 1

CONCLUSION :

52

The Flip-flop, shift Register and Synchronous Counter were designed, implemented and verified using VHDL.

D Flip Flop

Code

library IEEE;

53

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity dff is Port ( d : in std_logic; clk : in std_logic; reset : in std_logic; q : out std_logic);end dff;

architecture Behavioral of dff is

begin process(clk) begin if(reset='1')then q<='0'; else if ( clk'event and clk='1') then q<=d; end if; end if; end process;

end Behavioral;

RTL Schematic

54

Synthesis Report===================================================================

55

* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : dff.ngrTop Level Output File Name : dffOutput Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+Design Statistics# IOs : 4Macro Statistics :# Registers : 1# 1-bit register : 1Cell Usage :# FlipFlops/Latches : 1# FDC : 1# Clock Buffers : 1# BUFGP : 1# IO Buffers : 3# IBUF : 2# OBUF : 1===================================================================Device utilization summary:---------------------------


Number of Slices: 1 out of 2352 0% Number of Slice Flip Flops: 1 out of 4704 0% Number of bonded IOBs: 3 out of 144 2% Number of GCLKs: 1 out of 4 25%

===================================================================TIMING REPORT


Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 1 |-----------------------------------+------------------------+-------+

56


Minimum period: No path found Minimum input arrival time before clock: 2.857ns Maximum output required time after clock: 7.999ns Maximum combinational path delay: No path found

Timing Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Offset: 2.857ns (Levels of Logic = 1) Source: reset Destination: q Destination Clock: clk rising

Data Path: reset to q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 1 0.924 1.150 reset_ibuf (reset_ibuf) FDC:clr 0.783 q ---------------------------------------- Total 2.857ns (1.707ns logic, 1.150ns route) (59.7% logic, 40.3% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset: 7.999ns (Levels of Logic = 1) Source: q Destination: q Source Clock: clk rising Data Path: q to q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:c->q 1 1.292 1.150 q (q_obuf) OBUF:i->o 5.557 q_obuf (q) ---------------------------------------- Total 7.999ns (6.849ns logic, 1.150ns route) (85.6% logic, 14.4% route)===================================================================CPU : 1.66 / 1.94 s | Elapsed : 2.00 / 2.00 s--> Total memory usage is 55316 kilobytes

Test Bench Report

57

-- M:\VLSICOLLEGE\D_FF-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE JUN 30 12:39:19 2009-- -- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)





COMPONENT dffPORT (

d : in std_logic;clk : in std_logic;reset : in std_logic;q : out std_logic

);END COMPONENT;

SIGNAL d : std_logic;SIGNAL clk : std_logic;SIGNAL reset : std_logic;SIGNAL q : std_logic;

BEGINUUT : dffPORT MAP (

d => d,clk => clk,reset => reset,q => q

58

);

PROCESS -- clock process for clk,BEGIN

CLOCK_LOOP : LOOPclk <= transport '0';WAIT FOR 10 ns;clk <= transport '1';WAIT FOR 10 ns;WAIT FOR 40 ns;clk <= transport '0';WAIT FOR 40 ns;END LOOP CLOCK_LOOP;

END PROCESS;

PROCESS -- Process for clkVARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;

PROCEDURE CHECK_q(next_q : std_logic;TX_TIME : INTEGER


BEGINprocess(clk)

begin if(reset='1')then q<='0'; else if ( clk'event and clk='1') then q<=d; end if; end if; end process;

END;

BEGIN-- --------------------d <= transport '0';reset <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=100 nsd <= transport '1';-- --------------------WAIT FOR 200 ns; -- Time=300 nsreset <= transport '0';

59

-- --------------------WAIT FOR 360 ns; -- Time=660 ns-- --------------------






END IF;END PROCESS;

END testbench_arch;

CONFIGURATION dff_cfg OF testbench ISFOR testbench_archEND FOR;

END dff_cfg;

Batch : - A5

60

Output Waveform

Batch : - A5

61

Shift Register

Code



entity shift_reg is Port ( din : in std_logic; clk : in std_logic; qin : inout std_logic_vector(9 downto 0));end shift_reg;

architecture Behavioral of shift_reg is

beginprocess(clk)beginif (clk'event and clk='1')thenqin(0)<=din;qin(1)<=qin(0);qin(2)<=qin(1);qin(3)<=qin(2);qin(4)<=qin(3);qin(5)<=qin(4);qin(6)<=qin(5);qin(7)<=qin(6);qin(8)<=qin(7);qin(9)<=qin(8);end if;end process;

end Behavioral;

RTL Schematic

62

Synthesis Report

63

=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : shift_reg.ngrTop Level Output File Name : shift_regOutput Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+


Macro Statistics :# Registers : 10# 1-bit register : 10

Cell Usage :# FlipFlops/Latches : 11# FD : 11# Clock Buffers : 1# BUFGP : 1# IO Buffers : 11# IBUF : 1# OBUF : 10=========================================================================



Number of Slices: 6 out of 2352 0% Number of Slice Flip Flops: 11 out of 4704 0% Number of bonded IOBs: 11 out of 144 7% Number of GCLKs: 1 out of 4 25%

=========================================================================TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

64

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 11 |-----------------------------------+------------------------+-------+


Minimum period: 3.385ns (Maximum Frequency: 295.421MHz) Minimum input arrival time before clock: 3.017ns Maximum output required time after clock: 8.189ns Maximum combinational path delay: No path found


-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'Delay: 3.385ns (Levels of Logic = 0) Source: qin_6 Destination: qin_7 Source Clock: clk rising Destination Clock: clk rising

Data Path: qin_6 to qin_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:c->q 2 1.292 1.340 qin_6 (qin_6) FD:d 0.753 qin_7 ---------------------------------------- Total 3.385ns (2.045ns logic, 1.340ns route) (60.4% logic, 39.6% route)

-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Offset: 3.017ns (Levels of Logic = 1) Source: din Destination: qin_0 Destination Clock: clk rising

65

Data Path: din to qin_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 2 0.924 1.340 din_ibuf (din_ibuf) FD:d 0.753 qin_0 ---------------------------------------- Total 3.017ns (1.677ns logic, 1.340ns route) (55.6% logic, 44.4% route)

-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset: 8.189ns (Levels of Logic = 1) Source: qin_8 Destination: qin<8> Source Clock: clk rising

Data Path: qin_8 to qin<8> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:c->q 2 1.292 1.340 qin_8 (qin_8) OBUF:i->o 5.557 qin_8_obuf (qin<8>) ---------------------------------------- Total 8.189ns (6.849ns logic, 1.340ns route) (83.6% logic, 16.4% route)

=========================================================================CPU : 0.51 / 0.80 s | Elapsed : 0.00 / 0.00 s -->


66

Test Bench Report

-- M:\VLSICOLLEGE\SHIFTREGISTER-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE JUN 30 12:52:35 2009-- -- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)--





COMPONENT shift_regPORT (

din : in std_logic;clk : in std_logic;qin : inout std_logic_vector (9 DOWNTO 0)

);END COMPONENT;

SIGNAL din : std_logic;SIGNAL clk : std_logic;SIGNAL qin : std_logic_vector (9 DOWNTO 0);

BEGINUUT : shift_regPORT MAP (

din => din,clk => clk,qin => qin

67

);



END PROCESS;


PROCEDURE CHECK_qin(next_qin : std_logic_vector (9 DOWNTO 0);TX_TIME : INTEGER


BEGINprocess(clk)beginif (clk'event and clk='1')thenqin(0)<=din;qin(1)<=qin(0);qin(2)<=qin(1);qin(3)<=qin(2);qin(4)<=qin(3);qin(5)<=qin(4);qin(6)<=qin(5);qin(7)<=qin(6);qin(8)<=qin(7);qin(9)<=qin(8);end if;end process;

END;

BEGIN-- --------------------din <= transport '0';-- --------------------WAIT FOR 200 ns; -- Time=200 ns

68

din <= transport '1';-- --------------------WAIT FOR 600 ns; -- Time=800 nsdin <= transport '0';-- --------------------WAIT FOR 210 ns; -- Time=1010 ns-- --------------------






END IF;END PROCESS;

END testbench_arch;

CONFIGURATION shift_reg_cfg OF testbench ISFOR testbench_archEND FOR;

END shift_reg_cfg;

69

Batch : - A1

Output Waveform

70

Batch : - A5

UP DOWN Counter

Codelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity updncntr is Port ( u_d : in std_logic; rst : in std_logic; clk : in std_logic; q : inout std_logic_vector(3 downto 0));end updncntr;architecture Behavioral of updncntr isbegin process(clk,rst)

beginif rst='1'then q<="0000";else if clk'event and clk='1'then

if u_d='1'then if q="1111" then

q<="0000"; else

q<=q+1; end if;

else if q="0000"then

q<="1111"; else

q<=q-1; end if;

end if; end if; end if;end process;

end Behavioral;

71

RTL Schematic

72

Synthesis Report=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : updncntr.ngrTop Level Output File Name : updncntrOutput Format : NGCOptimization Criterion : SpeedKeep Hierarchy : NOMacro Generator : macro+Design Statistics# IOs : 7Macro Statistics :# Registers : 1# 4-bit register : 1# Adders/Subtractors : 1# 4-bit addsub : 1Cell Usage :# BELS : 20# GND : 1# LUT1 : 2# LUT1_L : 1# LUT2 : 2# LUT2_L : 3# LUT3_L : 3# LUT4_D : 2# MUXCY : 3# XORCY : 3# FlipFlops/Latches : 4# FDC : 4# Clock Buffers : 1# BUFGP : 1# IO Buffers : 6# IBUF : 2# OBUF : 4=========================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5 Number of Slices: 7 out of 2352 0% Number of Slice Flip Flops: 4 out of 4704 0% Number of 4 input LUTs: 13 out of 4704 0% Number of bonded IOBs: 6 out of 144 4%

73

Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 4 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 8.094ns (Maximum Frequency: 123.548MHz) Minimum input arrival time before clock: 9.080ns Maximum output required time after clock: 8.589ns Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'Delay: 8.094ns (Levels of Logic = 3) Source: q_1 Destination: q_1 Source Clock: clk rising Destination Clock: clk rising Data Path: q_1 to q_1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:c->q 4 1.292 1.600 q_1 (q_1) LUT2:i0->o 1 0.653 1.150 ker341_sw0 (n475) LUT4_D:I3->O 2 0.653 1.340 ker341 (n343) LUT3_L:I0->LO 1 0.653 0.000 _n0003<1>1 (_n0003<1>) FDC:d 0.753 q_1 ---------------------------------------- Total 8.094ns (4.004ns logic, 4.090ns route) (49.5% logic, 50.5% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Offset: 9.080ns (Levels of Logic = 7) Source: u_d Destination: q_3

74

Destination Clock: clk rising Data Path: u_d to q_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:i->o 3 0.924 1.480 u_d_ibuf (u_d_ibuf) LUT1:i0->o 3 0.653 1.480 _n00051 (_n0005) LUT2_L:I1->LO 1 0.653 0.000 maddsub__n0004_inst_lut2_01 (maddsub__n0004_inst_lut2_0) MUXCY:s->o 1 0.784 0.000 maddsub__n0004_inst_cy_1 (maddsub__n0004_inst_cy_1) MUXCY:ci->o 0 0.050 0.000 maddsub__n0004_inst_cy_2 (maddsub__n0004_inst_cy_2) XORCY:ci->o 1 0.500 1.150 maddsub__n0004_inst_sum_3 (_n0004<3>) LUT3_L:I1->LO 1 0.653 0.000 _n0003<3>1 (_n0003<3>) FDC:d 0.753 q_3 ---------------------------------------- Total 9.080ns (4.970ns logic, 4.110ns route) (54.7% logic, 45.3% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset: 8.589ns (Levels of Logic = 1) Source: q_0 Destination: q<0> Source Clock: clk rising

Data Path: q_0 to q<0> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDC:c->q 5 1.292 1.740 q_0 (q_0) OBUF:i->o 5.557 q_0_obuf (q<0>) ---------------------------------------- Total 8.589ns (6.849ns logic, 1.740ns route) (79.7% logic, 20.3% route)=========================================================================CPU : 2.38 / 4.16 s | Elapsed : 2.00 / 3.00 s--> Total memory usage is 54372 kilobytes

75

Test Bench Report

-- D:\VLSI\UPDOWN_COUNTER-- VHDL Test Bench created by-- HDL Bencher 5.1i-- TUE JUN 30 12:07:01 2009-- -- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)--





COMPONENT updncntrPORT (

u_d : in std_logic;rst : in std_logic;clk : in std_logic;q : inout std_logic_vector (3 DOWNTO 0)

);END COMPONENT;

SIGNAL u_d : std_logic;SIGNAL rst : std_logic;SIGNAL clk : std_logic;SIGNAL q : std_logic_vector (3 DOWNTO 0);

BEGINUUT : updncntrPORT MAP (

76

u_d => u_d,rst => rst,clk => clk,q => q

);



END PROCESS;


PROCEDURE CHECK_q(next_q : std_logic_vector (3 DOWNTO 0);TX_TIME : INTEGER


BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (q /= next_q) THEN

write(TX_LOC,string'("Error at time="));write(TX_LOC, TX_TIME);write(TX_LOC,string'("ns q="));write(TX_LOC, q);write(TX_LOC, string'(", Expected = "));write(TX_LOC, next_q);write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;writeline(results, TX_LOC);Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

BEGIN

77

-- --------------------u_d <= transport '1';rst <= transport '0';-- --------------------WAIT FOR 600 ns; -- Time=600 nsu_d <= transport '1';-- --------------------WAIT FOR 200 ns; -- Time=800 nsu_d <= transport '0';-- --------------------WAIT FOR 110 ns; -- Time=910 ns-- --------------------






END IF;END PROCESS;

END testbench_arch;

CONFIGURATION updncntr_cfg OF testbench ISFOR testbench_archEND FOR;

END updncntr_cfg;

78

Batch : - A5

Output Waveform

79

Experiment No : 03

TRAFFIC LIGHT CONTROLLER

PROBLEM STATEMENT :

To design a sequential traffic light controller, for the intersection of ‘A’ street and ‘B’ street.

THEORY :

Each street A and B has traffic sensors, which detect presence of vehicles approached or stopped at the intersection.

Sa = 1 :means vehicle is approaching on A street.Sb = 1 :means vehicle is approaching on b street.

‘A’ street is the main street and has a green light until a car approaches on ‘B’. The light then changes and ‘B’ has a green light. At the end of 50 seconds, the lights change back unless there is a car on ‘B’ street and none on ‘A’ in which case, the ‘B’ cycle is extended 10 seconds more. When ‘A’ is green, it remains green at least 60 seconds and then light changes only when car approaches on ‘B’.

Three of outputs (Ga,Ya,Ra) drive green, yellow and red light on ‘A’ street. Other three (Gb,Yb,Rb) drive corresponding light on ‘B’ street. Moore state graph for controller is shown. For timing purpose, the sequential network is driven by a clock, which has a 10-sec period. Thus, a state change can occur at-most once every 10 seconds.

The notations used are as follows- GaRb implies Ga=Rb=1 and all other variables are 0. SaSb implies Sa=0 and Sb=1 cause transition. An arc without a label implies that a state transition will occur when

clock occurs, independent of clock variables.

Thus the green ‘A’ light will stay ON for 6 clock cycles (60 seconds) and then change to yellow if a car is waiting on ‘B’ street.

80

Sb’

Sb

(Sa+Sb’)

VHDL CODE FOR TRAFFIC LIGHT CONTROLLER : VHDL code represents the state machine by two processes. Whenever state Sa or Sb changes, the first process updates the output and next state. Since states S0 through S4 have same outputs and next states are in numeric sequence, we use ‘when’ clause with a range instead of five separate ‘when’ clauses.

when 0 to 4 => Ga <= ‘1’ ; Rb <= ‘1’;81

S5GaRb

S3GaRb

S9RaGb

S10RaGb

S11RaGb

S4GaRb

S6YaRb

S8RaGb

S7RaGb

S2GaRb

S1GaRb

S0GaRb

STATE DIAGRAM FOR

Traffic Light Controller

S12RaYb

next state <= state + 1 ;

Clk Sa Sb

Ga Ya Ra Gb Yb Rb

Before completing the design of traffic light controller, we will test the VHDL code to see that it meets specifications. As a minimum output , test sequence should cause all arcs on state graph to be traversed atleast once. To interpret the simulator output, we define type named light with values R,Y,G and two signals light A and light B which can assume these values.

CONCLUSION :

The sequential traffic light controller for an intersection of two streets (‘A’ street and ‘B’ street.) was designed and simulated using VHDL.

82

PAL 22V10

Name : - Atul Kumar Bisen Batch : - A1

Traffic Light

Codelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity tlc is Port ( clk,sa,sb : in std_logic; ra,rb,ga,gb,ya,yb : out std_logic);end tlc;

architecture Behavioral of tlc is signal state, nextstate: integer range 0 to 12; type light is (r,y,g); signal lighta,lightb:light; --define signal for waveform output

begin

process(state,sa,sb) begin ra<='0';rb<='0';ya<='0';yb<='0';ga<='0';gb<='0'; case state is when 0 to 4 => ga <='1';rb<='1';nextstate<=state+1; when 5=> ga<='1'; rb<='1'; if sb='1' then nextstate<=6;end if; when 6=> ya<='1'; rb<='1';nextstate<=7; when 7 to 10 => ra <='1';gb<='1';nextstate<=state+1;

when 11 => ra <='1';gb<='1'; if(sa='1' or sb='0') then nextstate<=12;end if; when 12 => ra <='1';yb<='1';nextstate <=0;

end case; end process;

process(clk) begin

if clk='1' then state <=nextstate;

end if;

83

end process;

-- lighta <= r when ra='1' else-- when ya='1' else-- when ga='1'-- lightb <= r when rb='1'else-- when yb='1' else-- when gb='1'

end Behavioral;

84

RTL Schematic

85

Synthesis Report=================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : tlc.ngrTop Level Output File Name : tlcOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 9Macro Statistics :# Adders/Subtractors : 1# 4-bit adder : 1Cell Usage :# BELS : 28# GND : 1# LUT1 : 4# LUT3 : 3# LUT4 : 12# MUXCY : 3# MUXF5 : 1# VCC : 1# XORCY : 3# FlipFlops/Latches : 8# LD : 8# Clock Buffers : 1# BUFGP : 1# IO Buffers : 8# IBUF : 2# OBUF : 6===================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5

Number of Slices: 11 out of 2352 0% Number of Slice Flip Flops: 8 out of 4704 0% Number of 4 input LUTs: 19 out of 4704 0% Number of bonded IOBs: 8 out of 144 5% Number of GCLKs: 1 out of 4 25%

===================================================================TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

86

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 4 |_n0029(_n00291:O) | NONE(*)(nextstate_2) | 4 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.


Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: 11.471ns Maximum combinational path delay: No path found

Timing Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset: 11.471ns (Levels of Logic = 2) Source: state_2 (LATCH) Destination: ya (PAD) Source Clock: clk falling

Data Path: state_2 to ya Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ LD:G->Q 13 1.421 2.500 state_2 (state_2) LUT4:I2->O 2 0.653 1.340 _n00211 (ya_OBUF) OBUF:I->O 5.557 ya_OBUF (ya) ---------------------------------------- Total 11.471ns (7.631ns logic, 3.840ns route) (66.5% logic, 33.5% route)

===================================================================CPU : 36.59 / 40.42 s | Elapsed : 36.00 / 38.00 s --> Total memory usage is 60876 kilobytes

87

Test Bench Report

-- H:\TLCONTROLLER-- VHDL Test Bench created by-- HDL Bencher 6.1i-- Sat Aug 23 11:53:50 2008-- Notes:-- 1) This testbench has been automatically generated from-- your Test Bench Waveform-- 2) To use this as a user modifiable testbench do the following:-- - Save it as a file with a .vhd extension (i.e. File->Save As...)-- - Add it to your project as a testbench source (i.e. Project->Add Source...)

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;USE STD.TEXTIO.ALL;

ENTITY tl ISEND tl;ARCHITECTURE testbench_arch OF tl ISFILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT tlcPORT (

clk : In std_logic;sa : In std_logic;sb : In std_logic;ra : Out std_logic;rb : Out std_logic;ga : Out std_logic;gb : Out std_logic;ya : Out std_logic;yb : Out std_logic

);END COMPONENT;

SIGNAL clk : std_logic;SIGNAL sa : std_logic;SIGNAL sb : std_logic;SIGNAL ra : std_logic;SIGNAL rb : std_logic;SIGNAL ga : std_logic;SIGNAL gb : std_logic;SIGNAL ya : std_logic;SIGNAL yb : std_logic;

BEGINUUT : tlc

88

PORT MAP (clk => clk,sa => sa,sb => sb,ra => ra,rb => rb,ga => ga,gb => gb,ya => ya,yb => yb

);PROCESS -- clock process for clk,BEGIN


END PROCESS;

PROCESS -- Process for clkVARIABLE TX_OUT : LINE;VARIABLE TX_ERROR : INTEGER := 0;PROCEDURE CHECK_ra(

next_ra : std_logic;TX_TIME : INTEGER


BEGINEND;PROCEDURE CHECK_rb(

next_rb : std_logic;TX_TIME : INTEGER


BEGIN

END;PROCEDURE CHECK_ga(

next_ga : std_logic;TX_TIME : INTEGER

) ISVARIABLE TX_STR : String(1 to 4096);

89

VARIABLE TX_LOC : LINE;BEGIN

END;

PROCEDURE CHECK_gb(next_gb : std_logic;TX_TIME : INTEGER


BEGINEND;

PROCEDURE CHECK_ya(next_ya : std_logic;TX_TIME : INTEGER


BEGIN-- If compiler error ("/=" is ambiguous) occurs in the next line of code-- change compiler settings to use explicit declarations onlyIF (ya /= next_ya) THEN

STD.TEXTIO.write(TX_LOC,string'("Error at time="));STD.TEXTIO.write(TX_LOC, TX_TIME);STD.TEXTIO.write(TX_LOC,string'("ns ya="));IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ya);STD.TEXTIO.write(TX_LOC, string'(", Expected = "));IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ya);STD.TEXTIO.write(TX_LOC, string'(" "));TX_STR(TX_LOC.all'range) := TX_LOC.all;STD.TEXTIO.writeline(results, TX_LOC);STD.TEXTIO.Deallocate(TX_LOC);ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;TX_ERROR := TX_ERROR + 1;

END IF;END;

PROCEDURE CHECK_yb(next_yb : std_logic;TX_TIME : INTEGER


BEGIN

END;

90

BEGIN-- --------------------sa <= transport '0';sb <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=100 nssb <= transport '1';-- --------------------WAIT FOR 100 ns; -- Time=200 nssa <= transport '1';sb <= transport '0';-- --------------------WAIT FOR 110 ns; -- Time=310 ns-- --------------------

END PROCESS;END testbench_arch;

CONFIGURATION tlc_cfg OF tl ISFOR testbench_archEND FOR;

END tlc_cfg;

91

Name : - Amritesh KumarBatch : - A1

Output Waveform

Experiment No : 0492

FIFO ( FIRST IN FIRST OUT )

PROBLEM STATEMENT :

To design, implement and verify a Synchronous FIFO using VHDL.

THEORY :

The synchronous FIFO is a first-in-first-out memory queue. Its control logic performs all the necessary read and write pointer management, generate status flags, and generates optional handshake signals for interfacing with the user logic.

The FIFO has a single clock port for both data-read and data-write operations. Data presented at the module’s data-input port (DIN) is written into the next available memory location on the rising edge of the clock when the write-enable input (WR_EN) is HIGH. The data can be read out of FIFO via module’s data-out port (DOUT) in the order in which it was written by asserting the read enable (RD_EN) prior to rising edge of the clock.

The synchronous FIFO clock (CLK) is rising edge active for the FIFO core. However, it can be made falling edge active by inserting an inverter between the clock source and the FIFO’s clock input.

When the RD pin is asserted, we get high impedance at the data input.When the WR pin is asserted, we get high Impedance at the data output.

When the CLR is pressed, the counter is cleared and initialized. Similarly, when the Reset is asserted, both the counters are initialized to “000” and the shift registers are also reseted.

93

CONCLUSION :The FIFO was designed, implemented and verified using VHDL

Name : - Amritesh KumarBatch : - A1

94

D EC O D E R

Clr Q

EN

Clk R

Clr Q

EN

Clk R

D Q

EN

Clk R

D Q

EN

Clk R

M U L T I P L E X ER

First In First Out ( FIFO )

Codelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;

entity fif is Port ( clk : in std_logic; rst : in std_logic; rd : in std_logic; wr : in std_logic; rdinc : in std_logic; wrinc : in std_logic; rdptrclr : in std_logic; wrptrclr : in std_logic; data_in : in std_logic_vector(8 downto 0); data_out : out std_logic_vector(8 downto 0));end fif;

architecture Behavioral of fif istype fifo_array is array(7 downto 0) of std_logic_vector(8 downto 0);signal fifo: fifo_array;signal wrptr,rdptr:std_logic_vector(2 downto 0);signal en:std_logic_vector(7 downto 0);signal dmuxout:std_logic_vector(8 downto 0);

begin-- fifo register array:reg_array:process(rst,clk)beginif rst='1' thenfor i in 7 downto 0 loopfifo(i)<=(others=>'0');--aggregateend loop;elsif (clk'event and clk ='1') thenif wr='1' thenfor i in 7 downto 0 loopif en(i)='1' thenfifo(i)<=data_in;elsefifo(i)<=fifo(i);end if;end loop;

95

end if; end if;end process;--read pointerread_count:process(rst,clk)beginif rst='1' thenrdptr<=(others=>'0');elsif(clk'event and clk='1') thenif rdptrclr='1' thenrdptr<=(others=>'0');elsif rdinc='1' thenrdptr<=rdptr+1;end if;end if;end process;--write pointerwrite_count:process(rst,clk)beginif rst='1' thenwrptr<=(others=>'0');elsif(clk'event and clk='1') thenif wrptrclr='1' thenwrptr<=(others=>'0');elsif wrinc='1' thenwrptr<=wrptr+1;end if;end if;end process;--8:1 output data MUXwith rdptr selectdmuxout<=fifo(0) when "000", fifo(1) when "001",

fifo(2) when "010", fifo(3) when "011", fifo(4) when "100", fifo(5) when "101", fifo(6) when "110", fifo(7) when others;

--fifo register select decoderwith wrptr selecten<="00000001" when "000", "00000010" when "001", "00000100" when "010", "00001000" when "011", "00010000" when "100", "00100000" when "101", "01000000" when "110", "10000000" when others;--three_state control of outputs

96

three_state:process(rd,dmuxout)beginif rd='1' thendata_out<=dmuxout;elsedata_out<=(others=>'Z');end if;end process; end Behavioral;

RTL Schematic

97

Synthesis Report

98

===================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : fif.ngrTop Level Output File Name : fifOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NODesign Statistics# IOs : 26Macro Statistics :# Registers : 10# 3-bit register : 2# 9-bit register : 8# Multiplexers : 3# 2-to-1 multiplexer : 2# 9-bit 8-to-1 multiplexer : 1# Tristates : 1# 9-bit tristate buffer : 1# Decoders : 1# 1-of-8 decoder : 1Cell Usage :# BELS : 81# LUT1 : 1# LUT2 : 5# LUT3 : 37# LUT3_L : 1# LUT4 : 7# LUT4_L : 3# MUXF5 : 18# MUXF6 : 9# FlipFlops/Latches : 79# FDCE : 79# Clock Buffers : 1# BUFGP : 1# IO Buffers : 25# IBUF : 16# OBUFT : 9===================================================================Device utilization summary:---------------------------Selected Device : 2s200pq208-5 Number of Slices: 66 out of 2352 2% Number of Slice Flip Flops: 79 out of 4704 1% Number of 4 input LUTs: 54 out of 4704 1% Number of bonded IOBs: 25 out of 144 17% Number of GCLKs: 1 out of 4 25% ===================================================================

99

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 79 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 7.251ns (Maximum Frequency: 137.912MHz) Minimum input arrival time before clock: 6.633ns Maximum output required time after clock: 13.403ns Maximum combinational path delay: 10.570ns

Timing Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'Delay: 7.251ns (Levels of Logic = 1) Source: wrptr_0 (FF) Destination: fifo_5_8 (FF) Source Clock: clk rising Destination Clock: clk rising

Data Path: wrptr_0 to fifo_5_8 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE:C->Q 11 1.292 2.300 wrptr_0 (wrptr_0) LUT4:I0->O 9 0.653 2.120 _n00341 (_n0034) FDCE:CE 0.886 fifo_0_0 ---------------------------------------- Total 7.251ns (2.831ns logic, 4.420ns route) (39.0% logic, 61.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Offset: 6.633ns (Levels of Logic = 2) Source: wr (PAD) Destination: fifo_5_8 (FF) Destination Clock: clk rising Data Path: wr to fifo_5_8 Gate Net

100

Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 8 0.924 2.050 wr_IBUF (wr_IBUF) LUT4:I3->O 9 0.653 2.120 _n00341 (_n0034) FDCE:CE 0.886 fifo_0_0 ---------------------------------------- Total 6.633ns (2.463ns logic, 4.170ns route) (37.1% logic, 62.9% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset: 13.403ns (Levels of Logic = 4) Source: rdptr_0_1 (FF) Destination: data_out<8> (PAD) Source Clock: clk rising Data Path: rdptr_0_1 to data_out<8> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCE:C->Q 36 1.292 4.000 rdptr_0_1 (rdptr_0_1) LUT3:I0->O 1 0.653 0.000 Mmux_dmuxout_inst_lut3_81 (Mmux_dmuxout__net0) MUXF5:I0->O 1 0.375 0.000 Mmux_dmuxout_inst_mux_f5_0 (Mmux_dmuxout__net2) MUXF6:I0->O 1 0.376 1.150 Mmux_dmuxout_inst_mux_f6_0 (dmuxout<0>) OBUFT:I->O 5.557 data_out_0_OBUFT (data_out<0>) ---------------------------------------- Total 13.403ns (8.253ns logic, 5.150ns route) (61.6% logic, 38.4% route)-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 10.570ns (Levels of Logic = 3) Source: rd (PAD) Destination: data_out<8> (PAD)

Data Path: rd to data_out<8> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.924 1.150 rd_IBUF (rd_IBUF) LUT1:I0->O 9 0.653 2.120 I12_EnableTr_INV1 (I12_N128) OBUFT:T->O 5.723 data_out_1_OBUFT (data_out<1>) ---------------------------------------- Total 10.570ns (7.300ns logic, 3.270ns route) (69.1% logic, 30.9% route)===================================================================CPU : 4.63 / 6.89 s | Elapsed : 4.00 / 5.00 s--> Total memory usage is 59068 kilobytes

Test Bench Report

101

-- VHDL Test Bench Created from source file fif.vhd -- 22:58:21 10/06/2007-- Notes: -- This testbench has been automatically generated using types std_logic and-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY testbench ISEND testbench;

ARCHITECTURE behavior OF testbench IS COMPONENT fifPORT(

clk : IN std_logic;rst : IN std_logic;rd : IN std_logic;wr : IN std_logic;rdinc : IN std_logic;wrinc : IN std_logic;rdptrclr : IN std_logic;wrptrclr : IN std_logic;data_in : IN std_logic_vector(8 downto 0); data_out : OUT std_logic_vector(8 downto 0));

END COMPONENT;SIGNAL clk : std_logic;SIGNAL rst : std_logic;SIGNAL rd : std_logic;SIGNAL wr : std_logic;SIGNAL rdinc : std_logic;SIGNAL wrinc : std_logic;SIGNAL rdptrclr : std_logic;SIGNAL wrptrclr : std_logic;SIGNAL data_in : std_logic_vector(8 downto 0);SIGNAL data_out : std_logic_vector(8 downto 0);

BEGINuut: fif PORT MAP(

clk => clk,rst => rst,rd => rd,wr => wr,rdinc => rdinc,wrinc => wrinc,rdptrclr => rdptrclr,wrptrclr => wrptrclr,

102

data_in => data_in,data_out => data_out

); tb : PROCESS BEGIN

clk<=transport'0';rst<=transport'0';rd<=transport'1';wr<=transport'1';rdinc<=transport'1';wrinc<=transport'1';rdptrclr<=transport'0';wrptrclr<=transport'0';data_in<=transport"000011001";wait for 100 ns;clk<=transport'1';rst<=transport'0';rd<=transport'1';wr<=transport'1';rdinc<=transport'0';wrinc<=transport'0';rdptrclr<=transport'0';wrptrclr<=transport'0';data_in<=transport"000011001";wait for 100 ns;clk<=transport'1';rst<=transport'0';rd<=transport'1';wr<=transport'1';rdinc<=transport'1';wrinc<=transport'1';rdptrclr<=transport'0';wrptrclr<=transport'0';data_in<=transport"000011001"; wait; -- will wait forever

END PROCESS;

END;

Name : - Amritesh Kumar

103

Batch : - A1

Output Waveform

Experiment No :05

104

BIDIRECTIONAL BUFFER

PROBLEM STATEMENT :

To design implement and verify Bidirectional Buffer using VHDL.

THEORY :

Data with multiple sources that need to be connected to one or more destination points in a circuit may be implemented using either multiplexer or tri-state buffers. Tri state buffers are modeled using any of the following statements. If statement Case statement, Conditional signal assignment.

A tri-state buffer is inferred by assigning a high impedance value (z) to a data object in a particular branch of multi-branch statement. The main point to note about modeling tri-state buffer is that multiple buffers that are connected to the same output must be modeled in separate concurrent statements.

105

Different models of the same circuit are shown below. It consists of tri-state buffer whose outputs are connected together. The operation is such that only one of the mode is available at any given time.

AU BU AU BU

AL BL AL BL

AU BU AU BU

AL BL AL BL

AU BU AU BU

AL BL AL BL

AU BU AU BU

AL BL AL BL

CONCLUSION :

The Bidirectional Buffer was designed, implemented and verified using VHDL.

Name : - Amritesh Kumar

106

Batch : - A1Bidirectional Buffer

Codelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity bi is Port ( au : inout std_logic_vector(3 downto 0); al : inout std_logic_vector(3 downto 0); bu : inout std_logic_vector(3 downto 0); bl : inout std_logic_vector(3 downto 0); reset : in std_logic; mode : in std_logic_vector(1 downto 0));end bi;

architecture Behavioral of bi is signal s0,s1,s2,s3:std_logic_vector (3 downto 0); begin process(reset,au,al,bu,bl)

begin s0<=au; s1<=al; s2<=bu; s3<=bl;

if (reset='1') thens0<="0000";s0<="0000";s0<="0000";s0<="0000"; end if; end process; bu<=s0 when mode="00" or mode ="10" else "ZZZZ"; bl<=s1 when mode="00" or mode ="11" else "ZZZZ"; au<=s2 when mode="01" or mode ="11" else "ZZZZ"; al<=s3 when mode="01" or mode ="10" else "ZZZZ";

end Behavioral;

RTL Schematic107

Synthesis Report

108

===================================================================* Final Report *===================================================================Final ResultsRTL Top Level Output File Name : bi.ngrTop Level Output File Name : biOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NO


Macro Statistics :# Tristates : 4# 4-bit tristate buffer : 4

Cell Usage :# BELS : 7# LUT1 : 1# LUT2 : 6# IO Buffers : 19# IBUF : 3# IOBUF : 16===================================================================Device utilization summary:---------------------------



=========================================================================TIMING REPORT



Timing Summary:

109

---------------Speed Grade: -5

Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 10.850ns


-------------------------------------------------------------------------Timing constraint: Default path analysisDelay: 10.850ns (Levels of Logic = 3) Source: mode<0> (PAD) Destination: al<0> (PAD)

Data Path: mode<0> to al<0> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 7 0.924 1.950 mode_0_IBUF (mode_0_IBUF) LUT1:I0->O 4 0.653 1.600 I2_EnableTr_INV1 (I2_N35) IOBUF:T->IO 5.723 au_2_IOBUF (au<2>) ---------------------------------------- Total 10.850ns (7.300ns logic, 3.550ns route) (67.3% logic, 32.7% route)

=========================================================================CPU : 4.91 / 5.89 s | Elapsed : 5.00 / 6.00 s -->


Test Bench Report

110

-- VHDL Test Bench Created from source file bi.vhd -- 19:41:56 08/21/2008-- Notes: -- This testbench has been automatically generated using types std_logic and-- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model.--LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;

ENTITY bi_B2_vhd_tb ISEND bi_B2_vhd_tb;

ARCHITECTURE behavior OF bi_B2_vhd_tb IS

COMPONENT biPORT(

reset : IN std_logic;mode : IN std_logic_vector(1 downto 0); au : INOUT std_logic_vector(3 downto 0);al : INOUT std_logic_vector(3 downto 0);bu : INOUT std_logic_vector(3 downto 0);bl : INOUT std_logic_vector(3 downto 0));

END COMPONENT;

SIGNAL au : std_logic_vector(3 downto 0);SIGNAL al : std_logic_vector(3 downto 0);SIGNAL bu : std_logic_vector(3 downto 0);SIGNAL bl : std_logic_vector(3 downto 0);SIGNAL reset : std_logic;SIGNAL mode : std_logic_vector(1 downto 0);

BEGIN

uut: bi PORT MAP(au => au,al => al,bu => bu,bl => bl,reset => reset,mode => mode

);

tb : PROCESS

111

BEGIN -- --------------------

reset <= transport '1';mode <= transport std_logic_vector'("00"); --0al <= transport std_logic_vector'("1101"); --D-- --------------------WAIT FOR 50 ns; -- Time=50 ns

-- --------------------WAIT FOR 50 ns; -- Time=100 nsreset <= transport '0';al <= transport std_logic_vector'("0010"); --2-- --------------------WAIT FOR 50 ns; -- Time=150 ns

-- --------------------WAIT FOR 50 ns; -- Time=200 nsal <= transport std_logic_vector'("1100"); --C-- --------------------WAIT FOR 50 ns; -- Time=250 ns

-- --------------------WAIT FOR 50 ns; -- Time=300 nsal <= transport std_logic_vector'("1110"); --E-- --------------------WAIT FOR 450 ns; -- Time=750 ns-- --------------------

wait; -- will wait forever END PROCESS;

END;

112

Output Waveform

Experiment No : 06113

CMOS INVERTER

PROBLEM STATEMENT :

To design and verify a CMOS INVERTER Logic gate using Microwind.

THEORY :

Inverter is probably the most important basic logic cell in circuit design. As the truth table of inverter shows, the cell inverts the logic value of input into output.

In the truth table the symbol ‘0’ represents the 0.0V, while ‘1’ represents the logic supply, which is 12V in 0.12 micrometer. The symbol ‘X’ means ‘undefined’. This state is equivalent to an undefined voltage just like floating input mode without any input connector.

The CMOS inverter design shown in figure, are P-channel MOS transistor, used as switches. When the input signal is logic ‘0’, the NMOS is switched off while the PMOS passes VDD through the output which turns to 1, when the input signal is logic ‘1’, the PMOS is switched off, while NMOS passes VSS to the output, which goes back to 0.

NAND gate

Input Output

0 1

1 0

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CMOS INVERTER

VDD

VSS

CONCLUSION :

The CMOS INVERTER Logic gate was designed and verified using Microwind.

INVERTER USING CMOS

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OUTPUT

Inverter using components

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Experiment No : 07

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CMOS NAND & NOR GATES

PROBLEM STATEMENT :

To design and verify two input CMOS NAND & NOR Logic gates using Microwind.

THEORY :

NMOS & PMOS are together used to form CMOS logic.

CMOS NAND & NOR Logic gates : Both NAND & NOR Logic gates can be constructed using CMOS. A s-input gate uses, s p-channel and s n-channel transistors.

Two input CMOS NAND GATE :

In a NAND GATE, if either or both input is low, the output Z has a low impedance connection to VDD through the corresponding ON p-channel transistor and the path to ground is blocked by the corresponding OFF n-channel transistor. If both inputs are high, the path to VDD is blocked and Z has a low impedance connection to ground.

NAND gate

Input 1 Input 2 Output

0 0 1

0 1 1

1 0 1

1 1 0

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Two input CMOS NOR GATE :

In a NAND GATE, if both inputs are low or high, the output Z has a low impedance connection to VDD through the corresponding ON p-channel transistor and the path to ground is blocked by the corresponding OFF n-channel transistor. If either of the inputs is high, then the path to VDD is blocked and Z has a low impedance connection to ground.

NOR gate

Input 1 Input 2 Output

0 0 1

0 1 0

1 0 0

1 1 0

NOTE :

CMOS NAND & NOR, do not have identical performance. For a given Si area, an n-channel transistor has lower ON resistance than a p-channel transistor. Hence, when connected in series, ‘s’ no. of n-channel transistors have lower ON resistance than p-channel. Thus, NAND GATE is generally faster than the NOR GATE.

A logic inversion comes for free, but for non-inv gates the number of transistors is typically more.

CONCLUSION :

The two input CMOS NAND & NOR Logic gates were designed and verified using Microwind.

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Two input CMOS NAND GATE

VDD

VSS

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Two input CMOS NOR GATE

VDD

VSS

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NAND USING CMOS

OUTPUT

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NAND using components

Output

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NOR USING CMOS

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OUTPUT

NOR using components

Output

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Experiment No : 08

COMBINATIONAL CIRCUIT

PROBLEM STATEMENT :

To design combinational logic circuit using Microwind.

THEORY :

Basically digital circuits are divided into two categories.

1. Combinational circuits.2. Sequential circuit.

In combinational ckt. the output at any instant of time depends upon the inputs present at that instant of time. This means there is no memory in there circuit. The design requirements of combinational circuit may be specified in one of the following way.

1. A set of statements.

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2. Boolean expression.3. Truth table.

Here we have designed a combinational circuit using N-mos & P-mos.P-mos logic is at the pull up part because pmos gives good (logic 1) condition. While pull down part is of N-mos because it gives good (logic 0).When all inputs are zeros all n switches are closed & output is directly connected to VSS. When all inputs are ones all p switches are closed & output is connected to VDD.CONCLUSION :A combinational logic circuit was designed and verified using Microwind.

CIRCUIT FOR EQUATION :- A+B(C+D)

OUTPUT WAVEFORM127

final vlsi pract 08

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