general description features - maxim integrated · vdd dynamic current idd vdd = +5v, fclk = 5mhz,...

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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16-Channel, Linear, High-Voltage Analog Switches

19-5786; Rev 2; 1/12

Ordering Information/Selector Guide

General DescriptionThe MAX4968/MAX4968A are 16-channel, high-linearity, high-voltage, bidirectional SPST analog switches with 18I (typ) on-resistance. The devices are ideal for use in applications requiring high-voltage switching controlled by a low-voltage control signal, such as ultrasound imag-ing and printers. The MAX4968A provides integrated 40kI (typ) bleed resistors on each switch terminal to discharge capacitive loads. Using HVCMOS technol-ogy, these switches combine high-voltage bilateral MOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals.

The MAX4968 is pin-to-pin compatible with the MAX14802 and Supertex HV2601. The MAX4968A is pin-to-pin compatible with the MAX14803 and Supertex HV2701. The only difference is the VPP positive supply voltage level. The MAX4968/MAX4968A require a low +10V (typ) voltage (VPP), whereas the MAX14802/MAX14803 and HV2601/HV2701 require a high +100V supply voltage.

In a typical ultrasound application, these devices do not require a dedicated high-voltage supply that implies a sig-nificant simplification of system requirement. The negative voltage supply can be shared with the transmitter, and the positive voltage supply is typically +10V.

The devices are available in the 48-pin LQFP package and are specified over the -40NC to +85NC extended temperature range.

ApplicationsMedical Ultrasound Imaging

Nondestructive Testing (NDT)/Industrial Ultrasound Imaging

Printers

FeaturesS Latch Free

SOI HVCMOS Process Technology for High Performance and Robustness

S No Dedicated High-Voltage Supplies Required

S RON Flatness Guaranteed in Entire Input Range

S Low-Power Dissipation

S Low-Charge Injection and Voltage Spike

S 25MHz Serial Interface (+2.5V to +5V)

S 2nd Harmonic Distortion < -45dB at 2MHz ± 90V Pulse

S Low Parasitic Capacitance Guarantees High Bandwidth

S DC to 30MHz Small-Signal Analog Bandwidth (CLOAD = 200pF)

S 500kHz to 20MHz High-Signal Analog Bandwidth (CLOAD = 200pF)

S Extended Input Range Up to 210VP-P

S -80dB (typ) Off-Isolation at 5MHz (50I)

S Shunt (Bleed) Resistors on Outputs (MAX4968A Only)

S Daisy-Chainable Serial Interface

+Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE SWITCH CHANNELS BLEED RESISTOR PIN-PACKAGE

MAX4968ECM+ -40°C to +85°C 16 No 48 LQFP

MAX4968AECM+ -40°C to +85°C 16 Yes 48 LQFP

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Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(All voltages referenced to GND.)VDD Logic Supply Voltage Range ..........................-0.3V to +6VVPP - VNN Supply Voltage ................................................ +212VVPP Supply Voltage Range ...................................-0.3V to +12VVNN Negative Supply Voltage ............................................-200VLogic Input Voltage Range (CLK, DIN, CLR) .........-0.3V to +6VLogic Input Voltage Range

(LE) ........................-0.3V to a minimum of (VPP + 0.3V) or 6VLogic Output Voltage Range (DOUT) ...... -0.3V to (VDD + 0.3V)

Analog Signal Range (SW_) ........ (VNN - 0.3V) to (VNN + 220V)Continuous Power Dissipation (TA = +70NC)

LQFP (derate 22.7mW/NC above +70NC) .................1818mWOperating Temperature Range .......................... -40NC to +85NCStorage Temperature Range ............................ -65NC to +150NCJunction Temperature ................................................... +150NCLead Temperature (soldering, 10s) ................................+300NCSoldering Temperature (reflow) ......................................+260NC

ELECTRICAL CHARACTERISTICS(VDD = +2.37V to +5.5V, VPP = +10V Q5%, VNN = 0 to -200V, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +3.3V, VNN = -100V, VPP = +10V at TA = +25NC.) (Note 2)

ABSOLUTE MAXIMUM RATINGS

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

PACKAGE THERMAL CHARACTERISTICS (Note 1)LQFP

Junction-to-Ambient Thermal Resistance (qJA) ..........44°C/W Junction-to-Case Thermal Resistance (qJC) ...............10°C/W

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES

VDD Logic Supply Voltage VDD +2.37 +5.5 V

VNN Supply Voltage VNN -200 0 V

VPP Supply Voltage VPP +9.5 +10 +10.5 V

VDD Static Current IDDS 4 FA

VDD Dynamic Current IDD VDD = +5V, fCLK = 5MHz, fDIN = 2.5MHz 200 FA

VNN Static Current INNS All switches remain on or off, SW_ = GND 10 25 FA

VNN Supply Dynamic Current(All Channels Switching Simultaneously)

INNVPP = +10V, VNN = -100V,fTURN_ON/OFF = 50kHz, SW_ = GND

3.3 5 mA

VPP Supply Static Current IPPS All switches remain on or off, SW_ = GND 12 25 FA

VPP Supply Dynamic Current(All Channels Switching Simultaneously)

IPPVPP = +10V, VNN = -100V,fTURN_ON/OFF = 50kHz, SW_ = GND

4 6 mA

SWITCH CHARACTERISTICS

Analog Dynamic Signal Range VSW_ AC operation only, f > 500kHz VNNVNN +

210V

Small-Signal On-Resistance RONSVPP = +10V, VNN = -100V, VSW_ = 0V, ISW_ = 5mA

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ELECTRICAL CHARACTERISTICS (continued)(VDD = +2.37V to +5.5V, VPP = +10V Q5%, VNN = 0 to -200V, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +3.3V, VNN = -100V, VPP = +10V at TA = +25NC.) (Note 2)


Small-Signal On-Resistance Matching

DRONS VPP = +10V, VNN = -100V, ISW_ = 5mA 3 %

Small-Signal On-Resistance Flatness

RONF

AC measured, fSW_ = 0.5MHz, VSW_ = 80VP-P, RLOAD = 50I, VPP = +10V, VNN = -100V

2 %

Switch Output Bleed Resistor RINT MAX4968A only 30 40 50 kI

Switch-Off Leakage ISW_(OFF) VSW_ = 0V, switch off (MAX4968 only) 0 1 FA

Switch-Off DC Offset No load (MAX4968A only) -15 0 +15 mV

Switch-On DC Offset No load (MAX4968A only) -15 0 +15 mV

Switch Output Isolation Diode Current

300ns pulse width, 2% duty cycle 3.0 A

SWITCH DYNAMIC CHARACTERISITICS

Turn-On Time tONVSW_A = +1V, RL = 100I, VNN = -100V, from enable to VSW_B = +0.9V

2 5 Fs

Turn-Off Time tOFFVSW_A = +1V, RL = 100I, VNN = -100V, from disable to VSW_B = +0.9V

2 3.5 Fs

Maximum VSW_ Slew Rate dV/dt CL = 100pF 20 V/ns

Off-Isolation VISO f = 2MHz, RL = 50I -76 dB

Crosstalk VCT f = 5MHz, RL = 50I -76 dB

SW_ Off-Capacitance CSW_(OFF) f = 1MHz, small signal close to zero 9 pF

SW_ On-Capacitance CSW_ (ON) f = 1MHz, small signal close to zero 13 pF

Output Voltage Spike VSPK RL = 50I ±70 mV

Large-Signal Analog Bandwidth (-3dB)

fBW_LCLOAD = 200pF, 60V amplitude sinusoidal burst, 1% duty cycle

30 MHz

Small-Signal Analog Bandwidth (-3dB)

fBW_SCLOAD = 200pF, 100mV amplitude sinusoidal

50 MHz

Charge Injection Q VPP = +10V, VNN = -100V, Figure 1 150 pC

LOGIC LEVELS

Logic-Input Low Voltage VIL 0.75 V

Logic-Input High Voltage VIHVDD - 0.75

V

Logic-Output Low Voltage VOL ISINK = 1mA 0.4 V

Logic-Output High Voltage VOH ISOURCE = 1mAVDD -

0.4V

Logic-Input Capacitance CIN 5 pF

Logic-Input Leakage IIN -1 +1 FA

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ELECTRICAL CHARACTERISTICS (continued)(VDD = +2.37V to +5.5V, VPP = +10V Q5%, VNN = 0 to -200V, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +3.3V, VNN = -100V, VPP = +10V at TA = +25NC.) (Note 2)

Note 2: All devices are 100% tested at TA = +85NC. Limits over the operating temperature range are guaranteed by design.


TIMING CHARACTERISTICS (Figure 2)

CLK Frequency fCLK 25 MHz

DIN to CLK Setup Time tDS 8 ns

DIN to CLK Hold Time tDH 3 ns

CLK to LE Setup Time tCS 8 ns

LE Low Pulse Width tWL 12 ns

CLR High Pulse Width tWC 12 ns

CLK Rise and Fall Times tR, tF 50 ns

CLK to DOUT Delay tDOVDD = +5V Q10%, CDOUT = 15pF 28

nsVDD = +2.5V Q5%, CDOUT = 15pF 45

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Test Circuits/Timing Diagrams

Figure 1. Test Circuits

SW_B

VDD 5V

A

ILEAK

SW_A

VPPVPP

A

ILEAK

MAX4968MAX4968A

GND

SWITCH-OFF LEAKAGE

VNNVNN

SW_B

VOUT

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GND

DC OFFSET ON/OFF

VNNVNN

RL100kΩ

tON/tOFF TEST CIRCUIT

SW_B

VOUT

VPP - 10V

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GNDVNNVNN

RL100kΩ

SW_B

VIN = 10VP-PAT 5MHz

VOUT

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GND

OFF-ISOLATION

VNNVNN

RL

VISO = 20logVOUT

VIN

ISOLATION DIODECURRENT

VNNSW_B

VOUT

VDD 5V

SW_A

IID

VPPVPP

MAX4968MAX4968A

GNDVNNVNN

SW_B

VIN = 10VP-PAT 5MHz

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GND

CROSSTALK

VNNVNN

50Ω

SW_B

SW_A50Ω

VCT = 20logVOUT

VIN

Q = 1000pF x VOUTCHARGE INJECTION

SW_B

VOUT

VOUT

100pF

VCOM_

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GNDVNNVNN

OUTPUT VOLTAGE SPIKE

SW_B

VOUT

+VSPK

-VSPK

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GNDVNNVNN

50Ω

RL1kΩ

SW_B

200pF10mVP-P

VOUTVIN

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GND

SMALL-SIGNALBANDWIDTH MEASUREMENT

VNNVNN

SW_B

200pF60VP-P BURST(1% DUTY CYCLE)

VOUTVIN

VDD 5V

SW_A

VPPVPP

MAX4968MAX4968A

GND

LARGE-SIGNALBANDWIDTH MEASUREMENT

VNNVNN

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Figure 2. Serial Interface Timing

Figure 3. Latch-Enable Interface Timing

Test Circuits/Timing Diagrams (continued)

DIN DN+1 DN-1DN50%

50% 50%

50%

50%50%

50%

90%

10%

50%

tCS

tWL

tDS tDH

tDO

tOFF

tWC

tON

50%

LE

CLK

DOUT

OFF

ON

SWITCH

CLR

DIN

DATA FROM PREVIOUS DATA BYTEPOWER-UP DEFAULT: D[15:0] = 0

D15

D15

D14 D13

D14 D13

D1 D0

D1 D0 D15

LSBMSB

LE

CLK

DOUT

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Typical Operating Characteristics(VDD = +3V, VPP = +10V, VNN = -100V, RL = 100I, CL = 100pF, TA = +25NC, unless otherwise noted.)

TURN-ON/TURN-OFF TIMEvs.TEMPERATURE

MAX

4968

toc0

1

TEMPERATURE (°C)

TURN

-ON/

TURN

-OFF

TIM

E (µ

s)

603510-15

1

2

3

4

5

0-40 85

tON tOFF

OFF-ISOLATION vs. FREQUENCY

MAX

4968

toc0

2

FREQUENCY (MHz)

OFF-

ISOL

ATIO

N (d

B)

1010.10.01

-80

-60

-40

-20

0

-1000.001 100

TA = -40°C

TA = +25°CTA = +85°C

SWITCH-OFF LEAKAGE CURRENTvs.TEMPERATURE

MAX

4968

toc0

3

TEMPERATURE (°C)

SWIT

CH-O

FF L

EAKA

GE C

URRE

NT (µ

A)

603510-15

0.2

0.4

0.6

0.8

1.0

0-40 85

ISW_(0FF)

HIGH-VOLTAGE SUPPLY CURRENTvs. OUTPUT SWITCH FREQUENCY

MAX

4968

toc0

7

OUTPUT SWITCH FREQUENCY (kHz)

SUPP

LY C

URRE

NT (m

A)

40302010

2

4

6

8

10

00 85

ALL SWITCHES SWITCHING

IPP (TA = +85°C)

IPP (TA = +25°C)

IPP (TA = -40°C)

INN (TA = +85°C)

INN (TA = -40°C)

INN (TA = +25°C)

LOGIC POWER-SUPPLY CURRENTvs. SERIAL-CLOCK FREQUENCY

MAX

4968

toc0

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SERIAL-CLOCK FREQUENCY(MHz)

LOGI

C PO

WER

-SUP

PLY

CURR

ENT

(µA)

18161412108642

100

200

300

400

500

00 20

TA = +85°C

TA = +25°C

TA = +-40°C

POSITIVE AND NEGATIVE POWER-SUPPLYCURRENT vs. TEMPERATURE

MAX

4968

toc0

5

TEMPERATURE (°C)

SUPP

LY C

URRE

NT (µ

A)

603510-15

10

12

14

16

18

20

8-40 85

VPP = +10V

VNN = -100V

VNN = -70VVNN = -40V

LOGIC POWER-SUPPLY CURRENT vs.SUPPLY VOLTAGE

MAX

4968

toc0

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VDD SUPPLY VOLTAGE (V)

LOGI

C PO

WER

-SUP

PLY

CURR

ENT

(µA)

5.14.74.33.93.53.12.7

0.5

1.0

1.5

2.0

2.5

3.0

02.3 5.5

TA = -40°C

TA = +25°C

TA = +85°C

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Pin Configuration

Pin Description

TOP VIEW

LQFP(7mm × 7mm)

+13

14

15

16

17

18

19

20

21

22

23

24

VNN

N.C.

VPP

N.C.

GND

VDD

DIN

CLK

LE

CLR

DOUT

N.C.

48

47

46

45

44

43

42

41

40

39

38

37

1 2 3 4 5 6 7 8 9 10 11 12

SW5A

SW5B

SW6A

SW6B

SW7A

SW7B

SW8A

SW8B

SW9A

SW9B

SW10A

SW10B

SW0A

SW0B

SW1A

SW1B

SW2A

SW2B

SW3A

SW3B

SW4A

SW4B

N.C.

N.C.

36 35 34 33 32 31 30 29 28 27 26 25

SW15

B

SW15

A

SW14

B

SW14

A

SW13

B

SW13

A

SW12

B

SW12

A

SW11

B

SW11

A

N.C.

N.C.

MAX4968MAX4968A

PIN NAME FUNCTION

1, 2, 14, 16, 24, 35, 36

N.C.No Connection. Not connected internally.

3 SW4B Analog Switch 4—Terminal

4 SW4A Analog Switch 4—Terminal





9 SW1B Analog Switch 1 —Terminal




13 VNN

Negative High-Voltage Supply. Bypass VNN to GND with a 0.1FF or greater ceramic capacitor.

PIN NAME FUNCTION

15 VPP

Positive Voltage Supply. Bypass VPP to GND with a 0.1FF or greater ceramic capacitor.

17 GND Ground

18 VDD

Logic Supply Voltage. Bypass VDD to GND with a 0.1FF or greater ceramic capacitor.

19 DIN Serial-Data Input

20 CLK Serial-Clock Input

21 LE Active-Low Latch-Enable Input

22 CLR Latch-Clear Input

23 DOUT Serial-Data Output




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Detailed DescriptionThe MAX4968/MAX4968A are 16-channel, high-linearity, high-voltage, bidirectional SPST analog switches with 18I (typ) on-resistance. The devices are ideal for use in applications requiring high-voltage switching controlled by a low-voltage control signal, such as ultrasound imag-ing and printers. The MAX4968A provides integrated 40kI (typ) bleed resistors on each switch terminal to discharge capacitive loads. Using HVCMOS technol-ogy, these switches combine high-voltage, bilateral MOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals.

The MAX4968 is pin-to-pin compatible with the MAX14802 and Supertex HV2601. The MAX4968A is pin-to-pin compatible with the MAX14803 and Supertex HV2701. The only difference is the VPP positive supply voltage level. The MAX4968/MAX4968A require a low +10V (typ) voltage (VPP), whereas the MAX14802/MAX14803 and HV2601/HV2701 require a high +100V supply voltage.

In typical ultrasound applications, these devices do not require dedicated high-voltage supply, which implies a significant simplification of system requirement. The negative voltage supply can be shared with the transmit-ter and the positive voltage supply is typically +10V.

Analog SwitchThe devices can transmit analog signals up to 210VP-P, with an analog signal range from VNN to VNN + 210V. Before starting the high-voltage burst transmission (VP-P > +20V), the input voltage is required to be close to GND to allow a proper settling of the pass FET. The high-voltage burst frequency must be greater than 500kHz.

Extremely long high-voltage bursts (VP-P > +10V) with duty cycle greater than 20% could result in signal deg-radation, especially for unipolar transmission. In general, this applies for burst transmission with a nonzero DC content.

Low-voltage signal (VP-P < 10V) continuous-wave bipo-lar transmission is supported for frequencies greater than 500kHz. For very small signals, such as the small echoes in typical ultrasound imaging systems (VP-P < 10V), the devices are not limited to a low-frequency bandwidth and can transmit DC signals.

Voltage SuppliesThe devices operate with a high-voltage supply VNN from -200V to 0, VPP supply of +10V (typ), and a logic supply VDD (+2.37V to +5.5V).

Pin Description (continued)

PIN NAME FUNCTION











PIN NAME FUNCTION










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Bleed Resistors (MAX4968A)The MAX4968A features integrated 40kI (typ) bleed resistors to discharge capacitive loads such as piezo-electric transducers. Each analog switch terminal is con-nected to GND with a bleed resistor.

Serial InterfaceThe MAX4968/MAX4968A are controlled by a serial interface with a 16-bit serial shift register and transparent latch. Each of the 16 data bits controls a single analog switch (see Table 1). Data on DIN is clocked with the most significant bit (MSB) first into the shift register on the rising edge of CLK. Data is clocked out of the shift register onto DOUT on the rising edge of CLK. DOUT reflects the status of DIN, delayed by 16 clock cycles (see Figures 2 and 3).

Latch Enable (LE)Drive LE logic-low to change the contents of the latch and update the state of the high-voltage switches

(Figure 3). Drive LE logic-high to freeze the contents of the latch and prevent changes to the switch states. To reduce noise due to clock feedthrough, drive LE logic-high while data is clocked into the shift register. After the data shift register is loaded with valid data, pulse LE logic-low to load the contents of the shift register into the latch.

Latch Clear (CLR)The MAX4968/MAX4968A feature a latch-clear input. Drive CLR logic-high to reset the contents of the latch to zero and open all switches. CLR does not affect the contents of the data shift register. Pulse LE logic-low to reload the contents of the shift register into the latch.

Power-On ResetThe MAX4968/MAX4968A feature a power-on-reset cir-cuit to ensure all switches are open at power-on. The internal 16-bit serial shift register and latch are set to zero on power-up.

Table 1. Serial Interface Programming (Notes 1–6)

DATA BITSCONTROL

BITSFUNCTION

D0(LSB)

D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

X X X X X X X X H L Hold Previous State

X X X X X X X X X H Off Off Off Off Off Off Off Off

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Table 1. Serial Interface Programming (Notes 1–6) (continued)

Note 1: The 16 switches operate independently.Note 2: Serial data is clocked in on the rising edge of CLK.Note 3: The switches go to a state retaining their present condition on the rising edge of LE. When LE is low, the shift register data

flows through the latch.Note 4: DOUT is high when switch 15 is on.Note 5: Shift register clocking has no effect on the switch states if LE is high.Note 6: The CLR input overrides all other inputs.

Applications InformationIn typical ultrasound applications, the MAX4968/MAX4968A do not require dedicated high-voltage supplies; the nega-tive voltage supply can be shared with the transmitter and the positive voltage supply is typically +10V. See Figures 5, 6, and 7 for medical ultrasound applications.

Logic LevelsThe MAX4968/MAX4968A digital interface inputs CLK, DIN, LE, and CLR operate on the VDD logic supply voltage.

Daisy-Chaining Multiple DevicesDigital output DOUT is provided to allow the connec-tion of multiple MAX4968/MAX4968A devices by daisy-

chaining (Figure 4). Connect each DOUT to the DIN of the subsequent device in the chain. Connect CLK, LE, and CLR inputs of all devices, and drive LE logic-low to update all devices simultaneously. Drive CLR high to open all the switches simultaneously. Additional shift registers can be included anywhere in series with the MAX4968/MAX4968A daisy-chain.

Supply Sequencing and BypassingThe MAX4968/MAX4968A do not require special sequencing of the VDD, VPP, and VNN supply voltages. Bypass VDD, VPP, and VNN to GND with a 0.1FF ceramic capacitor as close as possible to the device.

Note: Keep LE low during power-up.

DATA BITSCONTROL

BITSFUNCTION

D8 D9 D10 D11 D12 D13 D14D15

(MSB) LE CLR SW8 SW9 SW10 SW11 SW12 SW13 SW14 SW15

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

L L L Off

H L L On

X X X X X X X X H L Hold Previous State

X X X X X X X X X H Off Off Off Off Off Off Off Off

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Application Diagrams

Figure 4. Interfacing Multiple Devices by Daisy-Chaining

CLK

DIN

CLK

LE

CLR

U10 U11 U1n

U20 U21 U2n

DOUTDIN1

LE

CLR

DIN2 DIN

CLK

LE

CLR

DOUT DIN

CLK

LE

CLR

DOUT DIN

CLK

LE

CLR

DOUT

DIN

CLK

LE

CLR

DOUT DIN

CLK

LE

CLR

DOUT

MAX4968MAX4968A

MAX4968MAX4968A

MAX4968MAX4968A

MAX4968MAX4968A

MAX4968MAX4968A

MAX4968MAX4968A

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Application Diagrams (continued)

Figure 5. Medical Ultrasound Application—High-Voltage Analog Switches in Probe

HIGH-VOLTAGE TRANSMIT1 PER CHANNEL

PROBE SELECTION2 TO 4 PROBES

RELAY1 RELAY/CH/PROBE

CABLE1 PER CHANNEL

TRANSDUCERS2 TO 4 PER CHANNEL

HIGH-VOLTAGE ANALOGSWITCHES

2 TO 4 PER CHANNEL

±100V MAX ±1 TO 2A MAX

MAINFRAME

+V

-V

PROBES

±1V MAX

10mA TYP

HIGH-VOLTAGEISOLATION

LOW-VOLTAGE RECEIVE64 TO 128 CHANNELS

PROBEB

PROBEA

PROBEC

PROBED

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Figure 6. Medical Ultrasound Application—High-Voltage Analog Switches in Mainframe

PROBEA

HIGH-VOLTAGETRANSMIT

1 PER CHANNEL


RELAYS2 TO 4 RELAYS/CH/PROBE

CABLE2 TO 4 PER CHANNEL


HIGH-VOLTAGE ANALOGSWITCHES

2 TO 4 PER CHANNEL±100V MAX ±1 TO 2A MAX

MAINFRAME

+V

-V

PROBES

±1V MAX

10mA TYP

HIGH-VOLTAGEISOLATION

LOW-VOLTAGE RECEIVE

64 TO 128 CHANNELS

PROBEB

PROBEC

PROBED

MA

X4

96

8/M

AX

49

68

A


15


Figure 7. Medical Ultrasound Application—Multiple Transmit and Isolation per Receiver Channel

PROBEA

HIGH-VOLTAGE TRANSMIT2 TO 4 PER CHANNEL

HIGH-VOLTAGEISOLATION ANDCHANNEL SELECT2 TO 4 PER CHANNEL

LOW-VOLTAGE RECEIVE64 TO 128 CHANNELS


RELAYS2 TO 4 RELAYS/CH/PROBE

CABLE2 TO 4 PER CHANNEL


±100V MAX ±1 TO 2A MAX

MAINFRAME

+V

-V

PROBES

±1V MAX

10mA TYP

PROBEB

PROBEC

PROBED

+V

-V

+V

-V

+V

-V

+V

-V

+V

-V

+V

-V

+V

-V

MA

X4

96

8/M

AX

49

68

A


16

Functional Diagram

Chip InformationPROCESS: BiCMOS

Package InformationFor the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

16-BITSHIFT

REGISTER

LATCH

VDD VPP

*BLEED RESISTORS AVAILABLE ON THE MAX4968A ONLY.

GND VNN

LEVELSHIFTER

CLR

SW0B

SW0AVNN

*

*

VNN

DIN

CLK

DOUT

LE

LATCHLEVEL

SHIFTER

SW15B

SW15AVNN

*

*

VNN

MAX4968MAX4968A

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

LAND PATTERN NO.

48 LQFP C48+6 21-0054 90-0093

http://pdfserv.maxim-ic.com/package_dwgs/21-0054.PDF

http://pdfserv.maxim-ic.com/land_patterns/90-0093.PDF

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 17

© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

MA

X4

96

8/M

AX

49

68

A


Revision History

REVISIONNUMBER

REVISIONDATE

DESCRIPTIONPAGES

CHANGED

0 3/11 Initial release —

1 5/11Removed future product asterisk from MAX4968 in Ordering Information, corrected Off-Isolation specification in Electrical Characteristics

1, 3

2 1/12Updated VNN specifications in Absolute Maximum Ratings and Electrical Characteristics supply voltage and VNN static current specifications

2, 3, 4, 9

general description features - maxim integrated · vdd dynamic current idd vdd = +5v, fclk = 5mhz,...

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