untitled document [] · to ic unless otherwise indicated, all limits are specified for vdd = +2.7v...

MCP601/602/603/6042.7V to 5.5V Single Supply CMOS Op Amps

FEATURES• Specifications rated from 2.7V to 5.5V supplies• Rail-to-rail swing at output• Common-mode input swing below ground• 2.8MHz GBWP• Unity gain stable• Low power IDD = 325µA max• Chip Select capability with MCP603• Industrial temperature range (-40°C to 85°C)• Available in single, dual and quad

APPLICATIONS• Portable Equipment• A/D Converter Driver• Photodiode Pre-amps• Analog Filters• Data Acquisition• Notebooks and PDAs• Sensor Interface

AVAILABLE TOOLS• Spice Macromodels (at www.microchip.com)• FilterLab™ Software (at www.microchip.com)

2000 Microchip Technology Inc.

DESCRIPTION

The Microchip Technology Inc. MCP601/602/603/604family of low power operational amplifiers are offered insingle (MCP601), single with a Chip Select pin feature(MCP603), dual (MCP602) and quad (MCP604) config-urations. These operational amplifiers (op amps) utilizean advanced CMOS technology, which provides lowbias current, high speed operation, high open-loop gainand rail-to-rail output swing. This product offering oper-

ates with a single supply voltage that can be as low as2.7V, while drawing less than 325µA of quiescent cur-rent. In addition, the common-mode input voltagerange goes 0.3V below ground, making these amplifi-ers ideal for single supply operation.

These devices are appropriate for low-power batteryoperated circuits due to the low quiescent current, forA/D Converter driver amplifiers because of their widebandwidth, or for anti-aliasing filters by virtue of theirlow input bias current.

The MCP601, MCP602 and MCP603 are available instandard 8-lead PDIP, SOIC and TSSOP packages.The MCP601 is also available in the SOT23-5 pack-age. The quad MCP604 is offered in 14-lead PDIP,SOIC and TSSOP packages. PDIP and SOIC pack-ages are fully specified from -40°C to +85°C with powersupplies from 2.7V to 5.5V.

TYPICAL APPLICATION

PACKAGES

MCP60X

VREF

VIN

VOUT

OUT

VSS

VDD-IN

+IN

2nd Order Low Pass Filter

Low Input Bias Current Over Temperature

Rail-to-Rail Output Swing

+IN

-IN

VSS

1

2

3

4

NC

+INA

-INA

VDD

-IND

+IND

1

2

3

4 VSS

OUTDOUTA 14

13

12

11

-INB

+INB

OUTB

5

6

7

+INA

-INA

VSS

1

2

3

4

OUTA

+IN

-IN

VSS

1

2

3

4

NC

VDD

OUT

NC

CS8

7

6

5

OUTB

-INB

+INB

VDD8

7

6

5

PDIP, SOIC, TSSOPMCP601 MCP602

VDD

OUT

PDIP, SOIC, TSSOPMCP604

-

NC

NCA

B

MCP603

8

7

6

5

++ -

+--

+

A+-

+INC

-INC

OUTC

10

9

8

D+ -

B+- C

+ -

PDIP, SOIC, TSSOPPDIP, SOIC, TSSOP

1

2

3 4

5

-+

OUT

VSS

+IN

VDD

-IN

MCP601SOT23-5

2000 Microchip Technology Inc. DS21314D-page 1

MCP601/602/603/604

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*VDD ..................................................................................7.0VAll inputs and outputs w.r.t. ............. VSS -0.3V to VDD +0.3VDifference Input voltage ....................................... |VDD - VSS|Output Short Circuit Current ..................................continuousCurrent at Input Pin .......................................................±2mACurrent at Output and Supply Pins .............................±30mAStorage temperature .....................................-65°C to +150°CAmbient temp. with power applied ................-55°C to +125°CSoldering temperature of leads (10 seconds) .............+300°CESD Tolerance .................................3KV Human Body Model

*Notice: Stresses above those listed under “Maximum Ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listingsof this specification is not implied. Exposure to maximum ratingconditions for extended periods may affect device reliability.

PIN FUNCTION TABLE

DC CHARACTERISTICS

NAME FUNCTION

+IN, +INA, +INB, +INC, +IND Non-inverting Input Terminals

-IN, -INA, -INB, -INC, -IND Inverting Input Terminals

VDD Positive Power Supply

VSS Negative Power Supply

OUT, OUTA, OUTB, OUTC, OUTD Output Terminals

CS Chip Select

NC No internal connection to IC

Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND, TA = 25 °C, VCM = VDD/2, RL = 100kΩ to VDD/2, and VOUT ~ VDD/2

PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONSINPUT OFFSET VOLTAGEInput Offset Voltage VOS -2 +2 mV

Over Temperature(1) VOS -3 +3 mV TA= -40°C to +85°C

Drift with Temperature dVOS/dT — ±2.5 — µV/°C TA= -40°C to +85°C

Power Supply Rejection PSRR — 40 100 µV/V for VDD = 2.7V to 5.5V

INPUT CURRENT AND IMPEDANCEInput Bias Current IB — 1 — pA

Over Temperature(2) IB — 20 60 pA TA= -40°C to +85°C

Input Offset Bias Current IOS — 1 — pA

Common Mode Input Impedance ZCM — 1013||6 — Ω||pF

Differential Input Impedance ZDIFF — 1013||3 — Ω||pF

COMMON MODECommon-Mode Input Range VCM VSS−0.3 — VDD−1.2 V

Common-Mode Rejection Ratio CMRR 75 90 — dB VDD = 5V, VCM = -0.3 to 3.8V

OPEN LOOP GAINDC Open Loop Gain AOL 100 115 — dB RL = 25kΩ to VDD/2,

50mV < VOUT <(VDD − 50 mV)

DC Open Loop Gain AOL 95 110 — dB RL = 5kΩ to VDD/2, 100mV < VOUT < (VDD − 100mV)

OUTPUTLow Level/High Level Output Swing VOL, VOH VSS + 0.015 — VDD − 0.020 V RL = 25kΩ to VDD/2

VOL, VOH VSS + 0.045 — VDD − 0.060 V RL = 5kΩ to VDD/2

Linear Region Maximum OutputVoltage Swing

VOUT VSS + 0.050 — VDD − 0.050 V RL = 25kΩ to VDD/2, AOL ≥ 100dB

VOUT VSS + 0.100 — VDD − 0.100 V RL = 5kΩ to VDD/2, AOL ≥ 95dB

Output Short Circuit Current ISC 20 — mA VOUT = 2.5V, VDD = 5V

POWER SUPPLYSupply Voltage VDD 2.7 — 5.5 V

Quiescent Current Per Amp IQ 230 325 µA IL = 0

Note 1: Max. and Min. specified for PDIP and SOIC packages only. Typical refers to all other packages Note 2: Max. and Min. specified for PDIP, SOIC, and TSSOP packages only. Typical refers to all packages.

DS21314D-page 2 2000 Microchip Technology Inc.

MCP601/602/603/604

AC CHARACTERISTICS

SPECIFICATIONS FOR MCP603 CHIP SELECT FEATURE

TEMPERATURE SPECIFICATIONS

Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 100kΩ to VDD/2, and VOUT ~ VDD/2

PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONS

Gain Bandwidth Product GBWP — 2.8 MHz VDD = 5V

Phase Margin Θm — 50 — degrees CL = 50pF, VDD = 5V

Slew Rate SR — 2.3 — V/µs G = +1V/V, VDD = 5V

Setting Time to 0.01% — 4.5 — µs for ∆VOUT = 3.8VSTEP, CL = 50pF, VDD = 5V, G = +1V/V

NOISE

Input Voltage Noise en — 7 — µVP-P f = 0.1Hz to 10Hz

Input Voltage Noise Density en — 29 — nV/ f = 1kHz

Input Current Noise Density in — 0.6 — fA/ f = 1kHz

Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 100kΩ to VDD/2, and VOUT ~ VDD/2


CS LOW SPECIFICATIONS

CS Logic Threshold, Low VIL VSS 0.42 VDD 0.2 VDD V For entire VDD range

CS Input Current, Low ICSL -1.0 — — µA CS = 0.2VDD

Amplifier Output Leakage, CS High — 1 — nA

CS HIGH SPECIFICATIONS

CS Logic Threshold, High VIH 0.8 VDD 0.51 VDD VDD V For entire VDD range

CS Input High, Shutdown CS PinCurrent

ICSH — 0.7 2.0 µA CS = VDD

CS Input High, Shutdown GND Current

IQ — 0.7 2.0 µA CS = VDD

DYNAMIC SPECIFICATIONS

CS Low to Amplifier Output HighTurn-on Time

tON — 3.1 10 µs CS low ≤ 0.2VDD

CS High to Amplifier Output High Z tOFF — 100 — ns CS high ≥ 0.8VDD, No Load

CS Threshold Hysteresis — 0.3 — V

Hz

Hz

Unless otherwise indicated, all limits are specified for VDD = +2.7V to +5.5V, VSS = GND


TEMPERATURE RANGE

Specified Temperature Range TA -40 — +85 °C

Operating Temperature Range TA -40 — +85 °C

Storage Temperature Range TA -65 — +150 °C

THERMAL PACKAGE RESISTANCE

Thermal Resistance, 5L-SOT23-5 θJA — 256 — °C/W

Thermal Resistance, 8L-PDIP θJA — 85 — °C/W

Thermal Resistance, 8L-SOIC θJA — 163 — °C/W

Thermal Resistance, 8L-TSSOP θJA — 124 — °C/W

Thermal Resistance, 14L-PDIP θJA — 70 — °C/W

Thermal Resistance, 14L-SOIC θJA — 120 — °C/W

Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W


MCP601/602/603/604

2.0 TYPICAL PERFORMANCE CURVESNote: Unless otherwise indicated, VDD = +2.7V to +5.5V, TA = 25°C, VCM = VDD/2, RL = 25kΩ to VDD/2 and VOUT ~ VDD/2

FIGURE 2-1: Open Loop Gain, Phase Margin vs. Frequency

FIGURE 2-2: Slew Rate vs. Temperature

FIGURE 2-3: Gain Bandwidth Product vs. Temperature

FIGURE 2-4: Quiescent Current vs. Power Supply

FIGURE 2-5: Quiescent Current vs. Temperature

FIGURE 2-6: Input Voltage Noise Density vs.Frequency

Pha

se M

argi

n (d

egre

es)

-60

-40

-20

0

20

40

60

80

100

120

0 10 1000 100000 10000000Frequency (Hz)

Ope

n Lo

op G

ain

(dB

)

-250

-200

-150

-100

-50

0

50

100

150

200CL = 50pF, RL = 100kΩVDD = 5V

Gain

Phase

0.1 10 1K 100K 10M

1

1.5

2

2.5

3

3.5

-40 -20 0 20 40 60 80

Temperature (°C)

Sle

w R

ate

(V/ µ

s)

High-to-Low Transition

Low-to-High Transition

CL=50pF, RL=100kΩ,

VDD=5V

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

-40 -20 0 20 40 60 80

Temperature (°C)

Gai

n B

andw

idth

Pro

duct

(M

Hz)

40

45

50

55

60

65

70

75

80

85

Pha

se M

argi

n (d

egre

es)Gain Bandwidth Product

Phase

CL = 55pF

100

120

140

160

180

200

220

240

260

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply, VDD (V)

Qui

esce

nt C

urre

nt p

er A

mpl

ifier

( µA

)

IL = 0

100

120

140

160

180

200

220

240

260

280

300

-40 -20 0 20 40 60 80

Temperature (°C)

Qui

esce

nt C

urre

nt p

er A

mpl

ifier

(µA

)VDD = 5.5V

VDD = 2.7V

I L = 0

0.1 1 10 100 1k 10k 100k 1M10

100

1000

10000

Frequency (Hz)

Inpu

t Vol

tage

Noi

se D

ensi

ty (

nV/ √

Hz)

RL = 10kΩ


MCP601/602/603/604

Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, TA = 25°C, VCM = VDD/2, RL = 25kΩ to VDD/2 and VOUT ~ VDD/2

FIGURE 2-7: Offset Voltage vs. Number ofOccurrences with VDD = 5.5V

FIGURE 2-8: Offset Voltage vs. Number ofOccurrences with VDD = 2.7V.

FIGURE 2-9: Normalized Offset Voltage vs. Temper- ature with VDD = 2.7V

FIGURE 2-10: Offset Voltage Drift vs. Number ofOccurrences with VDD = 5.5V

FIGURE 2-11: Offset Voltage Drift vs. Number ofOccurrences with VDD = 2.7V

FIGURE 2-12: Common-Mode Rejection Ratio, Power Supply Rejection Ratio vs. Temperature

0

5

10

15

20

25

30

35

40

-1.7

5

-1.5

0

-1.2

5

-1.0

0

-0.7

5

-0.5

0

-0.2

5

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

Offset Voltage (mV)

Nu

mb

ero

fO

ccu

racn

es

-2.0

0

VDD = 5.5VRL = 100kΩSample Size = 203 op amp

0

5

10

15

20

25

30

35

40

-1.7

5

-1.5

0

-1.2

5

-1.0

0

-0.7

5

-0.5

0

-0.2

5

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

Offset Voltage (mV)

Nu

mb

er

of

Occ

ura

nce

s

-2.0

0

VDD = 2.7VRL = 100kΩSample Size = 203 op amp

-500

-400

-300

-200

-100

0

100

200

300

400

500

-40 -20 0 20 40 60 80

Temperature (°C)

Offs

et V

olta

ge (

µV)

VDD = 5.5V

VDD = 2.7V

RL = 100kΩ

0

10

20

30

40

50

60

1 2 3 4 5 6 7 8

Change in Offset Voltage with Temperature (µV/°C)

Nu

mb

ero

fO

ccu

ran

ces

0

VDD = 5.5VRL = 100kΩSample Size = 203Temperature Range = -40°C to +85°C

0

10

20

30

40

50

60

1 2 3 4 5 6 7 8

Change in Offset Voltage with Temperature (µV/°C)

Nu

mb

ero

fO

ccu

ran

ces

0 11

VDD = 2.7VRL = 100kΩSample Size = 203Temperature Range = -40°C to +85°C

75

80

85

90

95

100

-40 -20 0 20 40 60 80

Temperature (° C)

Com

mon

Mod

e R

ejec

tion

Rat

io, P

ower

Sup

ply

Rej

ectio

nR

atio

(dB

)

CMRRVDD = 2.7V

VCM = -0.3V to 1.5V

PSRR, VDD = 2.7V to 5.5V

CMRRVDD = 5.5V

VCM = -0.3V to 4.3V


MCP601/602/603/604

Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, TA = 25°C, VCM = VDD/2, RL = 25kΩ to VDD/2 and VOUT ~ VDD/2

FIGURE 2-13: Offset Voltage vs. Common-Mode Voltage

FIGURE 2-14: Input Bias Current, Input Offset Current vs. Temperature

FIGURE 2-15: DC Open Loop Gain vs. Output Load

FIGURE 2-16: Common-Mode Rejection Ratio,Power Supply Rejection Ratio vs. Frequency

FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage

FIGURE 2-18: DC Open Loop Gain vs. Power Supply

40

60

80

100

120

140

160

180

200

220

240

-1 0 1 2 3 4 5

Common Mode Voltage (V)

Off

set

Vol

tage

(µV

)

Representative Part

VDD = 2.7V

VDD = 5.5V

0

2

4

6

8

10

12

14

16

18

20

-40 -20 0 20 40 60 80

Temperature (°C)

Inpu

t Bia

s C

urre

nt, I

nput

Offs

et C

urre

nt (

pA)

Input Bias Current Levels are Typically less than 1pA Below 25°C

Input Bias Current

Input Offset

Current

VDD = 5.5V

80

90

100

110

120

0 20000 40000 60000 80000 100000

Load Resistance (Ω)

DC

Ope

n Lo

op G

ain

(dB

)

VDD = 5.5V

VDD = 2.7V

0 2K 4K 6K 8K 10K

-20

0

20

40

60

80

100

1 10 100 1000 10000 100000 1000000 10000000

Frequency (Hz)

PS

RR

, CM

RR

(dB

)

PSRR+

PSRR-

VDD=5.0V,

CL=50 pF

CMRR

1 10 100 1K 10K 100K 1M 10M

0

2

4

6

8

10

12

14

16

18

20

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

Common-mode Voltage (V)

Inpu

t Bia

s, In

put O

ffset

Cur

rent

(pA

)

VDD = 5.5V

RL = ∞TA = 85 °C

Input Bias Current

Input Offset

90

95

100

105

110

115

2 2.5 3 3.5 4 4.5 5 5.5

Power Supply Voltage, VDD (V)

Ope

n Lo

op G

ain

(dB

)


MCP601/602/603/604

Note: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, RL = 25kΩ to VDD/2 andVOUT ~ VDD/2

FIGURE 2-19: Gain Bandwidth, Phase Margin vs.Load Resistance

FIGURE 2-20: Low Level and High Level OutputSwing vs. Resistive Load

FIGURE 2-21: Maximum Full Scale Output VoltageSwing vs. Frequency

FIGURE 2-22: DC Open Loop Gain vs. Temperature

FIGURE 2-23: Low Level and High Level OutputSwing vs. Temperature

FIGURE 2-24: Output Short Circuit Current vs.Temperature

0

0.5

1

1.5

2

2.5

3

3.5

100 1000 10000 100000

Resistance (W)

Gai

n-B

andw

idth

(M

Hz)

30

40

50

60

70

80

90

100

Pha

se M

argi

n (d

egs)

Gain-Bandwidth

Phase MarginVDD = 5.0V,CL= 50 pF

100 1K 10K 100K

0

100

200

300

400

500

600

700

100 1000 10000 100000

Load Resistance (Ω)

VD

D-V

OH,

VO

L-V

SS (

mV

)

VDD-VOH

VDD=5.5V

VOL - VSS

VDD=5.5V

VDD-VOH

VDD=2.7V

VOL - VSS

VDD=2.7V

100 1K 10K 100K

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

1000 10000 100000 1000000 10000000

Frequency (Hz)

Ful

l-Sca

le O

utpu

t Vol

tage

Sw

ing

(V)

VDD = 5V

1K 10K 100K 1M 10M

80

85

90

95

100

105

110

115

120

-40 -20 0 20 40 60 80Temperature (°C)

DC

Ope

n Lo

op G

ain

(dB

)

VDD = 2.7V, VOUT = 50mV to 2.65V

VDD = 5.5V, VOUT = 50mV to 5.45V

0

2

4

6

8

10

12

-40 -20 0 20 40 60 80

Temperature (°C)

VO

H,

VO

L (m

V)

VDD-VOH, VDD=2.7VVOL-VSS, VDD=5.5V

VDD-VOH, VDD=5.5V

VOL-VSS, VDD=2.7V

-40

-30

-20

-10

0

10

20

30

40

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80

Temperature (°C)

Sho

rt C

ircui

t Cur

rent

(m

A)

Positive Short Circuit CurrentVDD = 5.5V

Positive Short Circuit CurrentVDD = 2.7VNegative Short Circuit Current

VDD = 2.7V

Negative Short Circuit CurrentVDD = 5.5V


MCP601/602/603/604


FIGURE 2-25: Large Signal Non-Inverting SignalPulse Response

FIGURE 2-26: Small Signal Non-inverting PulseResponse

FIGURE 2-27: Chip Select to Amplifier OutputResponse Time

FIGURE 2-28: Large Signal Inverting Signal Pulse Response

FIGURE 2-29: Small Signal Inverting Signal PulseResponse

FIGURE 2-30: GND Current vs. CS Voltage

1µS / div

500

mV

/ di

v

VDD = 5VRL = 100kΩCL = 50pFG = +1V/V

1µS / div

50 m

V/d

iv

VDD = 5V

RL = 100kΩCL=50 pFG = +1V/V

5 µS/div

500

mV

/div

CSAmplifier OutputActive

RL = 100kΩ to GND

CL = 50pFG = +1V/VVIN+ = 2.5V

VDD = 5V

Hi-Z

1µS / div

500

mV

/div

CL=50pF, RL=100kΩ,

VDD = 5V, G= -1V/V

1µS / div

50 m

V/d

iv

CL=50pF, RL=100kΩ,

VDD = 5V, G= -1V/V

-800

-700

-600

-500

-400

-300

-200

-100

0

100

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

CS Pin Voltage (V)

GN

D C

urre

nt (

µA)

VDD = 5.5V


MCP601/602/603/604


FIGURE 2-31: Input CS Current vs. CS Voltage

FIGURE 2-32: Channel to Channel Separation

FIGURE 2-33: CS hysteresis

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.0 1.0 2.0 3.0 4.0 5.0 6.0

CS Pin Voltage (V)

CS

Pin

Cur

rent

(uA

)

VDD = 5.5V

-150

-145

-140

-135

-130

-125

-120

-115

-110

-105

-100

100 1000 10000 100000 1000000Frequency (Hz)

Cha

nnel

to C

hann

el Is

olat

ion

(dB

)

RL = ∞

100 1K 10K 100K 1M

-0.5

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5 6CS Input Voltage (V)

Inte

rnal

CS

Sw

itch

Out

put (

V)

VDD = 5V

CS Input Low to High

CS Input High to Low

Amplifier Output in Hi-Z state

Amplifier Output Active (driven)


MCP601/602/603/604

3.0 APPLICATIONS INFORMATIONThe MCP601/602/603/604 family of operational ampli-fiers are fabricated on Microchip’s state-of-the-artCMOS process. They are unity gain stable and suitablefor a wide range of general purpose applications. Withthis family of operational amplifiers, the power supplypin should be by-passed with a 1µF capacitor.

3.1 Rail-to-Rail Output Swing

There are two specifications that describe the outputswing capability of the MCP601/602/603/604 family ofoperational amplifiers. The first specification, Low Leveland High Level Output Voltage Swing, defines theabsolute maximum swing that can be achieved underspecified loaded conditions. For instance, the LowLevel Output Voltage Swing of the MCP601/602/603/604 family is specified to be able to swing at least to15mV from the negative rail with a 25kΩ load to VDD/2.

This output swing performance is shown in Figure 3-1,where the output of an MCP601 is configured in a gainof +2V/V and over driven with a 40kHz triangle wave. Inthis figure, the degradation of the output swing linearityis clearly illustrated. This degradation occurs after thepoint at which the open loop gain of the amplifier isspecified and before the amplifier reaches its maximumand minimum output swing.

FIGURE 3-1: Low Level and High Level OutputSwing

The second specification that describes the outputswing capability of these amplifiers is the Linear RegionMaximum Output Voltage Swing. This specificationdefines the maximum output swing that can beachieved while the amplifier is still operating in its linearregion.

The Linear Region Maximum Output Voltage Swing ofthe MCP601/602/603/604 family is specified within50mV from the positive and negative rail with a 25kΩload and 100mV from the rails with a 5kΩ load. Theoverriding condition that defines the linear region of theamplifier is the open loop gain that is specified over thatregion. In the voltage output region between VSS +50mV and VDD - 50mV, the open loop gain is specifiedto 100dB (min) with a 25kΩ load.

The classical definition of the open loop gain of anamplifier is:

AOL = ∆VOUT / ∆VOS

where:

AOL is the DC open loop gain of the amplifier,

∆VOUT is equal to (VDD - 50mV) - (VSS + 50mV)for RL= 25kΩ, and

∆VOS is the change in offset voltage with thechanging output voltage of the amplifier.

3.2 Input Voltage and Phase Reversal

Since the MCP601/602/603/604 amplifier family isdesigned with CMOS devices, it does not exhibit phaseinversion when the input pins exceed the negative sup-ply voltage. Figure 3-2 shows an input voltage exceed-ing both supplies with no resulting phase inversion.

FIGURE 3-2: The MCP601/602/603/604 family of opamps do not have phase reversal issues. For thegraph, the amplifier is in a unity gain or bufferconfiguration.

-2

0

2

4

6

8

10

0 10 20 30 40 50

Time (µs)

Inpu

t Sig

nal (

V)

-0.7

-0.5

-0.3

-0.1

0.1

0.3

0.5

VO

H, V

OL

(0.1

mV

/div

)

VOLVOH

G=+2V/V, VDD= 5V

VDD

VSS

-1

0

1

2

3

4

5

6

0 10 20 30 40 50

Time(µS)

Inpu

t and

Out

put V

olta

ge (

V)

Input Signal

Output Signal

G = +2V/VVDD = 5V


MCP601/602/603/604

The maximum operating common-mode voltage thatcan be applied to the inputs is VSS - 0.3V to VDD - 1.2V.In contrast, the absolute maximum input voltage is VSS- 0.3V and VDD + 0.3V. Voltages on the input thatexceed this absolute maximum rating can cause exces-sive current to flow in or out of the input pins. Currentbeyond ±2mA can cause possible reliability problems.Applications that exceed this rating must be externallylimited with an input resistor as shown in Figure 3-3.

FIGURE 3-3: If the inputs of the amplifier exceed theAbsolute Maximum Specifications, an input resistor,RIN, should be used to limit the current flow into thatpin.

3.3 Capacitive Load and Stability

Driving capacitive loads can cause stability problemswith many of the higher speed amplifiers.

For any closed loop amplifier circuit, a good rule ofthumb is to design for a phase margin that is no lessthan 45°. This is a conservative theoretical value, how-ever, if the phase margin is lower, layout parasitics candegrade the phase margin further causing a trulyunstable circuit. A system phase shift of 45° will havean overshoot in its step response of approximately25%.

A buffer configuration with a capacitive load is the mostdifficult configuration for an amplifier to maintain stabil-ity. The Phase versus Capacitive Load of the MCP60Xamplifier is shown in Figure 3-4. In this figure, it can beseen that the amplifier has a phase margin above 40°,while driving capacitance loads up to 100pF.

FIGURE 3-4: Gain Bandwidth, Phase Margin vs.Capacitive Load

FIGURE 3-5: Amplifier circuits that can be usedwhen driving heavy capacitive loads.

If the amplifier is required to drive larger capacitiveloads, the circuit shown in Figure 3-5 can be used. Asmall series resistor (RISO) at the output of the amplifierimproves the phase margin when driving large capaci-tive loads. This resistor decouples the capacitive loadfrom the amplifier by introducing a zero in the transferfunction.

This zero adjusts the phase margin by approximately:

∆θm = tan-1 (2π GBWP x RISO x CL)

where:

∆θm is the improvement in phase margin,

GBWP is the gain bandwidth product of theamplifier,

RISO is the capacitive decoupling resistor, and

CL is the load capacitance

RIN = (Maximum expected voltage - VDD) / 2mA

or

(VSS - Minimum expected voltage)/ 2mA.

RIN

MCP60X

0

0.5

1

1.5

2

2.5

3

3.5

4

10 100 1000 10000 100000 1000000

Capacitance (pF)

Gai

n-B

andw

idth

(M

Hz)

0

10

20

30

40

50

60

70

80

Pha

se M

argi

n (d

egre

es)

Gain-Bandwidth

Phase Margin

VDD=5.0V,

RL=100 kΩ

10 100 1E3 10E3 100E3 1E6

VIN

CL

RISO VOUTMCP60X

VDD


MCP601/602/603/604

3.4 The Chip Select Option of the MCP603

The MCP603 is a single amplifier with a Chip Selectoption. When CS is pulled high the supply currentdrops to 0.7µA (typ), which is pulled through the CS pinto VSS. In this state, the amplifier is put into a highimpedance state. By pulling CS low or letting the pinfloat, the amplifier is enabled. Figure 3-6 shows the out-put voltage and supply current response to a CS pulse.

FIGURE 3-6: Timing Diagram for the CS Function of the MCP603 Amplifier

3.5 Layout Considerations

In applications where low input bias current is critical,PC board surface leakage effects and signal couplingfrom trace to trace need to be taken into consideration.

3.5.1 SURFACE LEAKAGE

Surface leakage across a PC board is a consequenceof differing DC voltages between two traces combinedwith high humidity, dust or contamination on the board.For instance, the typical resistance from PC boardtrace to pad is approximately 1012Ω under low humidityconditions. If an adjacent trace is biased to 5V and theinput pin of the amplifier is biased at or near zero volts,a 5pA leakage current will appear on the amplifier’sinput node. This type of PCB leakage is five times theroom temperature input bias current (1pA, typ) of theMCP601/602/603/604 family of amplifiers.

The simplest technique that can be used to reduce theeffects of PC board leakage is to design a ring aroundsensitive pins and traces. An example of this type oflayout is shown in Figure 3-7.

FIGURE 3-7: Example of Guard Ring for theMCP601, the A-amplifier of the MCP602 or theMCP603 in a PC Board Layout

VIL

Hi-Z

tON

VIH

tOFF

Hi-ZOutput

2.0nA (typ) 2.0nA (typ)VDD SupplyCurrent

230µA (typ)

0.7µA (typ) 0.7µA (typ)GND Current

230µA (typ)

0.7µA (typ) 0.7µA (typ)CSCurrent

2nA(typ)

CS

-In +In V-

Guard Ring


MCP601/602/603/604

Circuit examples of ring implementations are shown inFigure 3-8. In Figure 3-8A, B and C, the guard ring isbiased to the common-mode voltage of the amplifier.This type of guard ring is most effective for applicationswhere the common-mode voltage of the input stagechanges, such as buffers, inverting gain amplifiers orinstrumentation amplifiers.

The strategy shown in Figure 3-8D, biases the com-mon-mode voltage and guard ring to ground. This typeof guard ring is typically used in precision photo sens-ing circuits.

FIGURE 3-8: Examples of how to design PC Boardtraces to minimize leakage paths to the highimpedance input pins of the MCP601/602/603/604amplifiers.

3.5.2 SIGNAL COUPLING

The input pins of the MCP601/602/603/604 amplifiershave a high impedance providing an opportunity fornoise injection, if layout issues are not considered.These high impedance input terminals are sensitive toinjected currents. This can occur if the trace from a highimpedance input is next to a trace that has fast chang-ing voltages, such as a digital or clock signal. When ahigh impedance trace is in close proximity to a tracewith these types of voltage changes, charge is capaci-tively coupled into the high impedance trace.

FIGURE 3-9: Capacitors can be built with PCBtraces allowing for coupling of signals from one traceto another.

As shown in Figure 3-9, the value of the capacitancebetween two traces is primarily dependent on the dis-tance (d) between the traces and the distance that thetwo traces are in parallel (L). From this model, theamount of current generated into the high impedancetrace is equal to:

I = C ∂V/∂t

where:

I equals the current that appears on the highimpedance trace,

C equals the value of capacitance between the twoPCB traces,

∂V equals the change in voltage of the trace that isswitching, and

∂t equals the amount of time that the voltagechange took to get from one level to the next.

Voltage

Reference

(could be ground)

MCP60X

MCP60X

MCP60X

MCP60X

VDD

Figure 3-8A

Figure 3-8C

Figure 3-8B

Figure 3-8D

w= thickness of PCB trace

L= length of PCB trace

d= distance between the two PCB traces

PCB Trace

w(typ 0.003mm)

PCBCross-Section

w x L x eo x erC = pFd

L

d


MCP601/602/603/604

3.6 Typical Applications

3.6.1 ANALOG FILTERS

Examples of two second order low pass filters areshown in Figure 3-10 and Figure 3-11. The filter in Fig-ure 3-10 can be configured for gain of +1V/V or greater.The filter in Figure 3-11 can be configured for invertinggains.

FIGURE 3-10: 2nd Order Low Pass Sallen-Key Filter

FIGURE 3-11: 2nd Order Low PassMultiple-Feedback Filter

The MCP601/602/603/604 family of operational ampli-fiers are particularly well suited for these types of filters.The low input bias current, which is typically 1pA (up to60pA at temperature), allows the designer to selecthigher value resistors, which in turn reduces the capac-itive values. This allows the designer to select surfacemount capacitors, which in turn can produce a compactlayout.

The rail-to-rail output operation of the MCP601/602/603/604 family of amplifiers make these circuits wellsuited for single supply operation. Additionally, the widebandwidth allows low pass filter design up to 1/10 of theGBWP or 300kHz.

These filters can be designed using the calculationsprovided in the Figures or with Microchip’s interactiveFilterLab software. FilterLab will calculate capacitorand resistor values, as well as, determine the number

of poles that are required for the application. Finally, theprogram will generate a SPICE macromodel, which canbe used for spice simulations.

3.6.2 INSTRUMENTATION AMPLIFIER CIRCUITS

The instrumentation amplifier has a differential input,which subtracts one analog signal from another andrejects common mode signals. This amplifier also pro-vides a single ended analog output signal. The three opamp instrumentation amplifier is illustrated in Figure3-12 and the two op amp instrumentation amplifier isshown in Figure 3-13.

FIGURE 3-12: An instrumentation amplifier can bebuilt using three operational amplifiers and sevenresistors.

FIGURE 3-13: An instrumentation amplifier can alsobe built using two operational amplifiers and fiveresistors.

R2

VOUT

VIN

C2

R1

R4R3

C1

Sallen-Key

VOUT

VIN

K/(R1R2C2C1)

s2+s(1/R1C2+1/R2C2+1/R2C1 – K/R2C1+1/R1R2C2C1)=

K = 1 + R4/R3

MCP60X

R3

VOUT

VIN

R1

C2

R2C1

VOUT

VIN

–1/R1R3C2C1

s2C2C1 + sC1(1/R1 + 1/R2 + 1/R3) + 1/(R2R3C2C1)=

MCP60X

*Bypass Capacitor, 1µF

V2

R4

R3 VOUTRG MCP60X

V1

R2

R2

R4R3*

*

VOUT V1 V2–( ) 12R2

RG---------+

R4

R3------

VREF

R4

R3------

+=

VREF

VDD

VDD

MCP60X

MCP60X

*

VOUT

*Bypass Capacitor, 1µF

VREF

V2

RG

R1

VOUT V1 V2–( ) 1R1

R2------

2R1

RG---------+ +

VREF+=

V1

R2

R1

R2

VDD

MCP60X

MCP60X


MCP601/602/603/604

An advantage of the three op amp configuration is thatit is capable of unity gain operation. A disadvantage, ascompared to the two op amp instrumentation amplifier,is that the common mode range reduces with highergains.

The two op amp configuration uses fewer op amps, sopower consumption is also low. Disadvantages of thisconfiguration are that the common-mode rangereduces with gain and it must be configured in gains oftwo or higher.

3.6.3 PHOTO DETECTION

The amplifiers in the MCP601/602/603/604 family ofdevices can be used to easily convert the signal from asensor that produces an output current, such as a pho-todiode, into a voltage. This is implemented with a sin-gle resistor and an optional capacitor in the feedbackloop of the amplifier as shown in Figure 3-14.

FIGURE 3-14: Photo Sensing Circuits Using theMCP60X Amplifier

A photodiode that is configured in the photovoltaicmode has no voltage potential placed across the ele-ment or is zero biased (Figure 3-14). In this mode, thelight sensitivity and linearity is maximized making itbest suited for precision applications. The key amplifierspecifications for this application are low input bias cur-rent, low noise and rail-to-tail output swing. TheMCP601/602/603/604 family is capable of meeting allthree of these difficult requirements.

In contrast, a photodiode that is configured in the pho-toconductive mode has a reverse bias voltage, which isapplied across the photo sensing element as shown inFigure 3-14. The width of the depletion region isreduced when this voltage is applied across the photodetector, which reduces the photodiode parasiticcapacitance significantly. This reduced parasitic capac-itance facilitates high speed operation, however, the lin-earity and offset errors are not optimized. The designtrade off for this action is increased diode leakage cur-rent and linearity errors. A key amplifier specification forthis application is high speed digital communication.The MCP601/602/603/604 family is well suited formedium speed photoconductive applications with theirwide bandwidth and rail-to-rail output swing.

VBIAS

R2

C2

R2

VOUT

VOUT = R2 ID1

D1

VOUT

Light

D1

Light

MCP60X

MCP60X

ID1

ID1

Photodiode in Photovoltaic Mode

Photodiode in Photoconductive Mode


MCP601/602/603/604

4.0 SPICE MACROMODELThe Spice macromodel for the MCP601, MCP602,MCP603 and MCP604 simulates the typical amplifierperformance of offset voltage, DC power supply rejec-tion, input capacitance, DC common mode rejectionratio, open loop gain over frequency, phase margin withno capacitive load, output swing, DC power supply cur-rent, power supply current change with supply voltage,input common mode range and input voltage noise.

The characteristics of the MCP601, MCP602,MCP603, and MCP604 amplifiers are similar in termsof performance and behavior. This single op amp mac-romodel supports all four devices with the exception ofthe chip select function of the MCP603, which is notmodeled.

The listing for this macromodel is shown on the nextpage. The most recent revision of the model can bedownloaded from Microchip’s web site atwww.microchip.com.


MCP601/602/603/604

.subckt mcp601 1 2 3 4 5* | | | | |* | | | | Output* | | | Negative supply* | | Positive Supply* | Inverting input* Non-inverting input** Macromodel for MCP601 (single), MCP602 (dual), MCP603 (single w/CS), and MCP604 (quad)** The characteristics of the MCP601, MCP602, MCP603, and MCP604 have the same fundamental * performance and behavior. Consequently, this single op amp macromodel supports all four * devices. However, the chip select function of the MCP603 is not modeled.** Revision History:* REV A : 6-30-99 created BCB* REV B : 7-10-99 corrected DC Iq BCB* REV C : 11-30-99 Placed “.subckt” command as first line, added L, W to Ptype model in

: listing BCB** This macromodel models typical amplifier offset voltage, DC power supply rejection, input * capacitance, DC common mode rejection ratio, open loop gain over frequency, phase margin * with no capacitive load, output swing, power supply current, input voltage noise.** NOTICE: THE INFORMATION PROVIDED HEREIN IS BELIEVED TO BE RELIABLE,* HOWEVER, MICROCHIP ASSUMES NO RESPONSIBILITY FOR INACCURACIES OR* OMISSIONS. MICROCHIP ASSUMES NO RESPONSIBILITY FOR THE USE OF THIS* INFORMATION, AND ALL USE OF SUCH INFORMATION SHALL BE ENTIRELY AT* THE USER’S OWN RISK. NO INTELLECTURAL PROPERTY RIGHTS OR LICENSES * TO ANY OF THE TECNOLOGY DESCRIBED HEREIN ARE IMPLIED OR GRANTED TO * ANY THIRD PARTY. MICROCHIP RESERVES THE RIGHT TO CHANGE THIS MODEL * AT ANY TIME WITHOUT NOTICE.**Input Stage, pole at 5MHzM1 9 64 7 3 Ptype L=2 W=275M2 8 2 7 3 Ptype L=2 W=275CDIFF 1 2 3E-12CCM1 1 4 6E-12CCM2 2 4 6E-12IDD 3 7 30e-6RA 8 6 1.485e3RB 9 6 1.485e3CA 8 9 10.71e-12

*Input Stage Common-Mode ClamplingVCMM 4 6 0.35ECM 55 4 3 64 1

RCM 57 56 1E3DCMP 56 55 DXVCMP 57 4 1.2

RST 58 59 1E3DST 59 55 DX VST 58 4 1.6

GCMP2 23 4 POLY(2) 57 56 58 59 0 -0.5E-3 0.5E-3

*Input errors (vos, en, psr, cmr)ERR 64 1 POLY(3) (67,4) (3, 4) (1,34) 0 1 40e-6 3.2e-6

*Second Stage, pole at 3.3HzGS 23 4 8 9 5.7e-3R1 23 4 0.397e9C2 23 4 122.8e-12


MCP601/602/603/604

VSOP 3 24 4.784VSOM 25 4 -3.48DSOP 23 24 DYDSOM 25 23 DY

*HCM 23 3 VCMP

FS 3 4 POLY(11) VO3 VO5 VO4 VO6 VO1 VO2 VO9 VO10 VMID1 VSOP VSOM + 200E-6 -1 -1 -1 1 -1 -1 1 1 -1 -1 -1

*mid-supply reference, output swing limitRMID1 3 35 61.62E3VMID1 35 34 0RMID2 4 34 61.62E3ELEVEL 34 4 23 4 -1

*output stageDO3 34 43 DYDO4 44 34 DYDO5 3 45 DYDO6 3 46 DYDO7 4 45 DYDO8 4 46 DYVO3 43 5 0.1VO4 5 44 0.1GO5 3 47 3 34 10E-3VO5 47 5 0 GO6 4 48 34 4 10E-3VO6 48 5 0GO1 49 4 5 34 10E-3VO1 49 45 0GO2 50 4 34 5 10E-3VO2 50 46 0RO9 3 51 100VO9 51 5 0RO10 52 4 100VO10 52 5 0

* input voltage noiseVN1 65 4 0.6DN1 65 67 DXRN1 67 4 13E3

.model Ptype PMOS

.model DY D(IS=1e-15 BV =50)

.model DX D(IS=1e-18 AF=0.6 KF=10e-17)

.ENDS


MCP601/602/603/604

MCP60X PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Package:

P = Plastic DIP (300 mil Body), 8-lead and 14-leadSN = Plastic SOIC (150 mil Body), 8-leadSL = Plastic SOIC (150 mil Body), 14-leadST = Plastic TSSOP, 8-lead and 14-leadOT = Plastic SOT23, 5-lead

Temperature Range: I = –40°C to +85°C

Device:

MCP601 = Single Operational AmplifierMCP601T = Single Operational Amplifier (Tape and Reel-SOIC/TSSOP/SOT23-5)

MCP602 = Dual Operational AmplifierMCP602T = Dual Operational Amplifier (Tape and Reel-SOIC/TSSOP)

MCP603 = Single Operational Amplifier w/CS FunctionMCP603T = Single Operational Amplifier w/CS Function

(Tape and Reel-SOIC/TSSOP)MCP604 = Quad Operational Amplifier

MCP604T = Quad Operational Amplifier (Tape and Reel-SOIC/TSSOP)

MCP60X — X /X

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differencesand recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one ofthe following:

1. Your local Microchip sales office2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-72773. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.


Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates.It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed byMicrochip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rightsarising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express writtenapproval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual propertyrights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All othertrademarks mentioned herein are the property of their respective companies.


All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 5/00 Printed on recycled paper.

AMERICASCorporate OfficeMicrochip Technology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-786-7200 Fax: 480-786-7277Technical Support: 480-786-7627Web Address: http://www.microchip.com

AtlantaMicrochip Technology Inc.500 Sugar Mill Road, Suite 200BAtlanta, GA 30350Tel: 770-640-0034 Fax: 770-640-0307BostonMicrochip Technology Inc.5 Mount Royal AvenueMarlborough, MA 01752Tel: 508-480-9990 Fax: 508-480-8575ChicagoMicrochip Technology Inc.333 Pierce Road, Suite 180Itasca, IL 60143Tel: 630-285-0071 Fax: 630-285-0075DallasMicrochip Technology Inc.4570 Westgrove Drive, Suite 160Addison, TX 75248Tel: 972-818-7423 Fax: 972-818-2924DaytonMicrochip Technology Inc.Two Prestige Place, Suite 150Miamisburg, OH 45342Tel: 937-291-1654 Fax: 937-291-9175DetroitMicrochip Technology Inc.Tri-Atria Office Building 32255 Northwestern Highway, Suite 190Farmington Hills, MI 48334Tel: 248-538-2250 Fax: 248-538-2260Los AngelesMicrochip Technology Inc.18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 949-263-1888 Fax: 949-263-1338New YorkMicrochip Technology Inc.150 Motor Parkway, Suite 202Hauppauge, NY 11788Tel: 631-273-5305 Fax: 631-273-5335San JoseMicrochip Technology Inc.2107 North First Street, Suite 590San Jose, CA 95131Tel: 408-436-7950 Fax: 408-436-7955

AMERICAS (continued)TorontoMicrochip Technology Inc.5925 Airport Road, Suite 200Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253

ASIA/PACIFICChina - BeijingMicrochip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan BuildingBeijing, 100027, P.R.C. Tel: 86-10-85282100 Fax: 86-10-85282104China - ShanghaiMicrochip Technology Unit B701, Far East International Plaza,No. 317, Xianxia RoadShanghai, 200051, P.R.C.Tel: 86-21-6275-5700 Fax: 86-21-6275-5060Hong KongMicrochip Asia PacificUnit 2101, Tower 2Metroplaza223 Hing Fong RoadKwai Fong, N.T., Hong KongTel: 852-2-401-1200 Fax: 852-2-401-3431IndiaMicrochip Technology Inc.India Liaison OfficeNo. 6, Legacy, Convent RoadBangalore, 560 025, IndiaTel: 91-80-229-0061 Fax: 91-80-229-0062JapanMicrochip Technology Intl. Inc.Benex S-1 6F3-18-20, ShinyokohamaKohoku-Ku, Yokohama-shiKanagawa, 222-0033, JapanTel: 81-45-471- 6166 Fax: 81-45-471-6122KoreaMicrochip Technology Korea168-1, Youngbo Bldg. 3 FloorSamsung-Dong, Kangnam-KuSeoul, KoreaTel: 82-2-554-7200 Fax: 82-2-558-5934

ASIA/PACIFIC (continued)SingaporeMicrochip Technology Singapore Pte Ltd.200 Middle Road#07-02 Prime CentreSingapore, 188980Tel: 65-334-8870 Fax: 65-334-8850TaiwanMicrochip Technology Taiwan10F-1C 207Tung Hua North RoadTaipei, TaiwanTel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPEDenmarkMicrochip Technology Denmark ApSRegus Business CentreLautrup hoj 1-3Ballerup DK-2750 DenmarkTel: 45 4420 9895 Fax: 45 4420 9910FranceArizona Microchip Technology SARLParc d’Activite du Moulin de Massy43 Rue du Saule TrapuBatiment A - ler Etage91300 Massy, FranceTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79GermanyArizona Microchip Technology GmbHGustav-Heinemann-Ring 125D-81739 München, GermanyTel: 49-89-627-144 0 Fax: 49-89-627-144-44ItalyArizona Microchip Technology SRLCentro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 120041 Agrate BrianzaMilan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883United KingdomArizona Microchip Technology Ltd.505 Eskdale RoadWinnersh TriangleWokingham Berkshire, England RG41 5TUTel: 44 118 921 5858 Fax: 44-118 921-5835

03/23/00

WORLDWIDE SALES AND SERVICE

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

untitled document [] · to ic unless otherwise indicated, all limits are specified for vdd = +2.7v...

Documents