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Design of SynchronStandby Sub-threshol

bias an

ShiDepaBanashiv

reetu

Abstract— The paper proposes a schemleakage(sub-threshold) standby power in synccircuits by using back gate bias, scannable flpoint insertion. A back gate bias can bcombinational circuit during standby mode foDesign is the most widely used structured attempts to improve testability of a circcontrollability and observability of storasequential design. These scannable latches withe state and output combination in which webe in after standby period is over. Keywords— Back-gate bias, Sub-threshold leDesign, control point insertion

I. INTRODUCTION Reverse body biasing has been widely umemory chips since the mid-1970s, in ordeof latch-up and memory data destructionsubstrate contacts for high density cell layoon the other hand, the substrate and wells astably to the ground and power potentisubstrate contacts to ensure that no devicebiased, raising the risk of latch-up duoperation of random logic circuits. Sinchowever, reverse body biasing has been appfor a different reason: power reduction. The sequential circuits in a mobile poperations in the active mode, while operastandby mode. The processor is requiredstandby mode, which may often be for relain mobile applications. Leakage reduction itherefore essential. As long as we keep theand our date output in the correct state we cremain in the standby state and reduce poincreasing the body bias during the standby

II. BODY BIAS

nous Sequential Circuitsd Leakage-Power Usin

nd Testability Logic

ivam Verma, Reetu Raj Pandey rtment of Electronics Engg. IT-BHU

aras Hindu University, Varanasi U.P [email protected]

[email protected]

me to reduce the chronous sequential lip-flops and control be applied to the or low leakage. Scan

DFT methodology, cuit by improving

age elements in a ill be used to regain e want the circuit to

eakage, DFT, Scan

sed in commercial er to lower the risk n, due to lack of out. In logic chips, are typically biased ial with sufficient es become forward ue to unexpected ce the mid-1990s, plied in logic chips

processor execute ations are halted in d to keep data in atively long periods in standby mode is e sequential circuit can make circuit to

ower dissipation by period.

The Body bias controls thetransistors. The relation betweeis described as

0 = �Where � is the body bias e

Fermi potential. The Vth is roroot of Vbb (body bias)[1][5]. Now, as the transistor approachbelow Vth Under this conditionbecomes predominantly diffuslike bipolar transistors, dependvoltage. In other words exponentially with Vgs for Vgstherefore results in larger sub-instance a sub-threshold swingthreshold leakage current (Ioffthe Vt is reduced by 85mVthreshold voltage will decreasconsiderably. The diagram below shows howinverter

s with Low ng Back gate

e threshold voltage Vth of the n the Vth and Vbb (body bias) 2 2

effect coefficient and is the oughly proportional to square

hes the OFF-state, the Vgs goes n the drain current mechanism sion based. Diffusion current, ds exponentially on its control the drain current changes

s below Vth A reduction in Vth threshold leakage current for

g (S) of 85mV/decade, the sub-f) will increase by ten times if

V. Conversely increasing the se the Sub threshold leakage

w it can be implemented in an

2012 1st International Conference on Emerging Technology Trends in Electronics, Communication and Networking

978-1-4673-1627-9/12/$31.00 ©2012 IEEE

The body terminals of NMOS and PMOSusual to most negative and the most respectively to reverse bias every pn junsource of NMOS and PMOS is connecshown in the figure. psVdd< Vdd in standby mod nsgnd>0(gnd) in standby mode Hence back gate bias (Vsb) on NMOS =(nsg And back gate bias (Vbs) on PMOS = (VddIn the normal operation with stdby=1 the cwith source of NMOS connected to 0V (gPMOS connected to Vdd. But in standby source of PMOS will be connected to a Vdd (0 to 0.4V less for 180nm CMOS techsupply Vdd=1.8V) through the PMOS passNMOS source will be connected to a poten(gnd) i.e between 0 to 0.4 V for 180nm Cand power supply Vdd=1.8V. And Hence a to 0.4 volts can be applied to the transistorsthreshold leakage power dissipated during sPMOS pass transistors are used to pass hiand psvdd and NMOS pass transistors aresmaller potentials gnd and nsgnd respectiveThe above figure is made for an inverter with a large combinational logic circuit the not be big.

III. SCAN DESIGN Muxed D scan cell design and LSSD s

two techniques [2]. Muxed D scan cell is composed of a multiplexer. The multiplexer uses a scan enselect between data input DI and the scan in LSSD scan cell contains two flip-flops, a flip-flop having DI (data) and SI(scan) whto slave D flip-flop . Non overlapping cloclclk are used to control the propagation ooutput respectively. The output of master twis L1 and slave D flip-flop is L2.

The Muxed D scan cell design for a sequ3 memory elements is given below

Basically in the sequential circuit we hav

flops with three Muxed-D scan cells. The

S are connected as positive voltages

nction. But its the cted differently as

gnd)-0 = (nsgnd) d)- (psVdd) circuit will operate gnd) and source of mode stdby=1 the potential less than hnology and power transistors and the ntial more than 0V CMOS technology net body bias of 0

s reducing the sub-standby mode. igh potentials Vdd e used to pass the ly. for simplicity but size overhead will

can design are the

D flip-flop and a nable (SE) input to nput (SI).

master two port D hich are propagated cks dclk , sclk and f DI, SI and slave wo port D flip-flop

uential circuit with

ve replaced D flip-e data inputs DI of

each scan cell is connected to thlogic circuit. To form a scan chflip-flops are connected to the Qcells. The SI of the first flip-flopSI and Q output of last flip flooutput SO. Hence in shift modcells operate as a single scan cany combination of logic valucapture mode SE is set to 0, acapture the response from theclock is applied or one can say used only scan cells.

The LSSD full scan design with 3 memory elements is give

In LSSD full scan circuit, th

are distinguished by non overlapDuring the shift operation scl

overlapping manner, and the schain from SI to SO. During dclk and lclk are applied in a nothe response from the combinati

IV CONCEPT

A sequential circuit can beCombinational Logic and the mof standby is during the standbycircuit stays for a long time) thmade to go to a high body bias leakage power dissipated in the

To retain the proper outputinserted control points [2](usinparticular value.

he output of the combinational hain, the scan inputs SI of the Q outputs of the previous scan p is connected as primary input op is connected to the primary de, SE is set to 1, and the scan chain which allows us to shift ues into the scan cells. In the and the scan cells are used to e combinational logic when a

it behaves in a way if we had

for a above sequential circuit en below

he shift and capture operations pping clocks. lk and lclk are applied in a non scan cells form a single scan the capture operation , clocks on overlapping manner to load ional logic into the scan cells

T OF STANDBY e seen to be composed of a memory elements. The concept y states (in which the sequential he combinational logic will be state (body bias>0) so that the circuit will be small.

t during the standby state the ng Mux) should be set to that


978-1-4673-1627-9/12/$31.00 ©2012 IEEE

Hence in the standby state the output lo

low will be equal to Vdd and 0V respectivstate of the design.

The figure above shows how this is outputs can be controlled during the stacontrol points CP5 and CP6 during the stanas the inputs are kept constant the circustandby state with the correct logical outputhat is driven by the sequential circuit. Thensgnd will provide the required back gate bpower dissipation very small by applying agate bias.

Specific sequence of events is going to bcircuit in the standby state and to end the sta

Standby Initialisation sequence The mux selects will be changed to the o/pthe standby state. Then the stdby signal wiapply a body bias to the combinational circu

Standby End sequence The back gate bias will be removed. Us

the memory elements will be loaded(in shstandby state in case due to some input chachanged and finally the control points wilmake the output change according to the log

V SIMULATION AND RES

To Illustrate the methodology a sequencea sequence (0101) circuit is simulated shbelow[4]

ogic high and logic vely along with the

implemented. The

andby mode using ndby state. As long uit can remain in

uts driving the logic e inputs psVdd and ias to keep leakage

an appropriate back

e needed to put the andby state

p corresponding to ill be made high to uit.

sing the scan chain hift mode) with the anges it might have ll be configured to gic.

SULTS e detector to detect hown in the figure

The state A will be the state cthe standby period is over.

The states are assigned as A(get sequence detector circuit smemory elements .

The usual D fip-flops will be

flops. It is operated by three ndclk (data clock), sclk (scan cloclock for the slave flip-flop)

The sclk will be used during ththe memory elements loaded which in this case is the start of Simulation is done on Cadencetechnology and supply voltagnsgnd are in between 0 and 1.8easily.

2 input Nand gate is simulagate bias on leakage power withgate bias is applied.

S.No psVdd (V)

nsgnd (V)

1 1.8 0 2 1.7 0.1 3 1.6 0.2 4 1.3 0.3 5 1.4 0.4

The combinational logic of

simulated skipping the D-flip fto the flip-flop with the output aThe results are tabulated belowthe state of the design as D

circuit will be loaded with after

(00),B(01),C(11) and D (10) to shown in figure It uses two

e replaced by scannable D flip-non overlapping clocks named ock) and the lclk (local clock or

he standby end sequence to get with a known or initial state

f the sequence detection. e spectre using 180nm CMOS

ge of 1.8V. Both psVdd and 8V and hence can be generated

ated to show the effect of back h both inputs set to and a back

Back Gate Bias(in V)

Power Dissipation

0 28pW 0.1 0.715pW 0.2 17.58fW 0.3 1.03fW 0.4 0.737fW

the above sequential circuit is flops directly connecting input and applying the back gate bias.

w. We kept the output z=1 and D (10) during simulation and


978-1-4673-1627-9/12/$31.00 ©2012 IEEE

calculation of the leakage power. The table below shows the experimental observations

S.No psVdd

(V) nsgnd (V)

Back Gate Bias(in V)

Power Dissipation (pW)

1 1.8 0 0 984.09 2 1.7 0.1 0.1 232.43 3 1.6 0.2 0.2 107.43 4 1.3 0.3 0.3 51.49 5 1.4 0.4 0.4 24.49 The plot below shows the reduction in standby leakage

power with back gate bias

CONCLUSIONS The proposed scheme results in a significant decrease in

standby leakage power using back gate bias and the testability logic (Scan chains and control points) which are an integral part in modern day VLSI Design. It is evident with the simulation results of above combinational logic that with increase of 0.1 volts back gate bias the sub-threshold power consumption is halved and hence for the sequential circuit if the standby period is large enough the power savings will be more than 25%. In future we propose to implement the methodology with minimum size overhead and reduce the increment in dynamic power dissipation due to increase size overhead. We also propose to implement the methodology in circuits that can be made to standby for long periods.

REFERENCES

[1] Siva G.Nagendra and Anantha Chandrakasan, Leakage in Nanometer CMOS technologies 2005, ISBN 0-387-25737-3 [2] Laung-Terng Wang, Cheng-Wen Wu and Xiaoqing , VLSI Test Principals and Architectures

[3] S. DasGupta et al., "A Variation of LSSD and its Implications on Design and Test Pattern Generation in VLSI," Int'l Test Conf:, IEEE, Oct. 1982, pp. 63-66. [4] ZVI Kohavi, Swithing and finite automata theory, 2nd Edition [5] Jan Rabaey, Low power Design Essentials [6]Sung-Mo Kang and Yusuf Leblebia CMOS Digital Integrated circuits [7]The National Technology Roadmap for Semiconductors by Semiconductor Industry Association,San Jose, http://public.itrs.net, 2005 [8] N.Weste and K.Eshraghian ,Principles of CMOS VLSI Design 1992. [9]J.P.Uyemura, CMOS Logic Circuit Design 2nd Edition. Norwell, MA: Kluwer,1999. [10]Cadence Design Systems, http://www.cadence.com/.

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978-1-4673-1627-9/12/$31.00 ©2012 IEEE

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