III-V FET Channel Designs for High Current Densities and Thin Inversion Layers

rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

Mark Rodwell University of California, Santa Barbara

Coauthors:

W. Frensley: University of Texas, Dallas

S. Steiger, S. Lee, Y. Tan, G. Hegde, G. KlimekNetwork for Computational Nanotechnology, Purdue University

E. Chagarov, L. Wang, P. Asbeck, A. Kummel, University of California, San Diego

T. BoykinUniversity of Alabama, Huntsville

J. N. SchulmanThe Aerospace Corporation, El Segundo, CA.

2010 IEEE Device Research Conference, June 21-23, Notre Dame, Indiana

Acknowledgements: Herb Kroemer (UCSB), Bobby Brar (Teledyne) Art Gossard (UCSB), John Albrecht (DARPA)

Thin, high current density III-V FET channels

InGaAs, InAs FETsTHz & VLSI need high currentlow m*→ high velocities

Density of states bottleneck (Solomon & Laux IEDM 2001)

→ For < 0.6 nm EOT, silicon beats III-Vs

FET scaling for speed requires increased charge densitylow m* →low charge density

Open the bottle !

low transport mass → high vcarrier

multiple valleys or anistropic valleys → high DOSUse the L valleys.

Simple FET ScalingGoal: double transistor bandwidth when used in any circuit

→ reduce 2:1 all capacitances and all transport delays

→ keep constant all resistances, voltages, currents

)/(~/ gggsgm WLCvWg

ggggsggs LLWCWC )/(/

~/, gfgs WC

~/ ggd WC

. ),/( ),/( , )/( doublemust wespeed, double To D sgggsggm nWLCWIWg

must increase gate

capacitance/area

must reduce

gate length

gate-source, gate-drain

fringing capacitances:

0.15-0.25 fF/mm

laws in constant-voltage limit:

FET Scaling Laws

GW widthgate

GL

FET parameter change

gate length decrease 2:1

current density (mA/mm), gm (mS/mm) increase 2:1

channel 2DEG electron density increase 2:1

electron mass in transport direction constant

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel density of states increase 2:1

source & drain contact resistivities decrease 4:1

Current densities should double

Charge densities must double

Changes required to double device / circuit bandwidth.

Semiconductor Capacitances Must Also Scale

inversiondepth /Tc

oxc

)( thgs VV

2*2 2/ gmqcdos

)2/()()(charge channel 2* gmEEqVVcqn wellfwellfdoss

motion) onalunidirecti(

scale. both alsomust states ofdensity & thicknessInversion

qEE wellf /)(

Calculating Current: Ballistic Limit

fvv )3/4( velocity electron mean

2/3

2/3

,

2/1

V 1)/*()/(1

)/*(

m

mA 84

thgs

ooxodos

oVV

mmgcc

mmgJ

m

minima band of # theis where, )/*(2/* ,

22 gmmgcgmqc oodosdos

thgs

dosequiv

equivdos

cfdos VVcc

ccVVc

s :charge Channel

2/* through velocity Fermidetermines

toapplied voltage voltage FermiChannel

2

ffff

dos

vmqVEv

c

Do we get highest current with high or low mass ?

Natori

InGaAs MOSFETs: superior Id to Si at large EOT.

InGaAs MOSFETs: inferior Id to Si at small EOT.

2/3*

,

2/1*

1

2/3

1

)/()/(1 where,

V 1m

mA84

oequivodos

othgs

mmgcc

mmgK

VVKJ

m

Drive current versus mass, # valleys, and EOT

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

no

rma

lized

drive c

urr

en

t K

1

m*/mo

g=2

EOT=1.0 nmEOT includes the wavefunction depth term

(mean wavefunction depth*SiO2

/semiconductor

)

0.6 nm

0.4 nm

g=1

InGaAs <--> InP Si

0.3 nm

/EOTε

)/c/c(c oxequiv

2SiO

1

depth

11

Solomon / Laux Density-of-States-Bottleneck → III-V loses to Si.

2/1*

,

2/1

0

*

2

2/1

72 1 whereVolt 1

cm/s 1052.2

oeq

odos

thgs

g

D

chch

m

mg

c

c

m

mK

VV

LK

I

Q

Transit delay versus mass, # valleys, and EOT

0

0.5

1

1.5

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

No

rma

lize

d t

ran

sit d

ela

y K

2

m*/mo

EOT=1.0 nm

EOT includes wavefunction depth term

(mean wavefunction depth*SiO2

/semiconductor

)

0.6 nm

0.4 nm

g=1, isotropic bands

g=2, isotropic bands

1 nm

0.4 nm

0.6 nm

/EOTε

)/c/c(c oxequiv

2SiO

1

semi

11

Low m* gives lowest transit time, lowest Cgs at any EOT.

Low effective mass also impairs vertical scaling

Shallow electron distribution needed

for high Id, high gm / Gds ratio,

low drain-induced barrier lowering.

./ 2*2

wellTmL

Only one vertical state in well.

Minimum ~ 3 nm well thickness.

→ Hard to scale below 10-16 nm Lg.

For thin wells,

only 1st state can be populated.

For very thin wells,

1st state approaches L-valley.

Energy of Lth well state

substrate material

III-V Band Properties, normal {100} Wafer

X L

valleys tocomparable are masses nsversevalley tra-L

eV 0.28 0.075 1.90

eV 0.57 0.050 0.65

eV 0.47 0.062 1.23

/ /

valley L

EEmmmm Lotol

Si Si

GaAs GaAs

InP InAs

InP AsGaIn

substrate material

0.50.5

---

0.067

0.026

0.045

/

valley

*

omm

(negative) 0.19 0.92

eV 0.47 0.22 1.30

eV 0.87 0.16 1.13

eV 0.83 0.19 1.29

/ /

valley

EEmmmm

X

xotol

substrate material

Consider instead: valleys in {111} Wafer

X L

---

0.067

0.026

0.045

/

valley

*

omm

(negative) 0.19 0.92

eV 0.47 0.22 1.30

eV 0.87 0.16 1.13

eV 0.83 0.19 1.29

/ /

valley

EEmmmm

X

xotol

eV 0.28 0.075 1.90

eV 0.57 0.050 0.65

eV 0.47 0.062 1.23

/ /

valley L

EEmmmm Lotol

Si Si

GaAs GaAs

InP InAs

InP AsGaIn

substrate material

0.50.5

mass verticalmoderate have valleys L three& valleysX

mass verticalhigh has valley Lone :nOrientatio

substrate material

Valley in {111} wafer: with quantization in thin wells

X L

mass erselow transv valley; L[111]Selects

---

0.067

0.026

0.045

/

valley

*

omm

(negative) 0.19 0.92

eV 0.47 0.22 1.30

eV 0.87 0.16 1.13

eV 0.83 0.19 1.29

/ /

valley

EEmmmm

X

xotol

eV 0.28 0.075 1.90

eV 0.57 0.050 0.65

eV 0.47 0.062 1.23

/ /

valley L

EEmmmm Lotol

Si Si

GaAs GaAs

InP InAs

InP AsGaIn

substrate material

0.50.5

eV 0.07 0.10 1.30

eV 0.28 0.075 1.90

eV 0.47 0.062 1.23

/ /

valleyL

EEmmmm Lotol

GaSb

GaAs

AsGaIn

material

0.50.5

---

nm 4

nm 2

(?) nm 1

alignment L

for thickness Well

material

{111} -L FET: Candidate Channel Materials

Ge

GaSb

GaAs

AsGaIn

material

0.50.5

0.039

0.067

0.045

/

valley

*

omm

(negative) 0.08 1.58

eV 0.07 0.10 1.30

eV 0.28 0.075 1.90

eV 0.47 0.062 1.23

/ /

valleyL

EEmmmm Lotol

Standard III-V FET: valley in [100] orientation

3 nm GaAs wellAlSb barriers

=0 eV

L=177 meVX[100]= 264 meVX[010] = 337 meV

-1

-0.5

0

0.5

1

1.5

2

LE

ne

rgy,

eV

X[010]X[100]L

Wa

ve

fun

ctio

ns

-1

1st Approach: Use both and L valleys in [111]

-1

XL[111]

L[111]

L[111]

L[111]

-1

2.3 nm GaAs wellAlSb barriers[111] orientation

= 41 meVL[111] (1)= 0 meVL[111] (2)= 84 meV

L[111] , etc. =175 meVX=288 meV

2/3*

,

2/1*

1

2/3

1

)/()/(1 where,

V 1m

mA84

oequivodos

othgs

mmgcc

mmgK

VVKJ

m

Combined -L wells in {111} orientation vs. Si

2 nm GaAs /L well→ g =2, m*/m0=0.07

4 nm GaSb /L well→ m*/m0=0.039, mL,t*/m0=0.1

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.01 0.1 1

Norm

aliz

ed

curr

ent

density K

1

m*/mo

g=2

EOT=1.0 nmEOT includes the wavefunction depth term

(mean wavefunction depth*SiO2

/semiconductor

)

0.6 nm

0.4 nm

GaAs Si

0.3 nm

GaSb

combined ( -L) transport

/EOTε

)/c/c(c oxequiv

2SiO

1

semi

11

2nd Approach: Use L valleys in Stacked Wells

Three 0.66 nm GaAs wells0.66 nm AlSb barriers [111] orientation

L[111](1) = 0 meVL[111](2)= 61 meVL[111](3)= 99 meV

=338 meVL[111], etc =232 meVX=284 meV

-1

X

L[111]L[111]

All

L[111]

-1

Increase in Cdos with 2 and 3 wells

1

1.5

2

2.5

3

0.01 0.1 1

1 nm well pitch2 nm well pitch3 nm well pitch

Cd

os,N

-well/C

do

s,1

-we

ll

m*/mo

2 wells

3 wells

3 High Current Density (111) GaAs/AlSb Designs(111) orientation

-1

-0.5

0

0.5

1

1.5

2

L

En

erg

y,

eV

X[010]X[100]L

-1

XL[111]

L[111]

L[111]

-1

XL[111]L[111]

L[111]

-1

X

L[111]L[111]

Wa

ve

fun

ctio

ns

-1

L[111]

-1

both L[111]

-1

All

L[111]

-1

0 1 2 3 4 5 6 7

0 100

2 1019

4 1019

6 1019

8 1019

1 1020

Cha

rge

de

nsity,

1/c

m3

position, nm0 1 2 3 4 5 6 7

position, nm0 1 2 3 4 5 6 7

-1

position, nm0 1 2 3 4 5 6 7

-1

position, nm

0

2 1012

4 1012

6 1012

8 1012

-0.2 -0.1 0 0.1 0.2 0.3

Ns (

1/c

m2)

(Vgs

-Vth

), V

L valleys filling

-0.2 -0.1 0 0.1 0.2 0.3

0

(Vgs

-Vth

), V-0.2 -0.1 0 0.1 0.2 0.3

0

(Vgs

-Vth

), V-0.2 -0.1 0 0.1 0.2 0.3

0

(Vgs

-Vth

), V

3 nm GaAs wellAlSb barriers

2.3 nm GaAs wellAlSb barriers

Two 0.66 nm GaAs wells0.66 nm AlSb barriers

Three 0.66 nm GaAs wells0.66 nm AlSb barriers

(100) orientation

Concerns

Nonparabolic bands reduce bound state energies

1-2 monolayer fluctuations in growth→ scattering→ collapse in mobility

Failure of effective mass approximation:1-2 nm wells

Purdue Confirmation

Purdue Confirmation Steiger, Klimeck, BoykinRyu, Lee, Hegde, Tan

1-D FET array = 2-D FET with high transverse mass

Weak coupling → narrow transverse-mode energy distribution→ high density of states

2-D FET 1-D Array FET

3rd Approach: High Current Density L-Valley MQW FINFETs

0

1

2

3

4

5

6

7

8

0.01 0.1 1

Dra

in c

urr

ent, m

A/m

m

m*/mo

Vgs

-Vth=0.3 V

0.3 nm EOT0.6 nm EOT

EOT includes wavefunction depth term

(mean wavefunction depth*SiO2

/semiconductor

)

5 nm well pitch

2.5 nm well pitch

2

2*

22

min,min,2

energiesvalley iWm

qVE ii

i

if VVgq

I min,

2

current

i

min,

*2 :charge ifch VVqmgl

Q

oxchfgs CQVV / : voltagegate

4th Approach: {110} Orientation→ Anisotropic Bands

locitycarrier vehigh transport toparallel mass plane-in Low

states ofdensity high transportlar toperpendicu mass plane-inHigh

populate valleysmass verticalmoderate: ]1L[11 [111], L

locitycarrier ve low transport toparallel mass plane-inHigh

depopulate mass verticallow :11]1[ 1],1[1 L

valleys.undesired and desiredbetween separationenergy moderateonly :Challenge

transport

Asbeck P.

2/32/1

||

2/1

,

2/12/1

1

2/3

1

)/()/(1

)/( where,

V 1m

mA84

oequivodos

othgs

mmmgcc

mmgK

VVKJ

m

Anisotropic bands, e.g. {110}

0

0.1

0.2

0.3

0.4

0.5

0.6

0.01 0.1 1

no

rma

lized d

rive c

urr

en

t K

1

m*/mo

EOT=1.0 nm

EOT includes wavefunction depth term

(mean wavefunction depth*SiO2

/semiconductor

)

0.6 nm

0.4 nm

g=2, mperpendicular

/m0=0.70.3 nm

g=2, m perpendicular

/m0=0.6

g=2, m perpendicular

/m0=0.5

Transport in {110}

oriented L valleys

1.58/ ,081.0/ ,2 :Ge 1.9/ ,075.0/ ,2 :GaAs

nsport valley tra-L with MOSFETs {110} Ge and GaAs

olotolot mmmmnmmmmn

/EOTε

)/c/c(c oxequiv

2SiO

1

semi

11

THz FET scaling: with & without increased DOS

Gate length nm 50 35 25 18 13 9

Gate barrier EOT nm 1.2 0.83 0.58 0.41 0.29 0.21

well thickness nm 8.0 5.7 4.0 2.8 2.0 1.4

S/D resistance Wmm 210 150 100 74 53 37

effective mass *m0 0.05 0.05 0.05 0.08 0.08 0.08

# band minima

canonical

fixed DOS

stepped #

1

1

1

1.4

1

1

2

1

1

2.8

1

2

4

1

3

5.7

1

3

Scaled FET performance: fixed vs. increasing DOS

0

500

1000

1500

2000

2500

3000 canonical scaling

stepped # of bands

transport only

f ,

GH

z

0

500

1000

1500

2000

2500

3000

3500

4000

f ma

x,

GH

z

0

0.5

1

1.5

2

2.5

0 10 20 30 40 50 60

dra

in c

urr

ent

density,

mA

/mm

gate length, nm

200 mV gate overdrive

0

200

400

600

800

1000

0 10 20 30 40 50 60

SC

FL

sta

tic d

ivid

er

clo

ck r

ate

, G

Hz

gate length, nm

f fmax

mA/mm→ VLSI metricSCFL divider speed

Increased density of states needed for high drive current, fast logic @ 16, 11, 8 nm nodes

10 nm / 3 THz III-V FETs: Challenges & Solutions

gate dielectric:decrease EOT 2:1

S/D access regions:decrease resistivity 2:1

channel: keep same velocity, butthin channel 2:1increase density of states 2:1

S/D regrowthWistey et alSingisetti et al

L

To double the bandwidth:

(end)

Purdue Confirmation

MOSFET Scaling Laws

circuitarbitrary an in bandwidth increased 1:for required Changes

:laws scalingvelocity -constant / voltage-Constant

parameter law parameter law

gate lengthg

L , source-drain contact lengths

DSL

/(nm)

1 gate-channel capacitance chg

C

1]/1/1/1[ DOSsemiox

CCC (fF)

1

gate width g

W (nm) 1 transconductance ginjectionchgm

LvCg /~

(mS) 0

equivalent oxide thickness oxideSiOoxeq

TT /2

(nm)

1 gate-source, gate-drain fringing capacitances

gfgsWC

, ,

ggdWC (fF)

1

dielectric capacitance eqggSiOox

TWLC /2

(fF) 1 S/D access resistances s

R , d

R (W ) 0

S/D contact resistivity gs

WR / , gd

WR / ( mmW ) 1

inversion thickness 2/~wellinv

TT (nm) 1 S/D contact resistivity c

( 2mmW ) 2

semiconductor capacitance

invggsemisemiTWLC / (fF)

1 drain current )(~thgsmd

VVgI (mA) 0

DOS capacitance 2*2 2/

ggDOSWLnmqC (fF)

1 drain current density ( mmA/m ) 1

electron density s

n (-2cm ) 1 temperature rise (one device, K) 1~

gW

2.0 nm GaAs well, AlAs barriers, on {111} GaAs

0

0.2

0.4

0.6

0.8

1

1.2

10-10

10-9

10-8

Bo

un

d s

tate

ene

rgy,

eV

well thickness, meters

L(l) valley

valley

. nm 7-5 ~at ticselectrosta good wellnm 2

doubles minima band two

locitycarrier ve high*low

075.0/ : l) L(067.0/* :

populated. bothminima L(l)and : wellnm 2

*

lateral

g

dos

oo

L

c

m

mmmm

GaSb well, AlSb barriers, on {110} GaSb

0

0.1

0.2

0.3

0.4

0.5

0.6

10-10

10-9

10-8

GaSb well, AlSb barriers, on (110) GaSb

Bo

un

d s

tate

en

erg

y,

eV

well thickness, meters

L [111],

L[11-1]

L [1-11],

L[-111]

X [001]

X [100],

X[010]