implementation of digital front end processing algorithms with portability across multiple...
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Implementation of Digital Front End Processing Algorithms with Portability Across Multiple Processing Platforms
September 20-21, 2011
John Holland, Jeremy W. Horner, Randy Kuning, David B. Oeffinger
Northrop Grumman CorporationP.O. Box 1693
Baltimore, Maryland [email protected]
High Performance Embedded Computing (HPEC) Workshop 2011
Copyright 2011 Northrop Grumman Corporation. All Rights Reserved.
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1) Requirements & CapabilitiesDetermine system algorithm
requirements
Evaluate candidate hardware
2) Establish Trade SpaceCritical system requirements
Limitations on implementation
A Process for Implementing Algorithms Across Hardware Platforms
Can use this process with any algorithm and implementation
Architecture Development Process
Requirements & Capabilities Establish Trade Space Partitioning Trade Final Architecture Selection
Alg
orit
hmS
yste
mT
ech
nol
ogy
Operations, Data Dependancies, and Processing Timeline
Cost: Size, Weight, Power, NRE
Benefit: Resources: (Logic, Memory, I/O)Performance: Clock Frequency
Concept of Operations, Reliability, Survivability, Affordability
Develop and Rank Evaluation Criteria
If required, Request Requirements Relief
Identify Technology Limitations
Eliminate Technologies that violate System Requirements
Identify Candidate Architectures that map the Algorithm Requirements into the Technology Resources
Cost/Benefit Analysis:
Maximizing Technology Resources within Technology Limitations will minimize cost
Select Architecture from Candidates Based on Established Evaluation Criteria and System Cost/Benefit Analysis
3) Partitioning Trade
Partition the architecture into technologies
4) Final Architectural Selection
Copyright 2011 Northrop Grumman Corporation. All Rights Reserved.
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Example: Digital Beamforming
• Digital Beamforming– Architecture elements: time delays, phase
shifts, synchronization– Key Parameters: number of channels,
number of beams, signal bandwidth, data bandwidth
• Hardware Implementation Options– Devices: ASIC, FPGA, multi-core
processors, GPUs– Boards:
• COTS
• Custom
Each implementation option offers a unique set of capabilities and limitations
Complex Weight
Summation
Beam Output
Complex Weight
Complex Weight
Complex Weight
SubaperturePhaseCenters
Wavefront
Boresight
Desired time delays to achieve a constant phase
front
A/D A/D A/D A/D
Sample DelaySubband
Sample DelaySubband
Sample DelaySubband
Sample DelaySubband
Complex Weight
Summation
Complex Weight
Complex Weight
Complex Weight
Boresight
Desired time delays to achieve a constant phase
front
A/D A/D A/D A/D
Digital BeamformerFunctions
Digital BeamformerFunctions
Time Delay
Time Delay
Time Delay
Time Delay
Down-converter
Down-converter
Down-converter
Down-converter
θ
θ
Hardware PlatformCapabilities and
Limitations
DigitalBeamformingArchitecture
Copyright 2011 Northrop Grumman Corporation. All Rights Reserved.
4
Example Architecture:FPGAs on a Custom Board
• System Requirements– Process multiple channels
• Algorithm Requirements– Over 100 Giga-operations/second
• Trade Space Restrictions– Radiation-tolerant FPGAs
Architecture achieves a balance between capability, flexibility, and cost
Beamformer 1FPGA
(Subbands 0 - 5)
18 Channels, 6 Sub-bands
BeamA
BeamB
BeamC
BeamD
Beamformer 2FPGA
(Subbands 6 - 11)
18 Channels, 6 Sub-bands
BeamA
BeamB
BeamC
BeamD
Beamformer 3FPGA
(Subbands 12 - 17)
18 Channels, 6 Sub-bands
BeamA
BeamB
BeamC
BeamD
Beamformer 4FPGA
(Subbands 18 - 23)
18 Channels, 6 Sub-bands
BeamA
BeamB
BeamC
BeamD
• Data Dependencies– None between sub-bands
– Significant dependencies between beams
• Candidate Architectures– Minimize number of devices
– Increase number of subbands in a given device
Architecture forFPGAs on aCustom Board
Copyright 2011 Northrop Grumman Corporation. All Rights Reserved.
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Results: Beamforming Architecturesfor Land, Air, Sea, and Space
• Full Custom – ASICs and Custom Board– Minimizes power, maximizes performance
• FPGA and Custom Board– Minimizes the number of FPGAs– Maximizes resource use
• COTS Modular Processor – Open system architecture using off-the-shelf
hardware.
• COTS and Advanced Processors– Highly programmable
An adaptable design process allows algorithm portability across platforms
Full Custom Digital Beamformer
COTS ModularProcessor Beamformer
Copyright 2011 Northrop Grumman Corporation. All Rights Reserved.