increasing the efficiency of grid-connected power-electronic...

Simon Ravyts

power-electronic invertersIncreasing the efficiency of grid-connected

Academic year 2015-2016Faculty of Engineering and ArchitectureChair: Prof. dr. ir. Jan MelkebeekDepartment of Electrical Energy, Systems and Automation

Master of Science in Electromechanical EngineeringMaster's dissertation submitted in order to obtain the academic degree of

Counsellor: Dimitar BozalakovSupervisors: Dr. ir. Bart Meersman, Prof. dr. ir. Lieven Vandevelde

Permission to use

The author gives permission to make this master dissertation available for consultation

and to copy parts of this master dissertation for personal use. In the case of any other

use, the copyright terms have to be respected, in particular with regard to the obligation

to state expressly the source when quoting results from this master dissertation.

Simon Ravyts, 23 May 2016

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vi Chapter 0. Permission to use

Preface

After six years of study, the end has finally arrived. It wasn’t always as easy but I am glad

that I haven’t given up. During these past years, I developed a passion for electrical power-

and electronic engineering. This thesis combines aspects of both fields and was therefore

perfectly suited for my preferences.

At first, I would like to thank Prof. dr. ir. Lieven Vandevelde for the opportunity to

carry out this research. I would also like to thank him for his interesting courses on the

construction of electrical machines and electrical grids. I would like to thank dr. ir. Bart

Meersman for his clear vision on this project and for proofreading all the chapters. His

managerial capabilities come in very handy for all the projects that he is involved in. But

the person whom I thank the most for the success of this project is ir. Dimitar Bozalakov.

Since his lab setup was right next to mine, I had the opportunity to overwhelm him with

practical questions about the design of power converters. Also the original subject was his

idea and he learned me a lot about power electronics in general. Thank you, Mitko.

Besides the academic work, I owe a lot to my parents. They were always there for me to

support me and they kept believing in me during all these years. Also my beloved girlfriend

Inneke deserves a very big ’Thank you’. She kept supporting me, even if she didn’t always

get the attention she deserved during the past years. After some long and exhausting days

in the lab, she was always able to make me smile again. Thank you, darling.

And last but not least, I wish to thank Luc Lasne, Professeur Agrege at the University of

Bordeaux. He awakened my passion for power electronics during my stay in La Rochelle,

which is now already two years ago. The way he teaches and explains is clear and precise.

Merci Luc.

Simon Ravyts, 23 May 2016

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viii Chapter 0. Preface

Summary

Increasing the efficiency of grid-connected

power-electronic inverters

Simon Ravyts

Master’s dissertation submitted in order to obtain the academic degree of Master of Science

in Electromechanical Engineering Supervisors: Prof. dr. ir. Lieven Vandevelde, Dr. ir

Bart Meersman Counsellor: Dimitar Bozalakov

Department of Electrical Energy, Systems and Automation

Chair: Prof. dr. ir. Jan Melkebeek

Faculty of Engineering and Architecture

Academic year: 2015-2016

The aim of this thesis is to investigate possible manners to increase the efficiency of grid-

connected inverters. This specific type of inverters can be used to connect distributed

generation units, such as PV panels, with the distribution grid. They are usually equipped

with a split DC bus such that the neutral can be connected with the midpoint of the DC

bus. This also enables the use of active filtering techniques. PV grid-connected invert-

ers work below their nominal operating point during a considerable amount of time. The

efficiency in this region can be much lower than the nominal or peak-efficiency. Possible

solutions to increase this efficiency are investigated and proposed. The focus will lie on

reducing the switching losses, since they are a large part of the losses. Switching losses

stem from the simultaneous occurence of both a high current and a high voltage at the

commutation instant. They can be effectively reduced by adding a soft switching auxiliary

circuit (SSAC). The working principle of such a SSAC is usually based on an LC resonance.

The circuit is active for only a small amount of time and has thus only a minor influence

on the main circuit. Several of these circuits will be simulated and experimentally tested.

Also the performance of Silicon Carbide components will be evaluated.

Keywords: grid-connected inverters, soft switching, silicon carbide, efficiency improve-

ments

ix

Increasing the efficiency of grid-connectedpower-electronic inverters

Simon Ravyts

Supervisor(s): Prof. dr. ir. Lieven Vandevelde, Dr. ir. Bart Meersman, Dimitar Bozalakov

Ghent University, Faculty of Engineering and Architecture,Departement of Electrical Energy, Systems and Automation

Academic year 2015-2016

Abstract—The use of grid-connected inverters to couple distributed gen-eration (DG) units to the distribution grid is on the rise. The possibilityto support and stabilize the distribution grid makes them an attractive so-lution for the distribution system operator (DSO) as the increased level ofrenewable energy sources can lead to over-voltages and voltage unbalance.The transient response of these inverters is determined by the switching fre-quency. A fast response is necessary for the inverters to work properly. Ahigh switching frequency however, leads to a low efficiency due to the in-creased switching losses. This article proposes several methods to increasethe efficiency of grid-connected inverters. Also the possibility to increasethe switching frequency will be evaluated.

Keywords—grid-connected inverters, soft switching, silicon carbide, effi-ciency improvements

I. INTRODUCTION

GRID-CONNECTED inverters are commonly used to coupleDG units, such as PV panels, with the distribution grid. A

growing interest is noticed in literature for installations that sup-port, stabilize and increase the power quality of the distributiongrid via appropriate control techniques [1], [2], [3]. For this pur-pose, the neutral point of the load needs to be connected to themidpoint of the DC bus. In this way, currents can be injected inthe neutral to reduce the zero-sequence component. The use ofgrid-connected inverters is thus on the rise. A typical efficiencycurve of such an inverter is shown in Figure 1. The efficiency isin general relatively high, except for the low power region. Theinverters however operate during an important part of the time inthis region because nominal power is only reached round noon,

Fig. 1: PV inverter - Efficiency curve

when the solar irradiation is at its maximum.Increasing the efficiency can be done in several ways but this

paper will focus on reducing the switching losses. Three kindsof losses are present at the level of the switches: conductionlosses, switching losses and driving losses. Conduction anddriving losses are normally rather limited in the case of IGBTs.The switching losses are the most important due to the IGBTcurrent tail. They can become a problem at higher switchingfrequencies.

Switching frequencies in the range of 16-20 kHz are gener-ally applied for IGBT inverters. Higher frequencies can causethermal problems because of the excessive heat that is beingdissipated inside the component, due to the switching losses.The use of a high frequency is however very attractive sincetransformers and filters can be sized smaller. This makes thecircuit smaller and lighter, which means that the power density(or the power-to-weight ratio) increases. Also the transient re-sponse and the output waveform quality of the inverter will im-prove. If higher switching frequencies are desired, includinga soft switching auxiliary circuit (SSAC) can be advantageous.The circuit aims to reduce the switching losses by using an LCresonance that influences the voltage or current during the com-mutation instants. In this way, more favorable switching loci areachieved. A graphical representation for the switching loci incase of hard and soft switching is given in Figure 2.

Fig. 2: Switching loci

Fig. 3: Midpoint clamped soft switching auxiliary circuit [7]

Different topologies for SSAC are already proposed in liter-ature [4], [5] [6]. They differ in complexity, number of com-ponents and working principle. The first SSAC placed the LCcircuit inside the main power path. In this way, series or parallelloaded inverters or converters were created. They were load andfrequency dependent, which made the control circuit very com-plex. A newer type of SSAC places the LC circuit outside themain power path. This decreases the conduction losses in theresonant elements. The circuit is only activated just before thecommutation instant of the main power switch, via an auxiliaryswitch. They are called Zero-Voltage-Transition (ZVT) or Zero-Current-Transition (ZCT) SSAC. An important criterion is thatregular PWM operation is not disturbed as the converter can stilloperate without the SSAC. The major drawback of these SSACis that they result in a higher cost and a higher control com-plexity due to the increased number of components. They alsoreduce the reliability of the system. However, the possible ef-ficiency improvements are high and makes them worthwhile tobe investigated. Also the system’s behavior towards EMI canbe improved because the slew rate of the voltage and current iscontrolled.

II. SIMULATIONS

In this particular case of grid-connected inverters, the pres-ence of the balanced midpoint was a motivation to investigatethe midpoint clamped soft switching auxiliary circuit (MPCSSAC), proposed in [7]. The circuit is shown in Figure 3.

First the circuit was simulated via PSpice. It has been appliedto a regular Buck converter and a Buck converter with split DCbus. The load is in this case connected to the midpoint of the DCbus, instead of to the negative bar of the DC bus. This is shownin Figure 4. The simulation was done with this topology becauseit is very close to the actual grid-connected inverter where theneutral point of the load is connected to the midpoint of the DCbus. The simulation settings are given in Table I. It was noticedthat some serious over voltages were present across the auxil-iary switch. A snubber circuit was added to solve this problem.The obtained waveforms for the voltage, current and power areshown in Figure 6 and Figure 7 when the SSAC is active at turn-on. One can see a clear improvement when the SSAC is applied.The switching loss at turn-on has completely disappeared whilethe turn-off loss decreased significantly. The efficiency for a softand a hard switched Buck converter with split DC bus are shownin Figure 5. An improvement of approximately 0,5% is visibleover the complete range. Only for δ = 55% the hard switched

Fig. 4: Buck converter with split DC bus

Simulation time step 10 nsDC bus 600 V

Max. ouput power 2,5 kWMax. output current 10 A

Switching frequency fs 20 kHzMain and aux. switch IRF450Output inductor Lf 2 mHOutput capacitor Cf 5 µF

Resonant inductor Lr 22 µHResonant capacitor Cr 11 nF

Table I: Simulation settings

converter performs better. This is because the converter operatesin discontinuous conduction mode (DCM), which means that theturn-on is already under zero current. Applying the SSAC in thiscase only introduces extra losses.

III. EXPERIMENTAL VERIFICATION

A. Midpoint Clamped SSAC

The simulation showed that indeed an efficiency improve-ment is possible and therefore a test setup was built. The cir-cuit was tested for both a regular Buck converter and a Buckconverter with split DC bus, as this topology is very close to anactual grid-connected inverter. The measurement setup is shownin Figure 8. Notice the bleeder resistor that is used to stabilizethe midpoint. Better alternatives exist for this purpose (see [8])but this solution was chosen for simplicity. The unbalance of themidpoint is a consequence of the current that gets injected dur-ing the turn-off time of the transistor. During the turn-off time,

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the current flows via the lower capacitor and the free-wheelingdiode back to the load. At first, the same combination of res-onant elements was used as in simulation, being Lr = 22 µHand Cr = 11nF. The used inductor was an industrial availableSMD type with shielded core. It was however noticed that theinductor became very hot and that the soft switching conditionswere not met anymore. It was concluded that an air coil wasmore appropriate. The best combination found was Lr = 2 µHand Cr = 3.3 nF. With this combination, the zero-voltage con-ditions were easily obtained and the current peak at turn-on waslimited. The measurement results that were obtained with thetest setup are shown in Figure 9 and Figure 10. The DC busvoltage is 600 V and the efficiency is measured for a switch-ing frequency of 20 and 30 kHz. The maximum output power

of the converter is 2,5 kW for an output current of 9,5 A, theused IGBT is a IRGP30B120KDE. The red lines represent theefficiency under hard switching and the blue lines represent theefficiency under soft switching. At 20 kHz, an efficiency im-provement of 2% is visible over the complete range when theMPC SSAC is active. At 30 kHz, the hard switched converterexperienced a thermal breakdown for a duty ratio of 80%. Whenthe MPC SSAC is active, the converter is able to span the entireoperating range with an efficiency that is higher than the hardswitched efficiency. This is an important result since also theuse of snubbers was considered. Snubbers however are not ableto increase the efficiency, they only divert the losses from theswitch towards the snubber network. This option was thereforenot further investigated. The measured waveforms under hard

Fig. 8: Measurement setup - Buck converter with split DC bus

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Fig. 9: Buck converter with split DC bus - 600 V, 20 kHz

and soft switching are given in Figure 11. The DC bus voltageis 600 V and the output current is approximately 6 A.

Turn-on: A strong overlap between the collector-emittervoltage and the collector current is present in hard-switching.The switching losses are thus very high. There is also a bigcurrent peak due to diode reverse recovery. Also notice thevery high dv/dt and di/dt. When the MPC SSAC is active, softswitching conditions are clearly present. The SSAC is activatedjust before the main pulse. This makes the voltage drop in acontrolled way. The dv/dt is much lower, which is beneficialfor the EMC. The current increases when the voltage is alreadyzero. This means that the turn-on switching loss is practicallyzero. Also the current peak is much lower.

Turn-off: In hard switching the IGBT current tail is visibleduring the turn-off time. It lasts for approximately 300 ns. Sincethe voltage increases much faster, the turn-off switching lossis very high. By applying the MPC SSAC, the collector cur-rent strongly decreases before the collector-emitter voltage rises.Small oscillations are however still visible. This means that theturn-off loss is not completely zero but it is certainly stronglydecreased.

The effectiveness of the MPC SSAC has thus been proven.The SSAC is activated just before and just after the turn-on andturn-off of the main pulse. The timing of these pulses withrespect to the main pulse should be as constant as possible to

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achieve an easy control. Table II summarizes the duty cycle andthe phase shift of the turn-on and turn-off auxiliary pulses incase of the Buck converter with split DC bus, operating at 600V, 30 kHz. The duty ratio (δ) of the pulses is constant and equalto 1%. The time between the main and the auxiliary pulse isdenoted with Ton and Toff . From the table it is clear that thisadvancement is not constant. The timing of the on-pulse clearlyincreases for higher output power while the advancement of theoff-pulse decreases a little. During this investigation, the con-trol of the pulse width and timing has been done manually. Ifthe SSAC is implemented in a stand-alone version, a closed loopfeedback will be needed to check whether or not the soft switch-ing is achieved. This is again an increase in complexity. Furtherresearch is needed to check if this timing can be held constant,e.g. when other resonant elements are used. Another impor-tant remark is that the duty cycle of the SSAC is very low. Ascan be seen from Table II, it is only 1% for both the on or offpulse. The auxiliary circuit is thus applicable over a very wideoperating range.

B. Silicon Carbide

Another method to increase the efficiency of grid-connectedinverters is simply by using better components. Recently Sili-con Carbide (SiC) MOSFETS came into the market for a com-mercially acceptable price. These wide-bandgap semiconductor

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δmain δon Ton δoff Toff Pout

[%] [%] [ns] [%] [ns] [W]55 1 267 1 68,5 6260 1 333 1 68,0 18265 1 333 1 68,8 35670 1 373 1 68,3 59575 1 400 1 62,5 88680 1 400 1 68,7 124185 1 427 1 69,5 167090 1 427 1 65,0 216195 1 427 1 65,8 2533

Table II: Duty cycle and shift of the auxiliary pulses for theSSAC

devices have superior properties when compared to normal Sil-icon (Si) devices. Both the conduction losses and the switchinglosses of SiC components are very low. They were comparedwith the regular Silicon (Si) IGBTs. The results are shown inFigure 12 and Figure 13. It can be seen that the efficiency ofthe hard switched Buck converter with split DC bus using SiCMOSFETS is even higher than the regular inverter under softswitching. At 20 kHz and low duty ratios, an efficiency im-provement of more than 10% is possible. At higher duty ratios,the efficiency improvement is lower but still an increase of 5%is visible. At 40 kHz, the SiC converter still obtains a very highefficiency over the complete range. The comparison with theMPC SSAC shows that the SiC components perform better andthat they are able to span the complete operating range. The SiIGBTs with MPC SSAC experienced a thermal breakdown atδ = 80%. The performance of the newer SiC MOSFETs is thusclearly superior over the older Si IGBTs. It was however noticedthat the switching transients are very fast and can be a problemwith regard to EMI. This however requires further research toinvestigate if snubbers could improve this behavior.

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IV. CONCLUSION

Different methods to increase the efficiency of grid-connectedinverters were proposed in this article. First an introductionabout SSAC was given. Simulations were carried out for a MPCSSAC since this circuit makes use of the stabilized midpoint thatis already present in grid-connected inverters. In simulation, anefficiency increase is possible and the waveforms at turn-on andturn- off were given. An experimental setup was build to val-idate the performance of the MPC SSAC. It was shown thatthis circuit increases the efficiency by effectively reducing the

switching losses. Applying the SSAC also means that higherswitching frequencies are attainable, which enables the use ofsmaller filter equipment. The drawback is the increased numberof components, which leads to higher costs, and the higher con-trol complexity. Another proposed alternative is the use of SiCcomponents. These components have very low switching lossesand conduction losses. This was again experimentally tested ina Buck converter with split DC bus. These components performeven better than the Si components in soft switching and do notneed any auxiliary circuits. It is expected that SiC devices willshape the future of power electronics since they are clearly themost appropriate choice when a high efficiency is wanted.

REFERENCES

[1] D. Bozalakov, T. Vandoorn, B. Meersman, C. Demoulias, and L. Vande-velde, “Voltage dip mitigation capabilities of three-phase damping controlstrategy,” Electric Power Systems Research, vol. 121, pp. 192–199, 2015.

[2] D. Bozalakov, T. Vandoorn, B. Meersman, G. Papagiannis, A. Chrysochos,and L. Vandevelde, “Damping-based droop control strategy allowing an in-creased penetration of renewable energy resources in low voltage grids,”IEEE Transactions on Power Delivery, vol. PP, no. 99, pp. 1–1, 2016.

[3] D. Bozalakov, T. Vandoorn, B. Meersman, and L. Vandevelde, “Overviewof increasing the penetration of renewable energy sources in the distribu-tion grid by developing control strategies and using ancillary services,” inProceedings of the IEEE Young Researchers Symposium, p. 5, EESA, 2014.

[4] G. Hua, C. Leu, Y. Jiang, and F. Lee, “Novel zero-voltage-transition pwmconverters,” Power Electronics, IEEE Transactions on, vol. 9, pp. 213–219,Mar 1994.

[5] C.-M. Wang, “Novel zero-voltage-transition pwm dc-dc converters,” Indus-trial Electronics, IEEE Transactions on, vol. 53, no. 1, pp. 254–262, 2006.

[6] J. He, N. Mohan, and B. Wold, “Zero-voltage-switching pwm inverter forhigh-frequency dc-ac power conversion,” IEEE Transactions on IndustryApplications, vol. 29, September/October 1993.

[7] C. M. De Oliveira Stein, H. A. Grundling, H. Pinheiro, J. R. Pinheiro, andH. L. Hey, “Zero-current and zero-voltage soft-transition commutation cellfor pwm inverters,” Power Electronics, IEEE Transactions on, vol. 19, no. 2,pp. 396–403, 2004.

[8] B. Meersman, Regeling van driefasige invertorgekoppelde decentrale gen-eratoren met betrekking tot de verbetering van de netkwaliteit. PhD thesis,University of Ghent, 2012.

Contents

Permission to use v

Preface vii

Summary ix

Extended Abstract xvi

Figures xxiii

Tables xxix

Nomenclature xxxi

1 Introduction 1

1.1 Grid-connected inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Commutation and switching losses . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Literature review 7

2.1 Losses in hard switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Power diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

xvii

xviii Contents

2.1.1.1 Conduction losses . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1.2 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.2 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12



2.1.3 IGBTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14



2.1.4 Switch cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2 Driver circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Efficiency vs. switching frequency . . . . . . . . . . . . . . . . . . . . . . . 22

2.4 Inverters for grid connected power supplies . . . . . . . . . . . . . . . . . . 22

2.5 Enhancement of switching losses . . . . . . . . . . . . . . . . . . . . . . . . 26

2.5.1 RLC circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.5.2 Silicon Carbide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5.3 Snubber circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.5.4 Soft switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.5.4.1 Resonant DC link inverters . . . . . . . . . . . . . . . . . 31

2.5.4.2 Zero voltage and zero current switchings . . . . . . . . . . 32

2.5.4.3 Zero voltage and zero current transitions . . . . . . . . . . 34

Contents xix

2.6 Example: Losses of a hard switched inverter . . . . . . . . . . . . . . . . . 37

2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3 Simulations 43

3.1 Buck converter with split DC bus . . . . . . . . . . . . . . . . . . . . . . . 43

3.2 Simulation 1 - ZVT SSAC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.1 Components and simulation settings . . . . . . . . . . . . . . . . . 46

3.2.2 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.3 Buck converter with ZVT . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.4 Full leg with ZVT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3 Simulation 2 - MPC SSAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.3.1 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.3.2 Buck converter with split DC bus . . . . . . . . . . . . . . . . . . . 62

3.4 Simulation 3 - PRDCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4 Experimental verification 71

4.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.2 Measurement equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2.1 Voltage probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2.2 Current probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

xx Contents

4.2.3 Other equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.3 Switching loss measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.4 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4.1 Hard switched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.4.2 Soft switch auxiliary circuit 1 . . . . . . . . . . . . . . . . . . . . . 77

4.4.3 Soft switch auxiliary circuit 2 . . . . . . . . . . . . . . . . . . . . . 80

4.5 Buck converter with split DC bus . . . . . . . . . . . . . . . . . . . . . . . 82

4.5.1 Comparison for a 400 V DC bus . . . . . . . . . . . . . . . . . . . . 82

4.5.2 Comparison for a 600 V DC bus . . . . . . . . . . . . . . . . . . . . 85

4.5.3 Waveform analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.6 Silicon Carbide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5 Conclusion 93

A Matlab scripts 95

A.1 Calculation resonant parameters MPC SSAC . . . . . . . . . . . . . . . . . 95

A.2 Power losses - Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . 96

A.3 Power losses - Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

A.4 Determination of switching losses . . . . . . . . . . . . . . . . . . . . . . . 100

A.5 Calculation of the gate resistance . . . . . . . . . . . . . . . . . . . . . . . 104

Contents xxi

B Design considerations 107

B.1 Fundamentals of power electronics design . . . . . . . . . . . . . . . . . . . 107

B.1.1 Gate drive circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

B.2 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

B.3 PCB design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

B.4 PCB optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

B.5 Thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

B.6 Control circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

C DSP code 117

D PCB design 123

D.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

D.2 Board lay-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

D.3 Pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

E Measurements 137

F Data sheets 151

Bibliography 161

xxii Contents

Figures

1.1 Installed worldwide capacity of PV in GW . . . . . . . . . . . . . . . . . . 2

1.2 Yearly worldwide number of PV installations . . . . . . . . . . . . . . . . . 3

1.3 PV inverter - Efficiency curve . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Switching transients and power losses for a component in isolation . . . . . 10

2.2 Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Reverse recovery of a diode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Symbols of commonly used controllable switches . . . . . . . . . . . . . . . 13

2.5 IGBT structure and tail current . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Reference circuit for loss calculation . . . . . . . . . . . . . . . . . . . . . . 17

2.7 Waveforms during transition of switches . . . . . . . . . . . . . . . . . . . 18

2.8 Internal capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.9 IGBT switching behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.10 IGBT with driver circuit, gate resistance and common emitter inductance . 21

2.11 Efficiency as a function of the switching frequency . . . . . . . . . . . . . 23

2.12 Inverter topologies for grid connection . . . . . . . . . . . . . . . . . . . . 25

2.13 Series RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.14 Step response of an RLC circuit . . . . . . . . . . . . . . . . . . . . . . . . 28

xxiii

xxiv Figures

2.15 Snubber circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.16 Parallel resonant DC link inverter . . . . . . . . . . . . . . . . . . . . . . . 32

2.17 ZVS-PWM Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.18 ZCS-PWM Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.19 First implementation of a ZVT-PWM Buck converter [1] . . . . . . . . . . 35

2.20 Recently proposed soft switching auxiliary circuit [2] . . . . . . . . . . . . 36

2.21 Implementation the newly proposed SSAC in a Buck converter . . . . . . . 36

2.22 Proposed soft switching auxiliary circuit [3] . . . . . . . . . . . . . . . . . 37

2.23 Switching loci for different techniques . . . . . . . . . . . . . . . . . . . . . 40

3.1 Split DC bus topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.2 Buck converter simulation model in SPICE . . . . . . . . . . . . . . . . . . 47

3.3 Input and output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.4 Inductor, diode and MOSFET currents . . . . . . . . . . . . . . . . . . . . 49

3.5 MOSFET and diode power consumption . . . . . . . . . . . . . . . . . . . 50

3.6 Reverse recovery current effects in diode and MOSFET . . . . . . . . . . . 50

3.7 Zoom at turn-on power consumption . . . . . . . . . . . . . . . . . . . . . 51

3.8 Zoom at turn-off power consumption . . . . . . . . . . . . . . . . . . . . . 51

3.9 Buck converter with soft switching cell . . . . . . . . . . . . . . . . . . . . 53

3.10 Main MOSFET power dissipation - 5 cycles . . . . . . . . . . . . . . . . . 55

Figures xxv

3.11 Zoom on main MOSFET power dissipation - 1 cycle . . . . . . . . . . . . . 55

3.12 Aux. MOSFET power dissipation - 5 cycles . . . . . . . . . . . . . . . . . 56

3.13 Zoom on aux. MOSFET power dissipation - 1 cycle . . . . . . . . . . . . . 56

3.14 Comparison of the efficiency as a function of δ - Buck converter . . . . . . 57

3.15 Spice circuit for a full leg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.16 Graphical representation of the efficiency comparison - Full leg . . . . . . . 59

3.17 Proposed soft switching commutation cell [3] . . . . . . . . . . . . . . . . 61

3.18 Spice simulation circuit for a Buck with MPC SSAC . . . . . . . . . . . . 63

3.19 Efficiency comparison - Buck converter with and without ZVT circuit . . . 63

3.20 Efficiency comparison - Buck converter with split DC bus . . . . . . . . . . 64

3.21 Power consumption of the switch in hard switching . . . . . . . . . . . . . 65

3.22 Power consumption of the switch in soft switching . . . . . . . . . . . . . . 65

3.23 Parallel Resonant DC Link [4] . . . . . . . . . . . . . . . . . . . . . . . . 67

3.24 PRDCL simulation model in SPICE . . . . . . . . . . . . . . . . . . . . . . 68

3.25 Supplied inverter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.26 Current through the resonant inductor . . . . . . . . . . . . . . . . . . . . 69

4.1 Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2 Comparison of different current measurement techniques . . . . . . . . . . 74

4.3 Definition of the switching losses [5] . . . . . . . . . . . . . . . . . . . . . . 75

xxvi Figures

4.4 Hard switched Buck converter - Measurement setup . . . . . . . . . . . . 76

4.5 Hard switched Buck converter - Efficiency comparison . . . . . . . . . . . 77

4.6 Hard switched Buck converter - Output power . . . . . . . . . . . . . . . 77

4.7 Soft switched Buck converter - Measurement setup . . . . . . . . . . . . . 78

4.8 Efficiency comparison - 20 kHz Buck converter . . . . . . . . . . . . . . . 79

4.9 Efficiency comparison - 40 kHz Buck converter . . . . . . . . . . . . . . . 80

4.10 Soft switching auxiliary circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . 81

4.11 Voltage across diode D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.12 Buck converter with split DC bus - Measurement setup . . . . . . . . . . . 83

4.13 Efficiency comparison Buck split DC bus at 400V - 20 kHz . . . . . . . . . 84




4.17 Voltage and current waveforms . . . . . . . . . . . . . . . . . . . . . . . . 89

4.18 Efficiency comparison with SiC components - 20 kHz . . . . . . . . . . . . 90

4.19 Efficiency comparison with SiC components - 40 kHz . . . . . . . . . . . . 91

B.1 Recommended driver application circuit [6] . . . . . . . . . . . . . . . . . 113

B.2 Recommended application of the DESAT protection circuit [6] . . . . . . . 113

B.3 IGBT driving voltages (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figures xxvii

B.4 Thermal insulation tube . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

B.5 The Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . 116

D.1 PCB layout - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

D.2 PCB layout - ZVT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

D.3 PCB layout - ZVT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

D.4 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

D.5 Midpoint clamped SSAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

D.6 Soft switching auxiliary circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . 136

xxviii Figures

Tables

2.1 Comparison of RDS,on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Most important IGBT specifications . . . . . . . . . . . . . . . . . . . . . 14

2.3 Comparison between Si and SiC components . . . . . . . . . . . . . . . . . 29

2.4 Comparison of possible techniques . . . . . . . . . . . . . . . . . . . . . . . 41

3.1 Component values for simulation . . . . . . . . . . . . . . . . . . . . . . . 47

3.2 Losses in a Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.3 Resonant parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.4 Losses in a Buck converter with soft switching cell . . . . . . . . . . . . . . 56

3.5 Comparison of the efficiencies for a full leg with and without ZVT . . . . . 59

3.6 Peak current Ip in the MPC SSAC for different resonant elements . . . . . 62

4.1 Used components for the measurement setup . . . . . . . . . . . . . . . . . 76

4.2 Efficiency comparison for 20 and 30 kHz at 400 V . . . . . . . . . . . . . . 84

4.3 Efficiency comparison for 20 and 30 kHz at 600 V . . . . . . . . . . . . . . 86

4.4 Duty cycle and shift of the auxiliary pulses for the SSAC . . . . . . . . . . 88

4.5 Parameters of the SiC MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 90

B.1 Influence of gate resistance on performance [7] . . . . . . . . . . . . . . . . 109

xxix

xxx Tables

E.1 Hard switched Buck - Measurements at 10 kHz . . . . . . . . . . . . . . . 138



E.4 Buck converter with MPC SSAC at turn-on - 20 kHz . . . . . . . . . . . . 141

E.5 Buck converter with MPC SSAC at turn-off - 20 kHz . . . . . . . . . . . . 141

E.6 Buck converter with MPC SSAC at turn-on and off - 20 kHz . . . . . . . . 142

E.7 Buck converter with MPC SSAC at turn-on and off - 40 kHz . . . . . . . . 143

E.8 Buck with split DC bus 400 V - 20 kHz - hard switched . . . . . . . . . . . 144


E.10 Buck with split DC bus 400 V - 20 kHz - MPC SSAC . . . . . . . . . . . . 145






E.16 Buck with split DC bus 600 V - 20 kHz - Silicon Carbide . . . . . . . . . . 150

E.17 Buck with split DC bus 600 V - 40 kHz - Silicon Carbide . . . . . . . . . . 150

Nomenclature

Abbreviations

CCM Continuous Conduction Mode

CSV Comma Separated Value

DCM Discontinuous Conduction Mode

DG Distributed Generation

DSP Digital Signal Processor

EMC Electro Magnetic Compatibility

EMI Electro Magnetic Interference

GaN Gallium Nitride

IGBT Insulated Gate Bipolar Transistor

MOSFET Meta-Oxide-Semiconductor Field-Effect Transistor

MPC MidPoint Clamped

PCB Printed Circuit Board

PRDCL Parallel Resonant DC Link

S Switch

SiC Silicon Carbide

SMD Surface Mount Device

SMT Surface Mount Technology

SPICE Simulation Program with Integrated Circuit Emphasis

SS Soft Switching

SSAC Soft Switching Auxiliary Circuit

VSI Voltage Source Inverter

ZCT Zero Current Transition

ZVT Zero Voltage Transition

xxxi

xxxii Chapter 0. Nomenclature

Symbols

C Capacitance F

E Energy J

f Frequency Hz

I Current A

L Inductance H

P Power W

R Resistance Ω

t Time s

T Period s

V Voltage V

Q Charge C

α Attenuation constant /

δ Duty ratio /

ω Angular frequency rad

ω0 Natural pulsation rad

η Efficiency /

ζ Damping factor /

Chapter 1

Introduction

1.1 Grid-connected inverters

Power electronic inverters and converters are being used more and more in our daily life and

in industry. Renewable energy sources such as photo-voltaic (PV) panels and wind turbines

are commonly connected via so called grid-connected inverters. The worldwide installed

capacity of PV panels (in GW) is shown in Fig. 1.1 1, while the number of PV installations

is shown in Fig. 1.2 2. A growing trend is clearly visible. All these installations require one

or more inverters. Besides this, also wind turbines are usually coupled via grid-connected

inverters. The use of these inverters is thus on the rise. Care should be taken since the

increased penetration of these distributed generation (DG) units can cause problems such

as over-voltages and voltage unbalance [8]. More recently, grid-connected inverters are

being used to stabilize, support and increase the power quality of the distribution grid. As

described in [9], voltage dips can be mitigated by using an efficient three-phase damping

control strategy. Other aspects such as efficient droop control strategies [10] and the

implementation of battery systems are still being investigated. The purpose of this thesis

however, is to investigate how the efficiency of grid-connected inverters can be improved.

A high efficiency for all these devices is crucial to obtain the maximum power output of

renewable energy sources. The efficiency that can be found in the data sheet is usually

determined under full power, or it is the peak efficiency. Very high efficiencies in the range

1http://solarcellcentral.com2http://www.solarpowereurope.org

1

2 Chapter 1. Introduction

Year2009 2010 2011 2012 2013 2014

Inst

alle

d ca

paci

ty [

GW

]

0

20

40

60

80

100

120

140

160

180

200

23.00

42.60

70.30

100.40

138.80

183.80

Fig. 1.1: Installed worldwide capacity of PV in GW

of 92 - 96 % can then be reached3. An important remark is that the inverters do not

operate under full power during most of the time. A household PV installation will only

deliver it’s nominal power around noon. In the morning and in the afternoon the output

power will be lower. The efficiency curve for a ’Sunnyboy 4000’ is shown in Fig. 1.3. One

can see that a peak efficiency of almost 97% is reached. The efficiency is remarkably lower

when the output power is lower than 1.5 kW. In this thesis it will be shown that efficiency

improvements are possible, especially in this region of low output power. This can be done

in different ways but the focus will lie on reducing the switching losses.

3http://gosolarcalifornia.ca.gov/equipment/inverters.php

1.1. Grid-connected inverters 3

Year2009 2010 2011 2012 2013

Num

ber

of in

stal

latio

ns

×104

0

0.5

1

1.5

2

2.5

3

3.5

4

7340

17107

30282 29865

37007

Fig. 1.2: Yearly worldwide number of PV installations

Fig. 1.3: PV inverter - Efficiency curve


1.2 Commutation and switching losses

Throughout the years, forced commutation of power electronic switches has always been

a point of concern. It dates back to the time that thyristors were used as controllable

switches. Techniques to turn the thyristors off usually involved an auxiliary LC circuit.

This circuit was able to reduce the current below a critical value, such that the thyristor

will turn off. In the late eighties of the previous century, power MOSFETs (Metal-Oxide-

Semiconductor Field-Effect Transistor) and IGBTs (Insulated Gate Bipolar Transistor)

came into the market. They are easily controlled and the turn-off circuits, that were

required to cancel the current, are not needed anymore. The simplicity of controlling

these switches makes that they are applicable in a wide range of devices. Nowadays, the

purpose of the research has shifted. The commutation is no longer a purpose on its own

but rather an opportunity to increase the efficiency. As will be discussed in later chapters,

a big share of the losses are related to the commutation, namely the switching losses.

They are directly proportional to the switching frequency and thus to the overall size and

weight of the converters. If they can be avoided or reduced, both the efficiency and the so

called power-to-weight ratio of the device can increase significantly. A possible method to

achieve this is via soft switching cells. A large number of soft commutation techniques is

already proposed in literature. As in the past, they are usually based on an LC resonance.

A handful of them will be discussed and further investigated in this thesis. However, it

is important to note that the current state-of-the-art solution is the use of wide band-

gap semiconductors such as Silicon Carbide (SiC) and Gallium Nitride (GaN). They have

a better performance compared to the regular Silicon components. Unfortunately, their

production process still contains some errors which makes them rather expensive. They will

be treated later on as it is expected that this technology will dominate the future of power

electronics. When they become affordable, soft commutation circuits will be superfluous.

1.3 Overview

The thesis is built up in the following way: First, this chapter gave a general introduction

to the subject and pointed out the problem. In Chapter 2 , a literature study will be made

in order to understand the origins of switching losses and to investigate how to minimize

them. Several types of soft switching auxiliary circuits (SSAC) will be discussed here. The

1.3. Overview 5

focus is on the number and type of used components, complexity, load-dependency etc. At

the end of the chapter, an overview of the different techniques is given. In Chapter 3, the

most interesting solutions of the literature study are simulated using PSpice. They will

be simulated for a Buck converter and a full leg topology. The waveforms and expected

efficiencies are then examined. An important part of the thesis deals with the experimental

validation of the simulations. This is described in Chapter 4. Also the used measurement

techniques and tools are discussed. Chapter 5 contains the conclusion and the possibilities

for future work.

Chapter 2

Literature review

2.1 Losses in hard switching

In this section, an overview of the losses in semiconductor switches will be given. The

focus will be on the switching losses since these can be reduced by using soft switching

auxiliary circuits (SSAC), which is the aim of this work. Firstly, hard switching power

losses are discussed in general and afterwards the specific properties of diodes, MOSFET’s

and IGBT’s and their combination will be discussed. In general, the power losses of a

component during one cycle are given by Eqn. 2.1.

P =1

T

∫ T

0

v(t)i(t)dt (2.1)

Where:

T is one switching period

v(t) is the voltage across the component during one period

i(t) is the current through the component during one period

Usually this integral is hard to solve, since the waveforms of the voltage nor the current are

analytically known. Therefore, a distinction is made between three kinds of power losses:

7

8 Chapter 2. Literature review

Off state losses

On state losses or conduction losses

Switching losses or commutation losses

The off state losses are usually negligible compared to the other two since the leakage

current is very small. Therefore, they will not be further discussed.

The conduction losses mainly depend on the on-state voltage of the switch. In power

electronics circuit analysis, the on-state voltage of switches is mostly neglected to under-

stand the working principle of a circuit. This is an appropriate approximation since this

voltage is mostly negligible compared to the in- and output voltages of the circuit. Anyhow,

for design aspects where losses need to be taken into account, they cannot be neglected

anymore. The on-state voltage is mainly determined by the type of power switch, especially

by its internal geometry and by the current flowing through the switch. The dissipated

energy over one period can be found directly from the current flowing through the switch

Ion(t), the voltage across it during the on-state Von(t) and the conduction time ton, Eqn.

2.2. The voltage waveform is usually quite constant while the switch is conducting, so

Von(t) = Von. The current can be constant or not. If not, the best way to calculate the

conduction losses is by breaking up the interval in smaller sub-intervals where the current

can be assumed constant. Afterwards the results have to be summed. This gives more

accurate results than taking the average or RMS-value of the current [11].

Pcond(t) =1

T

∫ ton

0

Von(t).Ion(t)dt (2.2)

The switching losses stem from the simultaneous occurrence of high voltages and cur-

rents during switching. The switching losses include both the turn-on and turn-off losses.

Compared to the conduction losses, they need to be treated from a dynamic point of view

since they only occur at the transitions of the switch (ON ↔ OFF). During these time

intervals, which are usually very small, in the order of nano- or microseconds, the current

increases while the voltage over the device decreases (or vice versa). These transitions are

shown in Fig. 2.1 together with the corresponding power loss. Notice that the transitions

are supposed linear. This is generally not the case. Every type of switch has its typical

waveforms. But for the sake of simplicity, they are mostly split up in linear subintervals.

2.1. Losses in hard switching 9

Also the circuit in which the component is used, influences the switching losses. For induc-

tive loads, a diode normally commutates together with the switch. As will be shown later

on, the diode characteristics will influence the power dissipation of the switch. If nothing is

done to prevent or reduce the switching losses, this is referred to as hard switching. Several

techniques exist to reduce the switching losses, this is called soft switching.

Switching losses are directly related to the switching frequency since they occur at every

switching instant. The losses are dissipated as heat. This means that the component will

get warmer for higher switching frequencies. If the frequency is too high, the dissipated

heat cannot be removed fast enough (think at the relatively small contact surface between

the component and the heat sink) and the thermal limitations of the component will be

exceeded and it will experience a thermal breakdown. Off course, this device failure has to

be avoided at all time. This is why the thermal design of a circuit is so important. This

will be discussed later on in section B.5. With respect to Fig. 2.1, the switching losses for

one period are given by Eqn. 2.3. This equation will be elaborated later on [12], [13], [14].

Pswitch =1

2T· VDC · IL · (ton + toff ) (2.3)

Where:

VDC is the DC bus voltage

IL is the load current

ton is the turn-on time of the device

toff is the turn-off time of the device

2.1.1 Power diodes

The symbol and V-I characteristic are given in Fig. 2.2. Note that the V-I characteristic

of power diodes has a more linear behavior in the first quadrant, compared to the more

exponential behavior of signal diodes. There is a small leakage current when the diode is

reversed biased. The power loss that corresponds to it is usually neglected since it is small


Fig. 2.1: Switching transients and power losses for a component in isolation

in comparison to conduction and switching losses. Also the structure of power diodes is

somehow different from that of signal diodes. For power diodes, a drift region is added in

between the P and N substrate. The doping level of the drift layer is much smaller than the

doping of the other two layers. It’s function is to absorb the depletion layer of the reverse

biased PN junction. By doing this, the reverse voltage rating of the diode will increase

[12]. However, we will not go into any further detail in these constructional aspects since

the working principle stays exactly the same as for signal diodes.

2.1.1.1 Conduction losses

The total voltage across a forward biased diode (VD)is the sum of the junction voltage (Vj)

and the drift region voltage (Vd). For practical purposes, a diode is usually modeled as a

voltage source Vs in combination with a dynamic resistance Ron, also shown in Fig. 2.2.

The voltage across the diode VD is then given by Eqn. 2.4 and the average conduction

losses over one cycle by Eqn. 2.5. In some cases, the data sheet only provides the forward

voltage drop across the diode, VD, the conduction losses are even easier to calculate, via

Eqn. 2.6.


(a) Symbol

(b) I-V characteristic

Fig. 2.2: Diode

VD = Vs +RonID (2.4)

Pcond =1

T

∫ T

0

VDIDdt

= VsID,AV G +RonI2D,RMS

(2.5)

Pcond = VDID,AV G (2.6)

2.1.1.2 Switching losses

For low frequency applications, such as rectification of the grid voltages, diode switching

losses are often neglected. This is because the turn-on and turn-off times are extremely

small compared with the conduction time of the diode. For instance ton is in the order of

tens of nanoseconds, which is small compared to the period of the grid being 20 ms (for

f = 50 Hz). At higher frequencies the switching losses need to be included. Especially


Fig. 2.3: Reverse recovery of a diode

the turn-off needs special attention. An interesting phenomenon during turn-off that is

usually neglected in basic electronics courses is diode reverse recovery. Fig. 2.3 shows that

during a time trr, the reverse recovery time, a negative current flows through the diode.

This negative current is needed to reorganize the internal charge distribution, such that

the diode is able to block negative voltages again [12]. A low reverse recovery charge is

usually desired because the transistor losses can be reduced [15]. This will be explained

later on, in subsection 2.1.4.

2.1.2 Power MOSFETs

The symbol of an N-channel power MOSFET is shown in Fig. 2.4. MOSFETs are used

a lot in lower power applications. They can be switched on or off by applying a voltage

VGS between the gate and the source. Since they are voltage controlled, gate current will

only flow during the transitions to charge or discharge the internal gate capacitance. They

can be used for switching speeds up to 1 MHz. Their major drawback is the on-state

resistance RDS,on which increases rapidly for higher blocking voltage ratings, BVDSS. This

is why they are only used for voltages below 1 kV. Another important item is the inherent

’body diode’ of a MOSFET. This can be seen both as an advantage or a disadvantage.

It’s an advantage since no external anti-parallel diode needs to be added to the structure


(a) MOSFET symbol (b) IGBT symbol

Fig. 2.4: Symbols of commonly used controllable switches

Serial number BVDSS (V) Id (A) RDS,on (Ω)

STD30NF03L 30 19 0,025

IRFR18N15DPbF 150 13 0,125

FDPF16N50 500 16 0,380

Table 2.1: Comparison of RDS,on

anymore. It can also be seen as a disadvantage since the body diode does not always have

the required properties (e.g. soft recovery)[16].


When a MOSFET is conducting, it behaves as a resistor [13]. This resistor is usually

denoted as RDS,on and is given in the data sheet of the manufacturer. The conduction

losses are given by Eqn. 2.7. In Table 2.1, several examples of RDS,on are given. These

values can be found in the corresponding data sheet. Notice the strong relationship between

the blocking voltage BVDSS and RDS,on.

Pon = RDS,onI2D,RMS (2.7)


Serial number VCES (V) Ic (A) VCE,on (V)

ISL9V3040D3S 430 17 2,20

IRG4PH50UPbF 1200 24 2,78

IXGR16N170AH1 1700 16 6 5

Table 2.2: Most important IGBT specifications


The switching losses of MOSFETs are quite small since the turn-on and turn-off transients

are very fast. This means that ton and toff are very small, usually in the order of tens

of nanoseconds. However, the ideal switching transients will always be shorter than the

ones which are actually achieved. Therefore, the maximum data sheet parameters for ton

and toff should be used to give more realistic results [17]. As already mentioned in the

previous section, the switching losses do not only depend on the transistor itself. The circuit

in which it is placed and the diode that commutates together with it will have a significant

influence. This will be discussed in subsection 2.1.4. When no specific information about

the switching losses is given, Eqn. 2.3 can be used as a good approximation.

2.1.3 IGBTs

The symbol of an IGBT is shown in Fig. 2.4. IGBTs are the most used switching elements

in an intermediate power range (1→1000 kW). The state of the switch is determined by

the gate-emitter voltage VGE. Since they are voltage controlled, like MOSFETs, only a

small amount of power is required to switch them on or off. An IGBT’s on-state voltage

is rather small, like is the case for BJT’s. This can be seen from Table 2.2, summarizing

the most important parameters of several commercial IGBTs.


The on-state voltage of an IGBT, VCE,on, is equal to the saturation voltage between the

collector and emitter and assumed constant when conducting [11]. This means that the

conduction losses are given by Eqn. 2.8.


Pcond =1

T

∫ T

0

VCE,onIC

= VCE,onIC,AV G

(2.8)


Switching losses in IGBTs are rather high compared to diodes and MOSFETs. The major

contribution to the switching losses in an IGBT is due to a phenomenon which is called

the tail current of the IGBT. It only occurs at turn-off and is shown in Fig. 2.5. When the

device turns off, the collector current IC first decreases rapidly during time interval tf1.

This is called the MOSFET part of the turn-off. Afterwards, the decrease becomes much

smaller during a time interval tf2. This is called the BJT part of the turn-off. The length

of tf2 should be as short as possible since the voltage VCE is already at it’s blocking value,

which is usually quite high. This means that the power dissipation will be large during tf2.

The duration of the tail is usually in the range of 200 to 500 ns. The tail current cannot

be avoided since it is caused by minority carriers which are trapped in the base of the

BJT part of the IGBT, Fig. 2.5. They cannot be removed fast since there is no external

connection to this ’internal base’. The minority carriers have to recombine naturally. This

is a relatively slow process which causes the device to remain in his on-state for a longer

time. If temperature increases, the tail current will increase too [12], [18], [19].

In practice, hard switching losses are specified in the data sheet of the component. These

losses are usually referred to as Eon and Eoff and are valid under certain reference con-

ditions. If the reference conditions are not met, a linear interpolation should be applied

as described in [11]. It is also important to check whether or not the reverse recovery and

tail current losses are included. To find the power dissipation, one can simply multiply the

sum Eon + Eoff with the switching frequency, Eqn. 2.9.

Pswitch = fs · (Eon + Eoff ) (2.9)


(a) IGBT equivalent circuit (b) Tail current at IGBT turn-off

Fig. 2.5: IGBT structure and tail current

2.1.4 Switch cell

As mentioned before, the switching losses can be determined for a component as a sepa-

rate unit. However, it is more convenient to consider them for two commutating devices,

placed in a circuit. In power electronic circuits, the switched current mostly has an in-

ductive nature (e.g. Buck converter) and can therefore be considered as constant during

the switching interval. The most common and practical relevant case of a commutation

between a diode and a MOSFET/IGBT will be discussed here. This kind of commutation

is normally the one used for testing the transistor and is mostly given in the data sheet.

Consider the circuit and waveforms of Fig. 2.6. The current IL is assumed to be constant.

The transitions are assumed to be linear. Consider the following events[15]:

At first, the current IL flows entirely through the diode. The MOSFET is off.

At time t1, the MOSFET is turned on. The current IS linearly increases, while

ID linearly decreases, according to IL = IS + ID. The voltages VS and VD remain

constant, being VS = VDC and VD = VF . VF is the forward voltage drop across the

diode.

At time t2, ID becomes negative. This is due to the reverse recovery charge of the

diode. The maximum negative value of the current is called IRRM . Since IL = ID+IS

is still valid, this ’overshoot’ in the diode current is also visible in the MOSFET

current.

At t3, the diode starts to block and VD rises. VS falls during a time tB since VDC =

VD + VS


Fig. 2.6: Reference circuit for loss calculation

Finally, at t4, the transient finishes. The current that was first going through the

diode has commutated to the MOSFET.

The switching losses over one period can be calculated as follows:

Pdiode =1

6TtBVDCIRRM (2.10)

Pswitch =1

2TVDCILtr + VDC(IL +

1

2IRRM)ta + VDC(

1

2IL +

1

3IRRM)tB (2.11)


(a) Diode voltage (b) Diode current

(c) Switch voltage (d) Switch current

Fig. 2.7: Waveforms during transition of switches

2.2. Driver circuits 19

The described process is called forced commutation. The most important aspect of this

process is that the reverse recovery does not only affect the diode but also the transistor.

Let us compare a normal and a soft recovery diode with the same trr. For a soft recovery

diode, tb > ta, and for a normal diode tb << ta. The switching losses in the diode itself

will be higher for the soft recovery diode, since they are proportional to tb. But more

importantly, the losses in the transistor will be much smaller. This means that the overall

system efficiency can be improved. Other advantages of soft switching diodes are the low

dv/dt during tb and the lower IRRM compared to regular diodes. This is beneficial for the

radiated EMI and ringing losses. [13],[15]

2.2 Driver circuits

In recent years, great improvements have been made in the design of driver circuits. When

the thyristor was still the most frequently used component, driver circuits consumed a lot

of power to turn on the device, since the gate was current controlled. To shut it down, an

auxiliary circuit was needed to force the main current to zero. Nowadays huge advances

are made with voltage controlled gates for both IGBTs and MOSFETs.

The driver circuit forms the interface between the power switches and the controller. It

provides the necessary power for switching the transistors. Mostly, galvanic insulation

between the controller and the power circuit is provided. This can be done by using

transformers, optocouplers or fiber optic cables. Since the driver circuit consumes a certain

amount of energy, this is also considered as a loss. Therefore, the driving losses should

be added to the conduction and switching losses to determine the overall losses. Usually

they are relatively small compared to the total power of the inverter. Some basic driver

considerations for MOSFETs and IGBTs will be considered here. The focus will lie on

IGBTs since they will be the main switches of the inverter and the MOSFETs will serve as

auxiliary switches. At turn-on, IGBTs and MOSFETs behave in almost exactly the same

way. At turn-off, the IGBT current has the typical current tailing problem which was

already mentioned in subsection 2.1.3. This phenomenon is not observed for MOSFETs.

The insulated gate of IGBTs and MOSFETs behaves like a capacitor. Therefore, for

driving power switches, the internal capacitances between the three terminals of the device

are important. They are shown for both an IGBT and a MOSFET in Fig. 2.8. These


devices are voltage driven, which basically means that they start switching when VGE

passes a certain threshold. An important aspect of the switching waveform is shown in

Fig. 2.9. One can see that the gate voltage exhibits a step. This occurs at turn-on and

turn-off. The gate voltage remains at the same level while VCE rises or falls. This effect

is due to the Miller capacitance CGC and the voltage threshold level is called the Miller

plateau. The Miller plateau should be as short as possible. This is because the switch

is operated in linear operation and not in switch mode during this event, which basically

means an increase in switching losses. The Miller effect can be strongly reduced or even

eliminated by using zero voltage switching (ZVS) as discussed in [20].

An appropriate design can speed up or slow down the switching times. But it is important

to notice that the IGBT tail current cannot be influenced by the driver. The tail current

losses are completely independent of the driver. Only the losses due to the dV/dt can be

reduced. The driver has to be capable of delivering high dV/dt rates and high peak current.

In this way, the needed charge for switching is delivered quickly and switching times can

be reduced. Usually the driver itself can be bought separately and only some external

components need to be added. The most important one is the gate drive resistance Rg as

shown in Fig. 2.10. A low Rg is beneficial since the gate will charge more quickly. The

switching event will be shorter and switching losses will be lower. However, eliminating

Rg is not possible. There is always a certain emitter inductance present in the PCB design

and even in the IGBT package itself. This emitter inductance is called Le. Together with

CGE, this forms an LC tank circuit. If no or very little gate resistance is present, the

circuit will start to oscillate when a voltage step is applied. The transistor will turn ON

and OFF several times, which will cause high losses. Another problem is that the voltage

across Le is subtracted during turn-on and added during turn-off. This slows down the

switching. Therefore, Le should be kept as low as possible by using wide PCB tracks and

locate the driver as close as possible to the IGBT gate. By doing so, Rg can be optimized

and be as low as possible. It is also important to mention that the optimum gate resistance

can be different for turn-on and turn-off. For high inductive loads, the turn on resistance

should be relatively high to reduce turn-on spiking. However, it is usually too high for fast

turn-off. To overcome this problem, the resistor is split up in 2 parts and an anti-parallel

diode is placed across one of them. This creates a short circuit over one of the resistors,

which speeds up the turn-off. [7], [18], [21], [22].

2.2. Driver circuits 21

(a) IGBT (b) MOSFET

Fig. 2.8: Internal capacitances

(a) Turn on (b) Turn off

Fig. 2.9: IGBT switching behavior

Fig. 2.10: IGBT with driver circuit, gate resistance and common emitter inductance


2.3 Efficiency vs. switching frequency

As seen in the previous paragraphs, the losses can be split up in different parts [19]:

1. Switching losses Psw

For Etot being the total energy lost in the switching transitions of one switching pe-

riod, the average switching losses Psw can be found by multiplying with the switching

frequency fs: Psw = Etot · fsw

2. Conduction losses Pcond

3. Driver losses Pdriver

The total losses Ploss are then given by:

Ploss = Etot · fs + Pcond + Pdriver (2.12)

One can see that the total losses are thus determined by a constant term and a term that

linearly increases with fs. The critical frequency fcrit is defined as the frequency at which

the switching losses are equal to the constant losses:

fcrit =Pcond + Pdriver

Etot(2.13)

Below fcrit, the losses are mainly determined by driver and conduction losses. Above fcrit,

the losses are mainly switching losses and the efficiency decreases rapidly with increasing

fs. This typical phenomenon is shown in Fig. 2.11 where fcrit = 14, 4 kHz.

2.4 Inverters for grid connected power supplies

Voltage source inverters (VSI) that are intended for motor drive applications usually only

have three legs and do not use any filters. The neutral point of the motor is not connected

since this could generate the flow of a zero-sequence current and the filtering is done by

2.4. Inverters for grid connected power supplies 23

Switching frequency fs [Hz]

102 103 104 105 106 107

Eff

icie

ncy η

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

fcrit

= 14.4kHz

Fig. 2.11: Efficiency as a function of the switching frequency

the inductive behavior of the motor. This basically means that the line current will be

approximately sinusoidal while the line voltages still contain lots of higher harmonics. The

same topology (three phase VSI) can be applied for grid connected inverters. However, in

many cases a slightly different version is used. Grid-connected inverters usually contain

four legs and a filter in between the grid and the inverter. This is because the neutral point

of the load needs to be connected. The advantage is that currents can be injected in the

neutral, which may be necessary if the zero-sequence component needs to be reduced. The

fourth leg can either contain two extra switches or two capacitors. These frequently used

topologies are shown in Fig. 2.12. The first one uses a fourth leg with two extra switches.

The inductor Ln is placed in between the midpoint and the neutral point of the grid for

filtering purposes. The second topology is called a ’split DC bus inverter’. The DC bus

is split up in two parts by using two capacitors in series. The neutral point of the grid

is connected to the midpoint. Notice that no neutral filter is used in this configuration

since the fourth leg does not participate in the switching. The split DC bus inverter is

usually preferred since only six instead of eight switches are used. Furthermore, it can be

considered as three half-bridge inverters which will be an advantage for the current control.

It’s major drawback is the DC bus voltage which has to be chosen a lot higher. Also the

required voltage control over the two capacitors is an undesired feature. [23]

The extra leg might seem to be a disadvantage at any time. This is not always the case.


Certain soft switching circuits also require a split DC bus. It is thus an advantage if this

midpoint is already present in the device.

2.4. Inverters for grid connected power supplies 25

(a) Using two extra switches

(b) Using a split DC bus

Fig. 2.12: Inverter topologies for grid connection


2.5 Enhancement of switching losses

The use of a high switching frequency can be very beneficial. It decreases the size of trans-

formers and filter components. This makes the circuit smaller and lighter, which means

that the power density increases. Also the transient response, which may be important

for control purposes, is faster. For VSI applications, the output waveform quality will

increase, which leads to fewer harmonics in the line current spectrum. The drawbacks

of a high switching frequency are the increased switching losses and an increased electro-

magnetic interference(EMI). In this part, possible solutions will be discussed that enhance

switching or reduce switching losses. A comparison between the different possibilities will

be made at the end of this section.

2.5.1 RLC circuits

Most soft switching applications rely on the effects that are caused by an LC resonance.

Therefore, the basics of RLC circuits will be reviewed. Especially the behavior of DC RLC

circuits is important since the resonance circuits are usually placed on the DC bus of the

inverter or converter.

Consider the series RLC circuit shown in Fig. 2.13 . The equation that describes this

system can be found via Kirchoff’s voltage law (KVL):

V = VR + VL + VC (2.14)

Fig. 2.13: Series RLC circuit

2.5. Enhancement of switching losses 27

Filling in the constitutive equations leads to:

V = Ri(t) + Ldi(t)

dt+

1

C

∫ t

0

i(t)dt (2.15)

Via differentiation of both parts, this can be rewritten as:

0 =d2i(t)

dt2+R

L

di(t)

dt+

1

LCi(t) (2.16)

This is a second-order linear differential equation with constant coefficients. Usually this

result is rewritten in a more general form:

0 =d2i(t)

dt2+ 2α

di

dt+ ω2

0i(t) (2.17)

In which:

α = R2L

is the attenuation constant

ω0 = 1√LC

is the natural pulsation of the system

The solution of this equation is given by:

i(t) = A1es1t + A2e

s2t (2.18)

Where A1, A2 are determined by the boundary conditions and where s1 and s2 are the

solutions of the characteristic equation:

0 = s2 + 2αs+ ω20 (2.19)

s1,2 = −α±√α2 − ω2

0 (2.20)

Depending on the values of R, L and C the system’s transient response will be different

and can be determined via ζ = αω0

= R2

√CL

, the damping factor:

ζ < 1: Under damped

ζ = 1: Critically damped

ζ > 1: Over damped


Time [s] ×10-40 1 2 3 4 5 6 7 8

Vol

tage

[V

] / C

urre

nt [

A]

-100

-80

-60

-40

-20

0

20

40

60

80

100

Current IVoltage V

L

Fig. 2.14: Step response of an RLC circuit

In our case, R will be usually very small since it is the Equivalent Series Resistance (ESR)

of both L and C. Therefore, the response will be under damped. This case is shown in

Fig. 2.14 where both the current i(t) (black) and the voltage across the capacitor vc(t)

(red) are shown for a step of 100 V. The parameters are: R = 0.5 Ω, L = 33 µH and C =

1 µF. Both waveforms are in anti-phase because VL = Ldidt

. The current eventually dies

out since the capacitor gets fully charged.

2.5.2 Silicon Carbide

A first possible method to increase the switching frequency, without having excessive losses,

is simply by using better components. Present day, Silicon (Si) is the most used semicon-

ductor material. A new upcoming and improved semiconductor is Silicon Carbide (SiC).

The benefits of SiC compared to Si are discussed below, [24], [25].

SiC devices have a lower on-resistance compared to Si devices. This results in lower

conduction losses.

SiC devices have higher reverse breakdown voltages.


Product number Type Reverse voltage (VR) Forward current (IF ) Forward voltage drop (VF ) Price (¤)

DSR6V600D1 Ultrafast recovery rectifier diode - Si 600 6 3,0 0,56

SCS106AG Schottky barrier diode - SiC 600 6 1,5 9,49

Table 2.3: Comparison between Si and SiC components

SiC has a higher thermal conductivity.

The allowable junction temperatures of SiC are much higher. Today, SiC can operate

with temperatures up to 350 C, whereas Si is limited to 150 C.

The reverse recovery current of SiC devices is much lower compared to Si based

devices. This means that the switching losses are strongly reduced.

It may be clear from the previous arguments that in a near future, SiC will probably

replace Si as the standard semiconductor material used in power electronics applications.

It is estimated that a reduction of 40 % in weight and volume will be possible. Anyhow,

their biggest disadvantage is the very high price. An example is given in Table 2.3 where

the price of the SiC component is almost 17 times as high. This big price difference is due

to the high costs in the fabrication process of SiC. Present day techniques do not allow

a commercially acceptable price. Another disadvantage is the higher control complexity.

E.g. SiC MOSFETs need a +20V/-5V driving circuit. However, these constraints will be

eliminated over time, making SiC devices the future of power electronics. By using these

components, the need for auxiliary circuits will be eliminated.

2.5.3 Snubber circuits

In low power applications (< 100 W), snubbers are often used to provide damping , limit

dI/dt or dV/dt and ’reduce’ the switching losses. The term is put between brackets since

these circuits mostly only shift the problem. The switching losses are not dissipated in

the switch but are diverted to extra components which are placed in parallel to it. The

snubber circuit does not effectively reduce the switching losses. A possible snubber used for

diodes and IGBT’s is shown in Fig. 2.15. More complicated topologies exist but they are

not able to effectively increase the efficiency. For example, in [26], efficiency can increase

with 1% but only under full load conditions. We will not go in any further details since

this is clearly not an attractive solution.


(a) Snubber for diodes(b) Snubber for IGBTs

Fig. 2.15: Snubber circuits

2.5.4 Soft switching

Soft switching is a technique that shapes the voltage and current waveforms in such a way

that the switching transitions occur under favorable conditions. The device stresses are

strongly reduced by these zero voltage or zero current switchings. This purpose can be

achieved in many ways. Some of them will be more suited than others. Using soft switching

techniques is usually a must in high frequency applications, since otherwise the component

would heat up too much. The drawbacks differ from case to case but are mostly situated

in the following areas:

Higher conduction losses

More passive components, mainly diodes, capacitors and inductors

Extra active components

Higher circuit control complexity

Lower robustness, degraded reliability

Also the total cost of the circuit increases. However, if properly applied, the benefits are

considerable since the switching frequency can be increased:


Lower switching losses

Lower switching stresses due to more favorable switching loci

Smaller filtering equipment

Smaller transformers

Smaller heat sinks

Less EMI due to lower dv/dt and di/dt

Lower acoustic noise

Since transformers, filters and heat sinks are usually quite large and heavy, these advance-

ments will lead to a lighter and more compact design. This enables a higher power density

and a higher efficiency [12].

Most soft switching circuits are designed for PWM DC-DC converters. The topologies

that exist for inverters are rather limited. But, this will not be a problem. As will be

explained in more detail in Chapter 3, the split DC link inverter can be thought of as six

buck converters in parallel / anti-parallel. This allows us to use the same soft switching

topologies for the DC-AC inverter as the ones that are used for DC-DC converters.

2.5.4.1 Resonant DC link inverters

Resonant DC link inverters shift the resonant circuit from the inverter bridge to the DC bus

[27]. Series Resonant DC Link (SRDCL) inverters were the first ones being used. They

employed a resonant inductor-capacitor circuit between the DC source and the inverter

bridge to supply a resonating voltage across the inverter. Their major drawback is that

the resonating voltage can exceed twice the DC bus voltage. This means that the blocking

voltage of the switches needs to be increased. Several circuits exist to overcome this problem

but they all suffer from reliability problems [28], [29]. Also a special control strategy is

needed to establish the same initial conditions for each switching cycle. Another possible

type are the parallel resonant DC link inverters (PRDCL), Fig. 2.16. Several designs of

this type are proposed and investigated in [4] and [30]. However, also the PRDCL inverters

have some important drawbacks:


Fig. 2.16: Parallel resonant DC link inverter

Three extra switches and three extra diodes. The power rating of these auxiliary

components is comparable to the power rating of the main switches. This means a

significant increase in the overall cost of the inverter.

Increased complexity. Current control is needed before the resonant cycle can be

initiated.

Very high conduction losses in the resonant link.

A decrease of the fundamental output voltage due to the notches in the line-to-line

voltages. This is because the resonance takes a finite amount of time.

Due to these limitations, resonant DC link inverters have never known a real breakthrough

and will probably never be a commercial success. [4], [31]

2.5.4.2 Zero voltage and zero current switchings

Resonant inverters place LC networks in between the load and the switch network. These

are called ’tank networks’. Series LC, parallel LC and LCC filters are all possible. By


Fig. 2.17: ZVS-PWM Buck converter

adding them to the circuit, series or parallel loaded resonant converters are created. They

provide an oscillating load voltage and/or current which leads to zero voltage or zero

current switchings (ZVS/ZCS). A possible implementation of a ZVS-PWM converter is

shown in Fig. 2.17. ZVS is preferred for power MOSFETs that are used at high operating

frequencies. This is because ZVS eliminates the capacitive turn-on loss and it reduces the

turn-off switching loss by slowing down the voltage rise and reducing the overlap between

the switch voltage and switch current [32]. This circuit achieves soft switching for both

transistors and allows a bidirectional power flow. However, the peak current through the

transistor increases. Because of this, conduction losses can increase up to 40%. Another

drawback is that the frequency needs to be changed in order to achieve the ZVS over a wide

load range. This makes the optimization of filters, transformers etc. more difficult. Due

to these limitations, the ZVS-PWM converters are only used in some specific applications.

For example, the full bridge ZVS-PWM converter where no auxiliary switch is needed.

For IGBTs, zero current switching (ZCS) is more effective for reducing switching losses at

high switching frequencies. This is because the ZCS forces the current to zero before the

switch voltage rises. A possible topology for a Buck converter is shown in Fig. 2.18. It

achieves ZCS for the transistor and ZCS for the diode. But several drawbacks arise. The

voltage stress of the diode doubles. Due to parasitic ringing, circulating energy is present,

which increases the conduction losses. The zero current switching is also very sensitive to

changes of the line voltage and of the load. [32]


Fig. 2.18: ZCS-PWM Buck converter

2.5.4.3 Zero voltage and zero current transitions

Zero voltage and zero current transition (ZVT/ZCT) converters were developed to minimize

the disadvantages of ZVS and ZCS converters. In the previous type, the resonant element

is placed in the main power path. This leads to the aforementioned shortcomings such

as circulating energy, additional voltage stresses and dependency on line voltage and load

current. If the resonant elements are placed outside the main power path, the auxiliary

switch can be sized much smaller. This resonance network is called a soft switching auxiliary

circuit (SSAC) and is placed in shunt across the switch. The SSAC is only active during

a small time interval, when it creates the transition conditions for the main switch. A

possible implementation of a ZVT SSAC is shown in Fig. 2.19, applied to a Buck converter

[1]. The resonance is created by closing the auxiliary switch Sa. An important feature is

that, after the transient has finished, the circuit goes back to its normal operating mode.

This means that a regular PWM control can still be applied for the main switch Sm. The

key features are summarized below:

Soft switching of both the main switch and the diode. The auxiliary switch is hard

switched. However, the power rating of the auxiliary switch is relatively small com-

pared to the power rating of the main switch. This means that the overall switching

losses of the converter still decrease.

Low switching stresses on the switches since the switching loci are very beneficial.


Fig. 2.19: First implementation of a ZVT-PWM Buck converter [1]

Soft switching is achieved over almost the whole load range of the inverter. Also the

dependency on the line voltage is very low.

This SSAC was created in 1993. In the meanwhile, other circuits have emerged that solved

the shortcomings of the aforementioned topology. An interesting circuit is proposed in

[2]. The circuit and its implementation in a Buck converter are shown in Fig. 2.20 and

Fig. 2.21. In this SSAC, all active and passive semiconductor devices turn on and off with

ZVS. The auxiliary switch is operated under ZCS conditions. There are no additional

voltage or current stresses for the main switch. The circuit uses two switches, four diodes,

two resonant inductors and two resonant capacitors. The auxiliary switch has a small

power rating compared to the main switch. This SSAC is clearly one of the best possible

solutions for reducing the switching losses. Therefore, the cell will be discussed more in

detail in Chapter 3.

However, also other ZVT SSAC are available. Fig. 2.22 shows a possible configuration that

is used for inverters, proposed in [3]. It is called a MidPoint Clamped (MPC) SSAC since

a split DC bus is required for its operation. This midpoint is usually a disadvantage for


Fig. 2.20: Recently proposed soft switching auxiliary circuit [2]

Fig. 2.21: Implementation the newly proposed SSAC in a Buck converter

2.6. Example: Losses of a hard switched inverter 37

Fig. 2.22: Proposed soft switching auxiliary circuit [3]

VSI that are intended for motor applications. For grid-connected inverters, the midpoint

is already available since it is needed for voltage unbalance compensation. Notice that only

a small amount of components is needed (two switches, two diodes, two inductors and two

capacitors). The circuit can be used for both the top and bottom switch of an inverter leg.

For three-phase applications, three SSAC need to be applied with a separate control. This

means that the control is relatively easy. This topology also seems an attractive solution

and will therefor be further developed in Chapter 3.

2.6 Example: Losses of a hard switched inverter

In this section, the losses of a hard switched three-phase inverter are estimated. The

following items are given:

IGBT and free-wheeling diode in one package, IRGP30B120KD-E

DC bus voltage, VDC = 850V

Peak output power per phase, Pmax = 4kW

Minimum RMS voltage of the grid, Vmin = 207V

Switching frequency, fs = 20kHz


Unity power factor

From the modulation strategy, the maximum duty cycle per period is δmax = 0, 7

and thus m = 0,7

Only the losses for one transistor of one leg will be calculated. At the end, the result can

be extended for three legs. The IGBT data sheet can be found in Appendix F. First, the

maximum RMS collector current needs to be determined from the maximum output power

and the minimum output voltage:

Ic,RMS,max =PmaxVmin

=4000W

207V= 19, 32A

The total switching losses for a junction temperature of 125 C can be found from the data

sheet: Etot = 4436µJ . This value already includes the diode reverse recovery and tail

current losses. However, this value is specified for a collector current Ic = 25A and a DC

bus voltage of VDC = 600V . So it needs to be recalculated for this application. A linear

approximation is used:

Etot,new = Etot,old ·V DC

VDC,datasheet· Ic,RMS,max

Ic,datasheet

= 4436µJ · 850V

600V· 19, 32A

25A

= 4857µJ

By multiplying this result with the switching frequency fs, the switching losses are deter-

mined:

Pswitching = Etot,new · fs = 4857µJ · 20kHz = 97, 1W

For calculating the conduction losses we refer to [33] and [34], where a formula is given to

determine the conduction losses of inverters based on the output current and modulation

coefficient under the following assumptions:

2.7. Conclusion 39

Linear modulation of the inverter (0 5 m 5 1)

Switching times are neglected

Constant junction temperatures (valid for a fundamental output frequency of 50 Hz)

Ripple of the output current Io is negligible

Linear characteristics of the components in the forward conduction region: VCE =

VCE,0 +RCE · IC (IGBT) and VD = VD,0 +RD · ID (diode)

Pcond,diode =1

2(VD,0 ·

Io,pπ

+RD ·I2o,p4

)−m · cos(φ) · (VD,0 ·Io,p8

+1

3π·RD · I2o,p)

= 3.22 W

Pcond,IGBT =1

2(VCE0 ·

Io,pπ

+RCE ·I2o,p4

) +m · cos(φ) · (VCE0 ·Io,p8

+1

3π·RCE · I2o,p)

= 17.54 W

This leads to a total power dissipation of Ptotal = 117.86 W. This is approximately equal

to the maximum power dissipation of the casing, being 120 W at 100 C, as taken from

the data sheet. Notice that the switching losses account for 82,3 % of the total losses. If

they could be eliminated or strongly reduced, the total power dissipation will be more than

halved. Or, another approach is to reduce them while increasing the switching frequency.

This means that the heat sink stays at the same size but the filter components can be

reduced.

2.7 Conclusion

As can be seen from the example, switching losses are the main part of the losses in an

inverter. They increase linearly with the switching frequency. The switching frequency is

usually chosen as high as possible. This is done to reduce the size and weight of inductors


Fig. 2.23: Switching loci for different techniques

and transformers such that the power density of the device can be increased. This trade-

off between switching losses and switching frequency is one of the major concerns for

the design of a power electronic circuit. It has been shown that the type of switch, the

switching frequency, the freewheeling diode and the driver determine the total switching

losses. To reduce the switching losses, several methods such as snubbers, Silicon Carbide

components and soft switching techniques have been proposed. The switching loci for

these methods are shown in Fig. 2.23 . One can see that the soft switching techniques

have the best switching loci, which is translated in low switching stresses and good EMI

performance. Table 2.4 gives a comparison of the different techniques, based on several

important criteria such as the number of components, the cost and the complexity of the

circuit. Therefrom, it should be clear that, to the present day, soft switching techniques are

still the most valuable solution. Their greatest disadvantage is the relatively high number

of components that is needed per switch. However, it is possible that in the near future,

SiC components become cheaper and therefore more interesting to use.

Also notice that list of described soft switching techniques is not meant to be exhaustive.

Several other possibilities that exist are described in [27] but only the most interesting ones

for this specific case are presented here.

2.7. Conclusion 41

SiC Snubber RDCL ZVS/ZCS ZVT 1 ZVT 2 MPC

Effectiveness ++ −− + ++ + ++ ++

N of comp. ++ - + + −− −− +

Cost −− + + + - −− +/-

SS for all comp. NA −− - - - ++ ++

Control complexity - + - + - - -

Switching loci - - + + ++ ++ ++

Load dependency ++ + - −− ++ ++ ++

Influence on regular circuit NA + - −− ++ ++ ++

Power rating aux. switches NA NA High High Low Low Low

Table 2.4: Comparison of possible techniques

Chapter 3

Simulations

In this chapter, the ZVT circuits that have been discussed in Chapter 2 will be further

elaborated. Three simulations have been done and will be discussed in detail. This discus-

sion is important for the further development since only the most interesting soft switching

auxiliary circuits (SSAC) will be experimentally tested.

3.1 Buck converter with split DC bus

The proposed examples until now were all adopted for Buck converters. This has been done

intentionally since a three-phase inverter is in fact an extension where Buck converters are

placed in parallel/ anti-parallel. In this section, a Buck converter with split DC bus will

be analyzed. The transfer function of this converter is different from the transfer function

of a regular Buck converter. Therefore, we will derive it first. The relation between the

in- and output voltages of a regular Buck converter can be easily found by integrating the

voltage over the inductor over one switching period, T . Since the converter is analyzed in

steady state, this integral equals zero.

∫ T

0

vLdt =

∫ ton

0

vLdt+

∫ T

ton

vLdt = 0 (3.1)

43

44 Chapter 3. Simulations

After developing this equation, the well known result for a Buck converter is found, Eqn.

3.2 where δ is the duty ratio, defined as ton/T

VoutVin

= δ (3.2)

The behavior is different in case of the split DC bus, when compared to a regular Buck

converter. Consider the circuit of Fig. 3.1. The following assumptions are made:

The voltage across the two capacitors is evenly distributed and constant

The output voltage is assumed constant

The transistor and the diode are ideal switches

The converter is analyzed in steady state

The transfer function can again be found by integrating the inductor voltage over one

switching period.

∫ T

0

vLdt = 0 =

∫ ton

0

vLdt+

∫ T

ton

vLdt

=

∫ ton

0

(Vin − Vout)dt+

∫ T

ton

(−Vin − Vout)dt

= (Vin − Vout)ton − (Vin + Vout)(T − ton)

(3.3)

So the transfer function is given by Eqn. 3.4.

VoutVin

= 2δ − 1 (3.4)

This result has been verified by simulations in PSPICE. Only a slight difference (1%) in

the output voltage was observed due to the losses in the diode and in the transistor and

the above derivation is thus valid. The importance of this adapted circuit, stems from the

fact that it is the closest converter possible to the inverters with split DC bus and neutral

connection, as described in Chapter 2. The analogy is also shown in Fig. 3.1. If a SSAC

3.1. Buck converter with split DC bus 45

works correctly in case of the Buck converter with split DC bus, we also know that it will

work in case of a grid-connected inverter with split DC bus. A positive consequence is that

the simulations become less complex. The circuit will be tested for different duty ratios in

between 0,55 ≤ δ ≤ 0,95.

(a) Buck converter with split DC bus

(b) Three-phase inverter with split DC bus

Fig. 3.1: Split DC bus topologies


3.2 Simulation 1 - ZVT SSAC 1

This section contains the results of the simulations of the different topologies with and

without ZVT. The circuits are implemented in PSpice via Orcad Capture. The post-

processing has been done via Matlab and Microsoft Excel. It is important to notice that

the purpose of the simulations is a qualitative approach of the problem. It has to be shown

that ZVT conditions occur and that, despite the increased number of components, the

total efficiency of the system increases. It is not the aim to predict the exact efficiency

improvements. This is also not possible since the components that will be used are not yet

determined.

Also notice that the simulations use MOSFETs as main power switches, where the actual

design of an inverter can be with MOSFETs or IGBTs. A positive consequence is the

increased simulation speed. An IGBT is a more complex component in SPICE compared

to a MOSFET and as a consequence it slows down the entire simulation process. As

mentioned before, the turn-on behavior of MOSFETs and IGBTs is comparable, where

as the turn-off of IGBTs is usually more energy consuming due to the IGBT tail current

problem.

3.2.1 Components and simulation settings

Throughout all simulations, the same components are used such that the results can be

easily compared. They are given in Table 3.1. It is also important to notice that the passive

components are assumed ideal. This means that an inductance will be modeled as a simple

inductance, without any parasitic capacitance or resistance. They are assumed linear, so

the saturation and hysteresis are neglected. The same holds for the capacitors that will be

modeled without parasitic inductance or resistance. This is off course not entirely correct.

However, in this first design stage, the components that will be used are not selected yet,

it is best practice to exclude them from the simulation because it is impossible to allocate

an appropriate value. The main contribution will be a decrease in efficiency due to the

resistance. It is however possible that they are included in later simulations when the

appropriate components have been chosen.

The simulation itself is always a transient analysis with a maximum step size of 10 ns.

3.2. Simulation 1 - ZVT SSAC 1 47

Input voltage Vin 425 V

MOSFET IRF450

Diode MUR450

Filter inductance Lf 2 mH

Filter capacitance Cf 5 µF

Gate resistance Rg 10 Ω

Driving voltage 15 V

Switching frequency fs 50 kHz

Table 3.1: Component values for simulation

Fig. 3.2: Buck converter simulation model in SPICE

This is small enough compared to a switching frequency fs of 50 kHz which corresponds

to a period Ts of 20 µs The efficiency analysis is done via Matlab by using trapezoidal

integration over an integer multiple of switching periods.

3.2.2 Buck converter

At first, a regular Buck converter is simulated. The circuit is shown in Fig. 3.2, and the

voltages, currents and power consumption over 3 periods for a duty cycle δ = 60% are

shown in Fig. 3.3, Fig. 3.4, Fig. 3.5, respectively. The results are as expected. The input


voltage is constant, while the output voltage contains a small ripple of approximately 1 V.

This is due to the finite output capacitance. The inductor current contains a DC value of

approximately 10 A and a ripple of approximately 1 A peak-to-peak.

The inductor current rises during 60 % of the time. This is when the MOSFET is on. The

inductor current then equals the MOSFET current. While the MOSFET is off (during

40% of the time), the inductor current equals the diode current. The most important phe-

nomenon for our case arises when the MOSFET is turned on. One can then observe a peak

in the MOSFET current as shown in Fig. 3.6. This is due to the diode reverse recovery.

The diode current becomes negative and has a peak of −76 A. When going back to zero,

an overshoot of 48 A occurs before the current goes back to zero. These waveforms are also

found in the MOSFET current since the currents are related via IL = ID + IM . Where

IL can be assumed constant since the time interval of the reverse recovery is very short.

However, these large currents will lead to a lot of dissipation as can be seen in the Fig. 3.5

which shows the power dissipation at the same instant for the diode and the MOSFET.

One can clearly see the peaks in the power dissipation during turn-on and turn-off of the

MOSFET. These peaks are related to the switching losses of the device and are clearly

much higher than the conduction losses. From the figure, it can be seen that the conduction

losses of the MOSFET are equal to 29 W and the conduction losses of the diode equal 14 W.

Fig. 3.7 and Fig. 3.8 show the turn-on and turn-off in more detail. The turn-on has a

peak power consumption of almost 40 kW for the MOSFET and a peak of 3 kW for the

diode. However, this phenomenon takes less than 0.1 µs which means that the total energy

dissipation is rather limited. The turn-off power dissipation in the MOSFET contains a

peak value of about 4.5 kW while no peak is observed for the diode. So the total energy

dissipation of one switching action is rather limited due to the very small time intervals

that are involved. However, it may be clear that the occurrence of these phenomena is

directly related to the switching frequency. A higher switching frequency thus means more

switching losses, which deteriorates the efficiency.


×10-35 5.01 5.02 5.03 5.04 5.05 5.06

Vol

ts [

V]

424

424.5

425

425.5

426Input voltage V

in

Time [s] ×10-35 5.01 5.02 5.03 5.04 5.05 5.06

252

253

254

255

256

257Output voltage V

out

Fig. 3.3: Input and output voltages

×10-35 5.01 5.02 5.03 5.04 5.05 5.06

8

10

12Inductor current I

L

×10-35 5.01 5.02 5.03 5.04 5.05 5.06

Cur

rent

[A

]

0

5

10

Diode current ID

Time [s] ×10-35 5.01 5.02 5.03 5.04 5.05 5.06

0

5

10

Mosfet current IM

Fig. 3.4: Inductor, diode and MOSFET currents


×10-35 5.01 5.02 5.03 5.04 5.05 5.06

Pow

er c

onsu

mpt

ion

[W]

×104

-2

0

2

4Power consumption - Mosfet

Time [s] ×10-35 5.01 5.02 5.03 5.04 5.05 5.06

-10000

-5000

0

5000Power consumption Diode

X: 0.00502Y: 3.656e+04

X: 0.005032Y: 4392X: 0.005004

Y: 29.08X: 0.005014Y: 0.1708

X: 0.005004Y: 5.344e-06

X: 0.005015Y: 13.94

Fig. 3.5: MOSFET and diode power consumption

×10-35.02 5.0200 5.0200 5.0200 5.0200 5.0200 5.0201 5.0201 5.0201 5.0201 5.0201

Cur

rent

[A

] -100

-50

0

50

100Diode current I

D

Time [s] ×10-35.02 5.0200 5.0200 5.0200 5.0200 5.0200 5.0201 5.0201 5.0201 5.0201 5.0201

-100

0

100Mosfet current I

M

Fig. 3.6: Reverse recovery current effects in diode and MOSFET


×10-35.02 5.0200 5.0200 5.0200 5.0200 5.0200 5.0201 5.0201 5.0201 5.0201 5.0201

×104

-2

0

2


Time [s] ×10-35.02 5.0200 5.0200 5.0200 5.0200 5.0200 5.0201 5.0201 5.0201 5.0201 5.0201

Pow

er C

onsu

mpt

ion

[W]

-10000

-5000

0

5000Power consumption - Diode

Fig. 3.7: Zoom at turn-on power consumption

Time [s] ×10-35.05 5.0505 5.051 5.0515 5.052 5.0525 5.053 5.0535 5.054 5.0545 5.055

Pow

er C

onsu

mpt

ion

[W]

-5

0

5

10

15Power consumption - Diode ×10-3

5.05 5.0505 5.051 5.0515 5.052 5.0525 5.053 5.0535 5.054 5.0545 5.0550

2000

4000


Fig. 3.8: Zoom at turn-off power consumption


δ [/] Win [J] Wout [J] WMOS [J] WD [J] η [/]

0,1 0,0884 0,0775 0,0094 0,0015 0,8768

0,3 0,6902 0,6586 0,0281 0,0036 0,9541

0,5 1,8619 1,804 0,0529 0,0050 0,9689

0,7 3,6028 3,5122 0,0884 0,0025 0,9748

0,9 5,9072 5,7714 0,1387 -0,0029 0,9770

1 7,1409 7,0585 0,0828 2,46E-08 0,9885

Table 3.2: Losses in a Buck converter

The losses in the different components, together with the total efficiency η are summarized

in Table 3.2 for different values of δ. The different losses are always measured over 1 ms.

Notice the negative value for WD that is probably a consequence of numerical errors during

the simulation. The abbreviations have the following meaning:

Duty cycle δ

Input energy Win

Output energy Wout

MOSFET energy losses WMOS

Diode energy losses WD

Total efficiency of the converter η

3.2.3 Buck converter with ZVT

The next circuit that will be simulated is a Buck converter with soft switching cell. The

aim is to reduce the switching losses. The SPICE circuit is shown in Fig. 3.9. At first, the

parameters of the resonant network being Lr1, Lr2, Cr1 and Cr2 will be calculated using the

following equations:

nC =Cr2Cr1

(3.5)


Fig. 3.9: Buck converter with soft switching cell

nL =Lr2Lr1

(3.6)

Lr1 =Z0

2πfr(3.7)

Cr1 =Lr1Z2

0

(3.8)

where Lr1 Resonant inductance 1

Lr2 Resonant inductance 2

Cr1 Resonant capacitance 1

Cr2 Resonant capacitance 2

nL Inductance ratio

nC Capacitance ratio

fr Resonant frequency

Z0 Characteristic impedance


Z0 40 Ω

fr 229.7 kHz

Lr1 30 µH

Lr2 10 µH

Cr1 16 nF

Cr2 2.2 nF

Ton,aux 2.176 µs

Tdelay,main 1.1 µs

Table 3.3: Resonant parameters

To easily obtain soft switching conditions, [2] proposes to use Z0 = 40 Ω and fr = fs/0.35.

These parameters can however be tweaked via simulation for our purposes. For a first try-

out, the values as proposed by [2] will be used. Also the timing between the two on-signals

of the converter are important. The auxiliary switch is started first and has a pulse-width

determined by the LC resonant parameters Lr1 = 30 µH and Cr1 = 16 nF. The resonant

frequency is then given by:

fr =1

2π√Lr1 · Cr1

= 229.7 kHz (3.9)

The auxiliary switch is only ON during one half of the resonant period. The pulse-width

of the aux. switch then becomes:

Ton,aux =1

2fr= 2.176 µs (3.10)

The on-signal of the main switch is chosen such that the aux. pulse is symmetrical about

the starting pulse of the main switch. The delay of the main switch with respect to the

aux. switch is then given by:

Tdelay,main =Ton,aux

2= 1.1 µs (3.11)

The above values are summarized in Table 3.3. They are plugged into the simulation

file and the results showing the power consumption are plotted in Fig. 3.10, Fig. 3.11,

Fig. 3.12, Fig. 3.13. By looking at the power consumption of the main MOSFET, one

can conclude that the purpose of soft switching has been achieved. Under hard switching

conditions (Fig. 3.5), the turn-on power consumption peaked to 36 kW and the turn-off to

4.4 kW. When the SSAC is applied (Fig. 3.10), the turn-on peak has totally disappeared


Time [s] ×10-34 4.01 4.02 4.03 4.04 4.05 4.06 4.07 4.08 4.09 4.1

Pow

er [W

]

-300

-200

-100

0

100

200

300

400

500

Fig. 3.10: Main MOSFET power dissipation - 5 cycles

Time [s] ×10-34 4.002 4.004 4.006 4.008 4.01 4.012 4.014 4.016 4.018 4.02

Pow

er [W

]

-300

-200

-100

0

100

200

300

400

500

X: 0.004008Y: 36

X: 0.004013Y: 431.7

X: 0.004016Y: 0.1708

Fig. 3.11: Zoom on main MOSFET power dissipation - 1 cycle

while the turn-off peak is reduced to 0.45 kW. This is clearly a big improvement. However,

the major drawback is the increased number of components, that also add to the total

losses. As shown in Fig. 3.12, the switching losses of the auxiliary MOSFET are not

negligible. They have a peak of 2 kW. So the critical question is: Has the total efficiency

of the converter been improved or not? The efficiency of the regular Buck converter was

already calculated in the previous section. The same calculation has been done for the

Buck converter with soft switching cell and the results are summarized for different duty

ratios (δ) in Table 3.4. A graphical representation of the results is given in Fig. 3.14. It is

clear that, even with the extra losses in the soft switching cell, the total efficiency of the

converter rises. The biggest improvements are noticeable for lower duty ratios, whilst the

efficiencies converge for higher duty ratios.


Time [s] ×10-34 4.01 4.02 4.03 4.04 4.05 4.06 4.07 4.08 4.09 4.1

Pow

er [W

]

-1000

-500

0

500

1000

1500

2000

Fig. 3.12: Aux. MOSFET power dissipation - 5 cycles

Time [s] ×10-34 4.002 4.004 4.006 4.008 4.01 4.012 4.014 4.016 4.018 4.02

Pow

er [W

]

-1000

-500

0

500

1000

1500

2000

X: 0.004014Y: -0.07919

X: 0.004002Y: 1887

Fig. 3.13: Zoom on aux. MOSFET power dissipation - 1 cycle

δ [/] Win [J] Wout [J] WMOS,main [J] WMOS,aux [J] η [/]

0,1 0,2075 0,1944 0,0013 0,0074 0,9369

0,3 0,9284 0,9038 0,0042 0,0123 0,9735

0,5 2,2116 2,1682 0,0130 0,0204 0,9804

0,7 4,0463 3,9733 0,0310 0,0314 0,9819

0,9 6,4149 6,3004 0,0625 0,0432 0,9821

1 7,1423 7,0605 0,0808 0,0004 0,9885

Table 3.4: Losses in a Buck converter with soft switching cell


Duty ratio δ [/]0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1

Eff

icie

ncy η

[/]

0.86

0.88

0.9

0.92

0.94

0.96

0.98

1

Buck

Buck with ZVT

Fig. 3.14: Comparison of the efficiency as a function of δ - Buck converter

3.2.4 Full leg with ZVT

The original field of application of the used soft switching cell are DC/DC converters (Buck,

Boost, . . . ). However, the intention of this thesis is to use the cell in an inverter (DC/AC).

Therefore, the soft switching cell needs to be applied for both the upper and lower tran-

sistor in a full leg configuration. The obtained circuit is shown in Fig. 3.15, where now

the Buck converter is made between the mid-point and the positive DC voltage such that

the circuit can be tested for the lower transistor. The results are similar compared to the

previous case and are summarized in Table 3.5 and Fig. 3.16. This is an important result

since it means that the auxiliary circuit can be placed next to a leg of an inverter to obtain

soft switching conditions.

Also the possibility to merge the two cells of Fig. 3.15 was investigated. This however

leads to a lower efficiency increase and even an efficiency decrease in some regions. This

possibility is therefor not further investigated.


Fig. 3.15: Spice circuit for a full leg


Without ZVT With ZVT

δ [/] Win [J] Wout [J] η [/] Win [J] Wout [J] η [/]

0,1 0,1369 0,1062 0,7760 0,2383 0,2204 0,9249

0,3 0,7214 0,6779 0,9396 0,9553 0,9263 0,9695

0,5 1,8776 1,8147 0,9665 2,2331 2,1847 0,9783

0,7 3,6034 3,5125 0,9748 4,0647 3,9860 0,9806

0,9 5,8986 5,7656 0,9775 6,4154 6,2959 0,9814

1 7,1417 7,0585 0,9884 7,1426 7,0605 0,9885

Table 3.5: Comparison of the efficiencies for a full leg with and without ZVT

Duty ratio δ [/]0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Eff

icie

ncy η

[/]

0.75

0.8

0.85

0.9

0.95

1

Buck

Buck with ZVT

Fig. 3.16: Graphical representation of the efficiency comparison - Full leg


3.3 Simulation 2 - MPC SSAC

The second circuit that has been simulated is shown in Fig. 3.17. It is based on a topology

presented by [3] and is called a midpoint clamped (MPC) SSAC. As with the previous

solution, also this commutation cell is placed outside the main power path. A second

advantage is the applicability to inverters that use the capacitor midpoint, such as grid-

connected split DC bus inverters.

The design procedure to calculate the resonant elements is given in [3] and is used as a

starting point for optimization. The following parameters are defined:

Ipk is the current peak diverted from main switch to the auxiliary circuit

Ipk =E

2√

2Z(3.12)

Io,pk is the output current peak

Io,pk =

√2PoVo

(1 + ∆I) (3.13)

A parameter k is defined such that:

k =IpkIo,pk

; k ≥ 1 (3.14)

A practical value is k = 1, 1

E is the DC input voltage

Po is the output power (of one leg)

Vo is the RMS output voltage

∆I is the output current ripple

fs is the switching frequency

Z is the characteristic impedance

3.3. Simulation 2 - MPC SSAC 61

Fig. 3.17: Proposed soft switching commutation cell [3]

didt

is the rate of current change during turn-off of the main diodes:

di

dt=

Io,pkω√2 arcsin( 1

2k)

(3.15)

A practical value, suggested in [3], is 80 A/µs.

ω is the resonant tank frequency. It is determined via the didt

:

ω =didt

√2 arcsin( 1

2k)

Io,pk(3.16)

Lr and Cr are the resonant elements.

Lr =Z

ω(3.17)

Cr =1

Zω(3.18)

The above procedure has been implemented in a Matlab script that can be found in sec-

tion A.1. The input parameters are: E = 800 V, Po = 3 kW, Vo = 250 V, fs = 20 kHz,

fo = 50 Hz. The outcome is Lr = 5 µH and Cr = 30 nF.

The above result was used in simulation. However, the peak output current turned out to

be relatively high. Therefore, some other LC combinations that result in (approximately)

the same resonant frequency were tested. It turned out that the resonant current strongly

decreases in case of a higher characteristic impedance Z. This current should be as low as

possible in order to have low conduction losses and low circulating energy in the SSAC.

The results are given in Table 3.6.


Lr [µH] Cr [nF] Z[Ω] f [kHz] Ip [A]

5 30 12,9 401 50

8 20 20 398 40

33 16 45,4 219 30

12 12 31,6 419 30

18 8 47,4 419 18

Table 3.6: Peak current Ip in the MPC SSAC for different resonant elements

3.3.1 Buck converter

The first circuit that will be simulated is again a Buck converter. This means that the

load is not connected to the midpoint (see Fig. 3.17) but to the negative bar of the DC

bus. The circuit is shown in Fig. 3.18. The DC bus voltage is now chosen to be 600 V

because two identical power supplies are needed and the available EELAB power supplies

only go up to 300V. Also notice that two snubber circuits are added to the switches of

the auxiliary circuit. This was deemed necessary because some serious over-voltages were

observed during simulation. They dissipate the circulating energy that is already present

in the SSAC and thus do not introduce extra losses. The results are quite promising. In

Fig. 3.19, a strong efficiency increase is visible for lower duty ratios. For δ = 10%, an

improvement of more than 30 % is visible. The MPC SSAC is thus very effective since the

switching losses decrease significantly.

3.3.2 Buck converter with split DC bus

The next topology to be tested is again the buck converter with split DC bus as the behavior

of this converter is closest to the grid-connected inverter with a capacitor midpoint. The

results are shown in Fig. 3.20. The maximum output power is 2,5 kW for an output

current of 10 A. The DC bus voltage is 600 V. An efficiency improvement is visible over

the complete operating range. The improvement is however rather small, about 0,5%.

Only at δ = 55 % the hard switched efficiency is higher. This is because the circuit

operates in Discontinuous Conduction Mode (DCM). The turn-on then already occurs at

zero-current, including the MPC SSAC is thus not effective in this case. Fig. 3.21 and

Fig. 3.22 show the drain-source voltage, the drain current and the power dissipation of


Fig. 3.18: Spice simulation circuit for a Buck with MPC SSAC

Duty cycle0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Effi

cien

cy

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

Without ZVTWith ZVT

Fig. 3.19: Efficiency comparison - Buck converter with and without ZVT circuit


Duty cycle δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9 0,95

Eff

icie

ncy η [

/]

0,92

0,94

0,96

0,98

1

Hard switchedWith MPC SSAC

Fig. 3.20: Efficiency comparison - Buck converter with split DC bus

the MOSFET in case of hard switching and when the MPC SSAC is applied at turn-

on. In hard switching, very high peaks in the power (up to 11 kW) are visible because

the voltage and current waveforms overlap. With the MPC SSAC, these peaks disappear

almost completely. Also the dv/dt and the current slope during the commutations is much

lower, which has a positive influence on the EMC. The MPC SSAC is thus very effective

to reduce the switching losses.


×10-53.5 4 4.5 5 5.5 6

Vol

tage

[V

]

0

500

×10-53.5 4 4.5 5 5.5 6

Cur

rent

[A

]

0

10

20

30

Time [s] ×10-53.5 4 4.5 5 5.5 6

Pow

er [

W]

0

5000

10000

Fig. 3.21: Power consumption of the switch in hard switching

×10-53.5 4 4.5 5 5.5 6

Vol

tage

[V

]

0200400600

×10-53.5 4 4.5 5 5.5 6

Cur

rent

[A

]

-505

1015

Time [s] ×10-53.5 4 4.5 5 5.5 6

Pow

er [

W]

-100

0

100

200

Fig. 3.22: Power consumption of the switch in soft switching


3.4 Simulation 3 - PRDCL

The third topology that has been simulated is a Parallel Resonant DC Link (PRDCL).

This resonant circuit is placed in between the DC voltage source and the inverter as shown

in Fig. 3.23. Different implementations exist but we have chosen for the one presented

in [4]. The SPICE simulation model of this circuit is shown in Fig. 3.24. The required

number of auxiliary components is low and the voltage stress of the auxiliary components

is limited to the DC bus voltage. This is an advantage over other possible circuits where

the voltage stress may be twice the DC bus voltage. A disadvantage is that the on-time

of the auxiliary circuit is dependent on the inverter current. Current feedback is thus

required. Notice that, for the simulation, the inverter legs are replaced by an RL circuit

that represents the current that is drawn.

As shown in Fig. 3.25, the voltage that is supplied to the inverter is drawn to zero during

some finite amounts of time. The length of the zero-voltage period can be controlled via the

auxiliary switches. During this period, the main IGBTs need to be turned on. Although

this may seem an attractive solution, several concerns may arise:

The required resonant current for this circuit is plotted in Fig. 3.26. The peak value

equals almost 35 A. This very high value obviously corresponds to a high power

loss and means that the auxiliary components need to be sized quite big which also

increases the total costs. This resonant current can never be really low because it

always needs to be bigger than the current going to the inverter. In the case of a 12

kW inverter (4 kW per phase) and a DC bus of 800 V, the DC input current equals

IDC = 12 kW800V

= 15 A.

The DC bus voltage drops for a large amount of time. The consequence is a decrease

in the fundamental output voltage and extra harmonics because of the notches.

The resonant circuit can be tuned such that the voltage decreases faster. This high

dV/dt may cause EMI.

The control must be adapted such that the IGBTs are all turned on in the same

period. In this case only one resonance is needed for the three phases together. This

means an increased control complexity.

3.4. Simulation 3 - PRDCL 67

Fig. 3.23: Parallel Resonant DC Link [4]

The output current must be measured to ensure an adequate turn-on time of the

device.

These drawbacks have made that this solution was not further elaborated.


Fig. 3.24: PRDCL simulation model in SPICE

Time [s] ×10-41.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5

Vol

tage

[V

]

0

50

100

150

200

250

300

350

400

450

Fig. 3.25: Supplied inverter voltage

3.5. Conclusion 69

Time [s] ×10-41.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5

Cur

rent

[A]

-5

0

5

10

15

20

25

30

35

Fig. 3.26: Current through the resonant inductor

3.5 Conclusion

The modeling and simulation of several resonant circuits was discussed throughout this

chapter. From the advantages and disadvantages that followed from the simulation output,

results that the first and second SSAC give the best results. In both cases an efficiency

improvement is possible. Therefore, they will be examined further on and an experimental

setup will be built to verify the simulations. The disadvantages of PRDCL circuit are too

important and it will not be further investigated.

Chapter 4

Experimental verification

This chapter describes the different measurements and results that have been carried out

in order to verify the simulation results of Chapter 3. A hard switched converter will be

compared to two soft switching alternatives. Also a hard and soft switched converter using

Si IGBTs will be compared to a hard switched converter that is build with SiC MOSFETs.

4.1 Setup

A test setup has been built in order to verify the simulation results. One inverter leg

and the two auxiliary circuits have been made via Altium Designer 14.3.11. The design

procedure of the different boards is described in Appendix B. Also the choice of the

different components is discussed in this appendix. A picture of the test set-up is shown

in Fig. 4.1.

71

72 Chapter 4. Experimental verification

Fig. 4.1: Test setup

4.2 Measurement equipment

4.2.1 Voltage probes

Since the applied voltages that will be used are higher than 50 V, special care must be

taken to measure the voltages. Both the time delay as the bandwidth of the probes is an

important factor because of the very high dv/dt, possible overshoots and oscillations that

are present in power electronic converters. Regular Tektronix voltage probes (P2220) are

used when the applied voltages are below 300 V. When the applied voltages are higher,

the better insulated P5120 will be used for signals up to 1000 V. Both probes have a

bandwidth of 200 MHz. Also the probes presented in [35] were tested since they have a

high bandwidth(10 MHz). However, the time delay introduced by this equipment was too

high. This means that the voltage waveform will have a certain phase shift with respect to

the original signal. Power measurements will thus not be accurate and therefor they are

not used.

4.2. Measurement equipment 73

4.2.2 Current probes

A precise current measurement is needed such that the power losses can be estimated

appropriately. Three types of current measurement were tested:

Current sense resistor - VISHAY LVR05 0.1 Ω

The current sense resistor is cheap and reliable. The current signal will also have

the same delay as the voltage signal if it is measured by the same voltage probe. Its

major drawback is the limited current that is allowed. For a regular 5 W resistor, the

maximum RMS current is only 7.07 A. Another drawback is that it is intrusive.

Current probe - Fluke 80I-110S

The current probe has the advantage of being non-intrusive but the drawback is

the limited bandwidth of only 100 kHz and the introduced delay as will be shown

further on. The consequence of the delay is that the current measurement needs to be

time-shifted during post-processing to correspond correctly with the voltage signal.

High frequency current transformer - EELAB design

This current transformer has the same advantages as the current probe but a higher

bandwidth. The design is based on an adapted version of the current transformer

that can be found in [36]. The device is able to measure both AC as DC current whilst

the previous design was only intended for AC current measurements. It saturates

above 10 A.

The obtained waveforms are shown in Fig. 4.2. The current sense resistor and the current

transformer clearly give the best results. The signal of the current probe is delayed with

approximately 1.5 µs, which is too much for our purposes. Also the diode reverse recovery

is not present in the current probe signal. This makes it an inappropriate candidate. The

current transformer is found to be most suitable and will be used during the rest of the

experiments.

4.2.3 Other equipment

The probes will be connected to an oscilloscope with storage capabilities. This way the

data can be saved in CSV format for further processing in Matlab. The used oscilloscope is


×10-50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Cur

rent

[A

]

-10

0

10Current sense resistor

×10-50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Cur

rent

[A

]

-505

1015

Current transformer

Time [s] ×10-50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5C

urre

nt [

A]

-20246

Fluke current probe

Fig. 4.2: Comparison of different current measurement techniques

a Tektronix TPS2014 with isolated channels. Besides the equipment that is used to capture

the voltage and current waveforms, also the input and output power needs to be measured

with a high accuracy. This is done via true RMS digital multi-meters such as the Fluke 177

and the Fluke 179 in combination with shunt resistors (1mV/1A). The multi-meters are

first calibrated with a high precision tabletop multi-meter, namely the RIGOL DM3068.

4.3 Switching loss measurements

Measuring switching losses is not as straight forward as it seems to be. A variety of

standards [37] are followed by the different manufacturers. For comparative purposes,

the same method as the manufacturer needs to be chosen. In this case the measurement

method is given in the data sheet of our IGBT modules [5] and is shown in Fig. 4.3. The

turn-on losses are measured by integrating the power loss from 10% Ic to 5% Vce. The

turn-off losses are measured via integrating from 10% Vce to 5% Ic. This strategy has also

been followed in this thesis and is implemented in a Matlab script that can be found in

section A.4. This tool was developed such that an analytic comparison of the switching

losses with and without SSAC can be made. However, it will be shown later on that

the integration limits that are used in the definition of the switching losses switch sides.

4.4. Buck converter 75

(a) Turn on

(b) Turn off

Fig. 4.3: Definition of the switching losses [5]

At turn-on, the collector-emitter voltage decreases before the collector current rises. At

turn-off, the current decreases before the voltage increases. The behavior is thus totally

different when a SSAC is applied. This basically means that the integration would yield

a negative number. This is off course a worthless outcome. It means that the definition

of switching losses under hard switching is useless for soft switching. The definition or

suggestions for another standard falls beyond the scope of this thesis. This topic is treated

in more detail in [38] and [39]. The developed MATLAB script is however included since

it can be a valuable tool if switching losses need to be estimated under hard switching.

4.4 Buck converter

4.4.1 Hard switched

At first, the efficiency of a hard switched Buck converter is measured. The system is shown

in Fig. 4.4. The used components are described in Table 4.1. Notice that only the top


Fig. 4.4: Hard switched Buck converter - Measurement setup

Component Value

C1 - Electrolytic capacitor 1000 µF

C2, C3 - Film capacitor 1 µF

S1, S2 - IGBT IRG4PH40UD

R1, R2 - Shunt resistor 1 mΩ

Lf - Inductor 2.2 mH

C4 - Film capacitor 5 µF

Table 4.1: Used components for the measurement setup

IGBT is used for switching. The gate of the bottom IGBT is connected to the emitter

such that it is always off and thus works as a free-wheeling diode. The resistors R1 and

R2 are used for measuring the input and output current.

The results for different switching frequencies are shown in Fig. 4.5. The measured effi-

ciency shows very good correspondence with the results of the simulations of Chapter 3.

As expected, the efficiency drops in case of a higher switching frequency. This is explained

by the higher switching losses (Wsw ∼ fs). One can also see that the efficiency is the

lowest for low duty cycles because the relative importance of the switching losses is higher

compared to the transferred power. Also notice that the 40 kHz measurement stops at δ =

65% because the IGBTs failed during the experiment because of an excessive temperature

increase. The output power is shown in Fig. 4.6. A clear quadratic dependence is present

since Pout ∼ V 2out and Vout ∼ δ. In the following sections, the aim will be to increase the

efficiency by using soft switching auxiliary circuits (SSAC) that reduce the switching losses.


Duty ratio δ [/]0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Eff

icie

ncy η

[/]

82

84

86

88

90

92

94

96

98

100

10 kHz20 kHz40 kHz

Fig. 4.5: Hard switched Buck converter - Efficiency comparison

Duty ratio δ [/]0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Out

put p

ower

[W

]

0

500

1000

1500

2000

2500

300010 kHz20 kHz40 kHz

Fig. 4.6: Hard switched Buck converter - Output power

4.4.2 Soft switch auxiliary circuit 1

First, an experiment has been done with the midpoint clamped (MPC) SSAC, as described

in [3]. The measurement setup is shown in Fig. 4.7. This auxiliary circuit requires a split


Fig. 4.7: Soft switched Buck converter - Measurement setup

DC bus to operate. This has been achieved by using a second power source that stabilizes

the midpoint. The resistors R1, R2 and R3 are used to measure the input and output

currents. The circuit was first tested for a DC bus of 200 V to check the correct behavior

and to test different resonant parameters (Lr and Cr). The first set of parameters is Lr

= 22 µH (industrial VISHAY SMD shielded core) and Cr = 11 nF. It was however noticed

that the inductor became very hot and that the soft switching conditions were not met

anymore. It was concluded that an air coil would be more appropriate. Several inductance

values ( 1.3 µH, 2 µH and 8 µH) were fabricated and tested. Also multiple capacitors were

compared (Cr = 3.3 nF, 6.8 nF, 10 nF, 33 nF). The best results were obtained for the

combination: Lr = 2 µH and Cr = 3.3 nF. This combination was chosen because:

Zero voltage conditions are easily obtained

Current peak at turn-on is limited

Time delay of the main pulse is relatively constant

Now, the efficiency of a hard switched and a soft switched Buck converter, operating

at 20 kHz and 300 V is compared. The experimentally obtained results can be found in

Appendix E. Fig. 4.8 summarizes the results. The SSAC can be applied at turn-on, turn-

off or both. One can see that in all three cases a strong improvement is realized over the

complete range. The effect is most visible for lower duty cycles, e.g. an efficiency increase


Duty ratio δ0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Eff

icie

ncy η

0,84

0,88

0,92

0,96

1

Hard switchedSoft switched @ onSoft switched @ offSoft switched @ on + off

Fig. 4.8: Efficiency comparison - 20 kHz Buck converter

of about 6% for δ = 0,1. This is because the switching losses become more important when

the power output is lower (Pout ∼ δ2). Briefly, their relative importance is higher. A small

difference is visible when the SSAC is applied at turn-on or turn-off. The efficiency is higher

when the turn-on losses are reduced. This might not seem in accordance to intuition since,

generally spoken, the turn-off losses of IGBTs are higher due to the current tail. However,

the current tail depends on both the amplitude of the current as on the temperature of

the IGBT while the turn-on losses mainly depend on the diode reverse recovery, which is

rather constant.

Also the efficiency of a hard switched and a soft switched Buck converter, now operating

at 40 kHz and 300 V is investigated. The results are shown in Fig. 4.9. Notice that the

hard switched inverter experienced a thermal breakdown at δ = 70%, as already discussed

in subsection 4.4.1. By applying the SSAC, full range of operation is achieved and the

efficiency is increased. This means that the SSAC expands the application capabilities of

the converter while maintaining a high efficiency. This is an important conclusion since

also snubbers could have been used to extend this range. They however will never improve

the efficiency of the device.


Duty ratio δ0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Eff

icie

ncy η

0,82

0,86

0,9

0,94

0,98

BuckBuck ZVT

Fig. 4.9: Efficiency comparison - 40 kHz Buck converter

4.4.3 Soft switch auxiliary circuit 2

Not only the previous ’midpoint clamped’ SSAC had promising simulation results. It was

also proved that the SSAC shown in Fig. 4.10 is able to reduce the switching losses. An

impression of the PCB that was built can be found in Appendix D, Fig. D.6. The SSAC

was first tested for low voltages to see if it was able to provide the ZVT conditions. During

these tests, it was noticed that some serious over-voltages were present in the device.

The measured voltage across diode D3 is shown in Fig. 4.11. A voltage peak of 240 V is

present when the DC bus voltage is only 10 V. When the DC bus voltage increased to

50 V, sparks were observed that destroyed the transistor and other equipment. A possible

solution would be to add over-voltage snubbers. This option is not chosen because the

SSAC already contains a lot of components, especially when compared to the previous

SSAC. It was concluded that this circuit is not suitable for our purposes since it would

gain too much complexity. This possibility is therefor not further elaborated.


Fig. 4.10: Soft switching auxiliary circuit 2

Time [µs]0 1.0 2.0 3.0 4.0 5.0

Vol

ts [V

]

-50

0

50

100

150

200

250

Fig. 4.11: Voltage across diode D3


4.5 Buck converter with split DC bus

This section explains the results that were obtained by including the MPC SSAC to a Buck

converter with a split DC bus. This topology was theoretically discussed in Chapter 3.

The experimental setup for both hard and soft switching is shown in Fig. 4.12. Notice the

bleeder resistor R4 that is used to stabilize the midpoint of the DC bus. Better developed

systems for this purpose are described in [23]. They are more energy-efficient and can be

used for grid-connected inverters that use the midpoint of the DC bus. For this thesis,

the solution with a bleeder resistor is preferred because of the simplicity and because the

power losses that correspond to it can be easily measured. This is important since they

are needed to calculate the efficiency. R1, R2, R3 and R5 are used to measure the input

and output currents.

4.5.1 Comparison for a 400 V DC bus

At first, the circuit is tested for a DC bus of 400 V. The used IGBTs are the IRG4PH40UD,

the data sheet can be found in Appendix F. The results for switching frequencies of 20 and

30 kHz are shown in Fig. 4.13 and Fig. 4.14, respectively. Also a measurement at 40 kHz

was done but the converter failed in both hard as soft switching. This result is therefor not

included. The maximum output power of the converter is 1,7 kW, for a current of 9,5 A.

Especially at 20kHz, very high efficiency improvements are achieved in the lower current

region, for 0, 55 ≤ δ ≤ 0, 7. The average improvement in this region is roughly 8,6 %. For

30 kHz the improvement is rather constant over the complete operating area, it is in the

range of 1 to 3 %. This result is summarized in Table 4.2. It might seem counterintuitive

that the efficiency improvement at 30 kHz is lower compared to the 20 kHz case since the

switching losses are higher at 30 kHz. It should however be noted that the SSAC also

needs to be operated at 30 kHz. This means that the SSAC will consume more energy

since the conduction and switching losses of this device are not completely negligible. A

trade-off thus exists between the energy that is saved in the converter and the energy that

is consumed by the SSAC. As long as this balance is positive, the efficiency will increase

but the increase is not constant as the losses in the SSAC become more dominant.


(a) Hard switched

(b) Soft switched

Fig. 4.12: Buck converter with split DC bus - Measurement setup


δ [%] 55 60 65 70 75 80 85 90 95

20 kHz

ηhard 75,5 74,1 81,7 90,6 92,6 94,1 94,5 95,0 95,0

ηsoft 80,9 90,2 92,0 93,4 94,5 95,0 95,5 95,5 96,1

∆η 5,4 16,1 10,3 2,9 1,9 0,9 0,9 0,5 1,2

30 kHz

ηhard 74,0 85,9 89,6 91,8 92,7 93,9 94,0 93,9 93,7

ηsoft 76,9 88,6 92,0 94,0 94,9 94,8 95,1 95,1 95,1

∆η 2,8 2,7 2,4 2,2 2,1 0,9 1,1 1,3 1,4

Table 4.2: Efficiency comparison for 20 and 30 kHz at 400 V

Duty ratio δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9 0,95

Effic

ienc

y η

[/]

0,7

0,8

0,9

1

Hard switched

Soft switched

Fig. 4.13: Efficiency comparison Buck split DC bus at 400V - 20 kHz


Duty cycle δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9 0,95

Effic

ienc

y η

[/]

0,7

0,8

0,9

1

Hard switched

Soft switched


4.5.2 Comparison for a 600 V DC bus

After the successful tests at 400 V, it was decided to increase the DC bus voltage level to

600V. The used IGBTs are IRGP30B120KD-E, the data sheet can be found in Appendix F.

Due to the higher voltage, the maximum output power of the converter increases to 2,5

kW for a current of 9,5 A. The measurement setup remains the same as before.

The outcome of the experiments is shown in Fig. 4.15 and Fig. 4.16 for switching frequencies

of 20 and 30 kHz, respectively. A summary of the efficiency increase is given in Table 4.3

Similar results as in the previous paragraph are found. The improvement is again the

highest in the region of 0,65 ≤ δ ≤ 0,75. The efficiency increase is then always more

than 2 %. If we take a closer look at the 30 kHz results, one can see that the hard

switching measurements stop at δ = 0, 8. This is because the IGBT experienced a thermal

breakdown. Both the efficiency as the operating range increases when the MPC SSAC is

included.

The effectiveness of the MPC SSAC has been proven in the previous paragraph. The SSAC

is activated just before the turn-on and turn-off of the main pulse. The timing of these

pulses with respect to the main pulse should be as constant as possible to achieve an easy

control. Table 4.4 summarizes the duty cycle and the phase shift of the turn-on and turn-

off auxiliary pulses in case of the Buck converter with split DC bus, operating at 600 V, 30


δ [%] 55 60 65 70 75 80 85 90 95

20 kHz

ηhard [%] 65,0 77,3 86,1 89,3 91,2 92,5 93,3 93,9 93,6

ηsoft [%] 67,1 82,6 89,1 92,2 93,5 94,5 95,0 95,2 94,2

∆η [%] 2,1 5,3 3,0 2,9 2,3 2,0 1,7 1,3 0,7

30 kHz

ηhard [%] 52,9 72,1 81,7 85,6 87,9 88,9 / / /

ηsoft [%] 63,0 80,8 87,3 90,5 92,0 92,9 93,7 94,7 92,7

∆η [%] 10,1 8,6 5,6 4,9 4,0 4,0 / / /

Table 4.3: Efficiency comparison for 20 and 30 kHz at 600 V

Duty ratio δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9 0,95

Effic

ienc

y η

[/]

0,6

0,7

0,8

0,9

1

Hard switched

Soft switched



Duty ratio δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9 0,95

Effic

ienc

y η

[/]

0,5

0,6

0,7

0,8

0,9

1

Hard switched

Soft switched


kHz. The duty ratio (δ) of the pulses is constant and equal to 1%. The time between the

main and the auxiliary pulse is denoted with Ton and Toff . From the table it is clear that

this advancement is not constant. The timing of the on-pulse clearly increases for higher

output power while the advancement of the off-pulse decreases a little. For this thesis, the

control of the pulse width and timing has been done manually. If the SSAC is implemented

in a stand-alone version, a closed loop feedback will be needed to check whether or not

the soft switching is achieved. This is again an increase in complexity. Further research is

needed to check if this timing can be held constant, e.g. when other resonant elements are

used. Another important remark is that the duty cycle of the SSAC is very low. As can

be seen from Table 4.4, it is only 1% for both the on or off pulse. The auxiliary circuit is

thus applicable over a very wide operating range.


δmain δon Ton δoff Toff Pout

[%] [%] [ns] [%] [ns] [W]

55 1 267 1 68,5 62

60 1 333 1 68,0 182

65 1 333 1 68,8 356

70 1 373 1 68,3 595

75 1 400 1 62,5 886

80 1 400 1 68,7 1241

85 1 427 1 69,5 1670

90 1 427 1 65,0 2161

95 1 427 1 65,8 2533

Table 4.4: Duty cycle and shift of the auxiliary pulses for the SSAC

4.5.3 Waveform analysis

This section discusses the different voltage and current waveforms that occur at turn-on

and turn-off. They are plotted in Fig. 4.17. Notice that the timescale is in microseconds.

The DC bus voltage is 600 V and the output current is approximately 6 A. The behavior

of the circuit is clearly very different when the MPC SSAC is active.

Turn-on

A strong overlap between the collector-emitter voltage and the collector current is

present in hard-switching. The switching losses are thus very high. There is also a

big current peak due to diode reverse recovery. Also notice the very high dv/dt and

di/dt. When the MPC SSAC is active, soft switching conditions are clearly present.

The SSAC is activated just before the main pulse. This makes the voltage drop in

a controlled way. The dv/dt is much lower, which is beneficial for the EMC. The

current increases when the voltage is already zero. This means that the turn-on

switching loss is practically zero. Also the current peak is much lower.

Turn-off

In hard switching the IGBT current tail is visible during the turn-off time. It lasts for

approximately 300 ns. Since the voltage increases much faster, the turn-off switching

loss is very high. By applying the MPC SSAC, the collector current strongly decreases

before the collector-emitter voltage rises. Small oscillations are however still visible.

4.6. Silicon Carbide 89

×10-60 0.2 0.4 0.6 0.8 1

Vol

ts [

V]

0

500

Hard turn-on

Cur

rent

[A

]

0

20

×10-60.5 1 1.5 2 2.5

Vol

ts [

V]

0

500

Soft turn-on

Cur

rent

[A

]

0

10

20

Time [s] ×10-60 0.2 0.4 0.6 0.8 1

Vol

ts [

V]

0

500

Hard turn-off

Cur

rent

[A

]0

5

Time [s] ×10-60 0.5 1 1.5 2

Vol

ts [

V]

0

500

Soft turn-off

Cur

rent

[A

]

0

5

Fig. 4.17: Voltage and current waveforms

This means that the turn-off loss is not completely zero but it is certainly strongly

decreased.

4.6 Silicon Carbide

This section is dedicated to the results that were obtained with Silicon Carbide (SiC)

components. A SiC Power MOSFET was selected and the results will be compared to the

hard switching and soft switching measurements with IGBTs of the previous sections. The

selected component is a CREE C2M0080120D. The most relevant part of the data sheet

can be found in Appendix F. Some interesting parameters are summarized in Table 4.5.

Notice the combination of a very high drain-source breakdown voltage (VDS,BR) with a

very low on-state resistance (RDS,on). The RDS,on would be much higher when a regular

Silicon MOSFET would have been used.

The SiC MOSFET is immediately applied in a Buck converter with split DC bus, as this is

of highest interest for this thesis. The same PCB and drivers are used. The only difference

is the used DC-DC converter that is needed to supply the isolated driving voltages. SiC


Model VDS RDS,on ID,100

C2M0080120D 1200 V 80 mΩ 20 A

Table 4.5: Parameters of the SiC MOSFET

Duty ratio δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9 0,95

Effic

ienc

y η

[/]

0,6

0,7

0,8

0,9

1

Hard switched - normal IGBT

Soft switched - normal IGBT

Hard switched - SiC MOSFET

Fig. 4.18: Efficiency comparison with SiC components - 20 kHz

components need higher driving voltages, as already mentioned in Chapter 2. The SiC

MOSFET is supplied with +20/-5 V.

Measurements at 20 and 40 kHz are done and the results are plotted in Fig. 4.18 and

Fig. 4.19. At 20 kHz, a very clear improvement is visible. The SiC components (hard

switched!) perform much better than the hard or soft switched IGBTs. The efficiency

improvement ranges from 3 to 18 % when compared with hard switched IGBTs and it

ranges from 2 - 16 % when compared to soft switched IGBTs. This is a clear benefit as no

SSAC is needed to obtain this very high efficiency under hard switching. Fig. 4.19 shows

the efficiency at a switching frequency of 40 kHz. Again a very high efficiency is obtained

and the component is able to work in the entire operating area. This was not the case for

the soft switched IGBT that experienced a thermal breakdown at δ = 0, 75. When a high

efficiency in combination with a high switching frequency is required, SiC components are

clearly the best choice.

4.7. Conclusions 91

Duty ratio δ [/]0,6 0,65 0,7 0,75 0,8 0,85 0,9

Effic

ienc

y η

[/]

0,6

0,7

0,8

0,9

1

Hard switched - SiC MOSFET

Soft switched - normal IGBT

Fig. 4.19: Efficiency comparison with SiC components - 40 kHz

4.7 Conclusions

Two different SSAC were developed and tested. The first ZVT SSAC dealt with very high

over voltages. A possible solution is to add a snubber circuit. This was not done since

the SSAC already contained a high amount of components. This possibility was thus not

further developed.

The MPC SSAC showed its effectiveness on a Buck converter and was thus implemented

on a Buck converter with split DC bus. Experiments were done for a DC bus of 300, 400

and 600V and switching frequencies of 10, 20, 30 and 40 kHz. The SSAC is best perform-

ing at higher switching frequencies, when the switching losses are dominant. In this case,

an efficiency increase of about 10% is possible for low duty ratios, but the efficiency also

increases slightly for high output powers. This is clearly an advantage since the SSAC will

be applied to grid-connected inverters. These inverters are commonly connected with PV

panels, which means that they are only operating at full power when the solar irradiation

is at its maximum, at noon. During an important part of their lifetime, they will operate

below their nominal power. The efficiency is usually lower in this case, as was discussed

in Chapter 1. A possibility is thus to activate the MPC SSAC only in a certain operating

range, where the efficiency of an inverter is usually rather low. In case of high switching

frequencies, regular IGBTs usually experience a thermal breakdown because of the high


switching losses. This is not the case when the MPC SSAC is used. It increases the ef-

ficiency and prolongs the operating range. It has also been shown that the SSAC is only

active during a limited amount of time (δ = 1%). This means that it is applicable over a

wide range. The biggest concern is the shift of the pulse, which is not constant but varies

with the output power.

Also the recently commercially available SiC components were compared with the proposed

soft switching solutions. These components are rather expensive but it has been shown

that they perform much better. The efficiency of the SiC MOSFET in hard switching is

higher than the Si IGBT under soft switching. The additional cost can thus be justified

since no SSAC is needed. This solution is thus clearly more attractive and it is expected

that the future of power electronics will be dominated by these components.

Chapter 5

Conclusion

This chapter intends to give an overview of the work that has been done and the results

that have been achieved with the experimental setup. Also the possibilities for future

research are discussed.

The efficiency of a grid-connected inverter is rather high. Efficiencies above 90% are gen-

erally obtained. Only at low output power, the efficiency is rather low. Three types of

losses are present at the level of the switches: switching losses, conduction losses and driver

losses. It has been shown that the switching losses play a dominant role when IGBTs are

applied, because of the specific current tailing problem. An efficiency increase would thus

be possible if the switched losses can be omitted or reduced. This can be achieved by

using soft switching auxiliary circuits (SSAC). Different SSAC are proposed in literature.

A careful selection was made and an overview of their working principle and their topology

was presented. Three of these SSAC were simulated via PSpice to further investigate the

typical behavior of the circuit. Two of them were deemed suitable and an experimental

setup with a regular Buck converter and a Buck converter with split DC bus was realized.

Measurements have shown that the first SSAC was not an appropriate candidate since it

suffered from severe over-voltages. The second topology, being the MPC SSAC, was shown

to be very effective. The comparison of voltage and current waveforms under hard and soft

switching showed that the switching losses are virtually eliminated. The efficiency increase

that corresponds to it was in the range of 2-10% for switching frequencies of 20 and 30 kHz

and a DC bus voltage of 400 and 600 V. The efficiency over the complete operating area

improves but the effect is usually more visible in the lower power region. A possibility is

93

94 Chapter 5. Conclusion

thus to apply the SSAC only in this region where the SSAC is most effective.

Another alternative, besides the use of SSAC, is changing the Si IGBTs to the newer SiC

MOSFETs. SiC is a wide-bandgap semiconductor material and has superior properties

compared to Si. Both conduction and switching losses are remarkably lower. A converter

that uses SiC MOSFETs was compared to a soft switching Si IGBT converter. Measure-

ments for a DC bus of 600 V at a switching frequency of 20 and 40 kHz were carried

out. The efficiency of this device under hard switching is significantly higher than the soft

switched alternative. Switching frequencies of 40 kHz are proven to be possible without

any auxiliary components. A growing interest in this semiconductor material is noticed

in literature. It is therefore expected that SiC and GaN will shape the future of power

electronics as the potential for improvement is much higher compared to regular Si.

Future work

The MPC SSAC was tested for a regular Buck converter and a Buck converter with split

DC bus. It is thus expected that the SSAC will also perform correctly when it is applied

in a grid-connected inverter. There was unfortunately not enough time left at the end of

the research to build and troubleshoot an inverter PCB. Also an appropriate and flexible

control algorithm needs to be written in order to carry out enough tests.

Appendix A

Matlab scripts

A.1 Calculation resonant parameters MPC SSAC

1 %--------------------------------------------------------------

2 %Matlab script to determine the resonant elements of a MPC SSAC

3 %Simon Ravyts and Dimitar Bozalakov

4 %April 2016

5 %---------------------------------------------------------------

6

7 E = 800; %DC bus voltage

8 V o = 250; %RMS output voltage

9 P o = 3000; %Output power

10 Io pk max = 13.7; %Output peak current

11 Io pk min = 10.96;

12 delta I = Io pk max-Io pk min;

13 k = 1.095;

14 f s = 20000; %Switching frequency

15 dIdt = 80/1E-6; %Rate of change of the current

16

17 Io pk = sqrt(2)*P o*(1+delta I/Io pk max)/V o;

18 Z = (V o*E)/(4*k*P o*(1+delta I/Io pk max)); % Characteristic Impedance

19 I pk = E/(2*sqrt(2)*Z); %Peak current diverted from the main switch

20

21 omega = (dIdt *sqrt(2)*asin(1/(2*k)))/Io pk; %Angular frequency

95

96 Appendix A. Matlab scripts

22

23 Lr = Z/omega; %Henry

24 Cr = 1/(Z*omega); %Farad

A.2 Power losses - Buck converter

1 %-------------------------------------------------------------------------

2 %Calculation of the losses in case of a 4kW Buck converter with IGBTs

3 %Author: Simon Ravyts

4 %Date: March 2016

5 %-------------------------------------------------------------------------

6 clc

7 clear all

8

9 %% Input parameters converter

10 %--------------------------

11

12 Vin = 300; %volts

13 Vout = 150;

14 delta = Vout/Vin; %duty ratio t on/T

15 f s = 40000; %Switching frequency Hz

16 Pout = 1650; %Output power in watt

17 Rload = Voutˆ2/Pout; %Load resistance ohm

18

19 %% Component electrical properties - Assume linear approximation

20 %-------------------------------------------------------------

21 %Vce0, Rce, Vd0 and Rd have beel found via the figures in the data sheet

22

23 %IGBT

24 E sw tot = 7.04E-3; %Total switching loss, needs to be rescaled

25 Vce0 = 1.1946; % Volts, Vce = Vce0 + Rce * Ic

26 Rce = 0.0663;

27

28 %Diode

29 Vd0 = 1.59; % Volts, Vd = Vd0 + Rd * Id

30 Rd = 0.175;

31

32

33 %% Thermal properties casing/component

34 %------------------------------------

A.2. Power losses - Buck converter 97

35

36 P d maxi = 65; % Maximum power dissipation in watts at Tc = 100C

37 R JC T = 0.77; % C/W Junction-Casing Transistor

38 R JC D = 1.7; % C/W Junction-Casing Diode

39 R CS = 0.24; % C/W Case to Sink, greased surface

40 R SA = 0.29; % C/W

41

42 T J maxi = 100; %Maximum junction temperature in C

43 %T C = 100; %Casing temperature in C

44

45 %% Average and RMS currents

46 %--------------------------

47

48 %Assume that the output current is DC such that the ripple can be neglected

49 %The current passes through the transistor (T) during delta, through the

50 %diode(D) during (1-delta)

51

52 I out = Vout/ Rload;

53 I T avg = delta * I out;

54 I T rms = sqrt(delta) * I out;

55 I D avg = (1-delta)*I out;

56 I D rms = sqrt(1-delta) * I out;

57

58 %% Losses

59 %--------

60

61 E sw new = E sw tot * (I T rms/21) * (Vin/800); %Rescaled switching loss

62

63 P T cond = Rce * I T rmsˆ2 + Vce0 * I T avg; %Conduction loss

64 P T sw = E sw new .* f s; %Switching loss

65 P T total = P T cond + P T sw;

66

67 P D cond = Rd * I D rmsˆ2 + Vd0 * I D avg;

68

69 P tot = P T cond + P T sw + P D cond;

70

71 P out = Rload * I outˆ2;

72

73 Efficiency = P out./(P out + P tot);

74

75

76 %Heatsink - Temperature rise

77 %---------------------------


78

79 T A = 60 %Ambient temperature in C

80

81 %Transistor temperature increase

82 T S T = T A + R SA*P T total %Sink temperature transistor

83 T C T = T S T + R CS*P T total %Casing temperature transistor

84 T J T = T C T + R JC T*P T total %Junction temperature transistor

A.3 Power losses - Inverter

1 %-------------------------------------------------------------------------

2 %Calculation of the losses in case of a 4kW inverter using IGBTs

3 %Based on SEMIKRON Application Note AN-8005


5 %Date: April 2016

6 %-------------------------------------------------------------------------

7 clc

8 clear all

9

10 %% Input parameters inverter

11 %--------------------------

12

13 Vin = 800; %DC bus voltage

14 Vout = 230; %Output RMS voltage

15 Pout = 4000; %Output power in watt

16 cos phi = 1; %Cos phi of the load

17 Iout RMS = Pout/(sqrt(3)*Vout*cos phi); %Output RMS current

18 Iout P = sqrt(2)*Iout RMS; %Peak output current

19 f s = 20000; %Switching frequency Hz

20 m = 0.7; %Modulation coeffcient

21

22 %% Component electrical properties - Assume linear approximation

23 %-------------------------------------------------------------

24 %Vce0, Rce, Vd0 and Rd have been found via the figures in the data sheet

25

26 %IGBT

27 E sw tot = 7.04E-3; %Total switching loss, needs to be rescaled

28 Vce0 = 1.1946; % Volts, Vce = Vce0 + Rce * Ic

29 Rce = 0.0663;

30

A.3. Power losses - Inverter 99

31 %Diode

32 Vd0 = 1.59; % Volts, Vd = Vd0 + Rd * Id

33 Rd = 0.175;

34

35

36 %% Thermal properties casing/component

37 %------------------------------------

38

39 P d maxi = 65; % Maximum power dissipation in watts at Tc = 100C

40 R JC T = 0.77; % C/W Junction-Casing Transistor

41 R JC D = 1.7; % C/W Junction-Casing Diode

42 R CS = 0.24; % C/W Case to Sink, greased surface

43 R SA = 0.29; % C/W

44

45 T J maxi = 100; %Maximum junction temperature in C

46 %T C = 100; %Casing temperature in C

47

48 %% Losses (of one IGBT)

49 %----------------------

50

51 %Switching losses

52 E sw new = E sw tot * (Iout RMS/21) * (Vin/800);

53 P SW IGBT = E sw new .* f s;

54

55 %Conduction losses

56 P C DIODE = 1/2 * (Vd0*Iout P/pi + Rd/4 * Iout Pˆ2) - m * cos phi * (Vd0 ...

* Iout P/8 + Rd * Iout Pˆ2 / (3*pi));

57 P C IGBT = 1/2 * (Vce0 * Iout P/pi + Rce/4*Iout Pˆ2) + m * cos phi ...

*(Vce0*Iout P/8 + Rce*Iout Pˆ2/(3*pi));

58

59 P tot = P SW IGBT + P C DIODE + P C IGBT;

60

61 %Temperature increase

62 %---------------------------

63

64 T A = 60 %Ambient temperature in C

65

66 T S = T A + R SA*P tot %Sink temperature

67 T C = T S + R CS*P tot %Casing temperature

68 T J = T C + R JC T*P tot %Junction temperature


A.4 Determination of switching losses

1 %---------------------------------------------------------------------

2 %Script to determine the switching losses of an IGBT, based on the same

3 %technique as used in the datasheet


5 %Date: April 2016

6 %----------------------------------------------------------------------

7

8 clc

9 clear all

10

11 %First read in the CSV files of the ossciloscope using a function provided

12 %by Tektronix.

13 %CH1 <-> Vce Collector-Emitter voltage

14 %CH2 <-> Ic Collector current

15 %CH3 <-> Vge Gate-Emitter voltage (=driving voltage)

16

17 data Vce = read tektronix csv('F0050CH1.CSV');

18 data Ic = read tektronix csv('F0050CH2.CSV');

19 data Vge = read tektronix csv('F0050CH3.CSV');

20

21 %Exctract the useful data from the CSV files(time, voltages, currents)

22

23 t = data Vce.time;

24 %The time instances are symmetrical (t=0 in the middle), such as displayed

25 %on an oscilloscope. We want to start at t=0

26 t = t - min(t);

27

28 Vce = data Vce.values;

29 Ic = data Ic.values / 100; %Because the settings for the current are not ...

correct

30 Vdr = data Vge.values*5; %Since the home-made passive probe has an ...

attenuation of X50

31

32 Ts = data Vce.Sample Interval; %Sample period

33 Ns = data Vce.Record Length; %Number of samples - usually 2500

34

35 %% Display the values that are read in one figure using subplots

36

A.4. Determination of switching losses 101

37 figure

38 subplot(3,1,1)

39 plot(t,Vdr);

40 ylabel('Volts [V]')

41 title('Gate-Emitter voltage - Driving signal')

42 grid on

43 subplot(3,1,2)

44 plot(t, Vce );

45 title('Collector-Emitter Voltage')


47 grid on

48 subplot(3,1,3)

49 plot(t, Ic);

50 xlabel('Time [s]')

51 ylabel('Current [A]')

52 title('Collector current')

53 grid on

54

55 %% Determine the instantaneous power dissipation

56 P = Vce.*Ic;

57 figure

58 plot(t,P)


60 ylabel('Power [VA]')

61 title('IGBT power consumption')

62 grid on

63

64 %If needed, the result can be filtered using median or average filtering

65 %P filt = medfilt1(P,10);

66 %figure

67 %plot(t, P filt)

68

69 %% Split up the results

70 %This part is only necessary if the scope captures one entire waveform. In

71 %that case, the first part of the measurement is used for the turn-on and

72 %the second part for the turn-off. However, it's better to leave this part

73 %out and capture only one of the two events

74

75 t 1 = t(1:1250);

76 t 2 = t(1251:2500);

77

78 Ic 1 = Ic(1:1250);

79 Ic 2 = Ic(1251:2500);


80

81 Vce 1 = Vce(1:1250);

82 Vce 2 = Vce(1251:2500);

83

84 %% Determine the integration limits for 'E off', the turn-off energy

85 %The procedure is based on how the switching losses are specified in the ...

data sheet

86 %E off -> Integrate from 10%Vce to 5%Ic

87 %E on -> Integrate from 10%Ic to 5%Vce

88

89 %Determine 100%Vce using the final part of the values (last 200 entries)

90 Vce 100p = mean(Vce 2(1050:1250));

91 Vce 10p = 0.1 * Vce 100p;

92

93 %Make an array 'A' that has a constant value, equal to 10%Vce

94 A = ones(1250,1);

95 A(1:1250) = Vce 10p;

96

97 %Use the function 'curveintersect' to find the time values corresponding to

98 %the first integration limit(=int start). The int start corresponds to the

99 %place in the array where the value can be found

100 [X1,Y1] = curveintersect(t 2,Vce 2,t 2,A);

101 int start 1 = round(X1(1)/ Ts - 1250);

102

103 %Plot the functions for visual inspection of the intersection points that

104 %are determined (= red dots)

105 figure

106 plot(t 2,Vce 2,'k',t 2,A,'b',X1,Y1,'ro')



109 title('E-off: Intersection points (red dots) to find "int-start" ')

110 grid on

111

112 %Now the above procedure is repeated to determine the 2nd intersection

113 %point/ integration limit. The only difference is that there are usually

114 %multiple intersections due to the oscillations in the current so we can

115 %choose in fact between one of these values. A good choice might be

116 %comparing the first and last intersection.

117 Ic 100p = mean(Ic 2(1:200));

118 Ic 5p = 0.05*Ic 100p;

119 B = ones(1250,1);

120 B(1:1250) = Ic 5p;

121 [X2,Y2] = curveintersect(t 2,Ic 2,t 2,B);

A.4. Determination of switching losses 103

122 int stop 1 = round(X2(end)/Ts - 1250);

123 figure

124 plot(t 2,Ic 2,'k',t 2,B,'b',X2,Y2,'ro')



127 title('E-off: Intersection points (red dots) to find "int-stop" ')

128 grid on

129

130 %Both integration limits are now determined. The 'trapz' function can be

131 %used for trapezoidal integration. However, 'trapz' works for the entire

132 %array so we need to extract the interesting part of the array first.

133 t off = t 2(int start 1:int stop 1);

134 P off = Vce 2(int start 1:int stop 1).*Ic 2(int start 1:int stop 1);

135 W off = Ts*trapz(P off);

136

137 figure

138 plot(t off,P off,'r',t off,W off,'o')



141 title('Turn off power loss')

142 grid on

143

144 %% The same method will be used to determine E on, the turn on energy

145 %E on -> Integrate from 10%Ic to 5%Vce

146 %Note that sometimes the same names are used!

147

148 %int start

149 Ic 100p = mean(Ic 1(1050:1250));

150 Ic 10p = 0.1*Ic 100p;

151 C = ones(1250,1);

152 C(1:1250) = Ic 10p;

153 [X3,Y3] = curveintersect(t 1,Ic 1,t 1,C);

154 int start 2 = round(X3(1)/Ts);

155 figure

156 plot(t 1,Ic 1,'k',t 1,C,'b',X3,Y3,'ro')



159 title('E-on: Intersection points (red dots) to find "int-start" ')

160 grid on

161

162 %int stop

163 Vce 100p = mean(Vce 1(1:200));

164 Vce 5p = 0.05 * Vce 100p;


165 D = ones(1250,1);

166 D(1:1250) = Vce 5p;

167 [X4,Y4] = curveintersect(t 1,Vce 1,t 1,D);

168 int stop 2 = round(X4(1)/ Ts);

169 figure

170 plot(t 1,Vce 1,'k',t 1,D,'b',X4,Y4,'ro')



173 title('E-on: Intersection points (red dots) to find "int-stop" ')

174 grid on

175

176 t on = t 1(int start 2:int stop 2);

177 P on = Vce 1(int start 2:int stop 2).*Ic 1(int start 2:int stop 2);

178 W on = Ts*trapz(P on);

179 figure

180 plot(t on,P on,'r',t on,W on,'o')



183 title('Turn on power loss')

184 grid on

185

186

187 %% Comparison

188 %The obtained results can be compared to the data sheet values if they are

189 %corrected via linear interpolation

190

191 E on ds = 1.80E-3;

192 E off ds = 1.93E-3;

193 Vcc ds = 800;

194 Ic ds = 21;

195

196 E on ds conv = E on ds * (Vce 100p/Vcc ds) * (Ic 100p/Ic ds);

197 E off ds conv = E off ds * (Vce 100p/Vcc ds) * (Ic 100p/Ic ds);

198

199 %The comparison should lead to values close to 1

200 comp on = W on/E on ds conv;

201 comp off = W off/E off ds conv;

A.5 Calculation of the gate resistance

A.5. Calculation of the gate resistance 105

1 %-------------------------------------------------------------------------

2 %Matlab script to calculate the required value of R gate, based on the

3 %Avago ACPL-337J data sheet


5 %Date: March 2016

6 %-------------------------------------------------------------------------

7

8 I max = 4; %Ampere

9 V on = 15; %Volt

10 V off = 8.7; %Volt

11 R DS OH min = 0.5; %ohm, min resistance of the top (high side) transistor

12 R DS OL min = 0.2; %ohm, min resistance of the bot (low side) transistor

13

14 Rg min1 = V on/I max - R DS OH min;

15 Rg min2 = V off/I max - R DS OL min;

16

17 Rg = max(Rg min1,Rg min2);

18 %The gate resistance must be higher than the highest of both values.

19 %However, also the total power dissipation of the IC needs to be checked.

20

21 %Led power dissipation

22 duty cycle = 0.9; % Max duty cycle of the switches

23 I f = 16E-3; %Amps, max led current

24 V f = 1.95; %volts, max voltage drop over led

25 P E = duty cycle * I f * V f ;

26

27 %Input IC power dissipation

28 I cc1 = 6E-3; %Max input current

29 V cc1 = 5.5; %Volts, recommended max input voltage

30 P IN = I cc1*V cc1;

31

32 %Output IC power dissipation

33 V cc2 = 15;

34 V ee2 = -8.7;

35 I cc2 = 7.5E-3;

36 Qg = 130E-9; % From IGBT datasheet

37 f s = 50E3; % Switching frequency

38 R DS OH max = 4.5;

39 R DS OL max = 3.6;

40 P O = I cc2*(V cc2 - V ee2) + V cc2*Qg*f s*R DS OH max/(R DS OH max + ...

Rg)/2 + V cc2*Qg*f s*R DS OL max/(R DS OL max + Rg)/2;

41

42 P tot = P E + P IN + P O;


43

44 disp('If P tot is lower than 600mW, the selected Rg is appropriate')

Appendix B

Design considerations

This chapter will handle the basics of designing an IGBT or MOSFET inverter. At first,

the theoretical background and practical implementation of gate drivers and protection

circuits will be treated. Thereafter, an overview of the used components will be given,

together with their relevant features. This is important to understand the next part, that

deals with the lay-out of the circuit.

B.1 Fundamentals of power electronics design

B.1.1 Gate drive circuits

Gate drive circuits have already been briefly discussed in section 2.2 but we will go into

some more detail in this chapter.

The drive circuit is considered as the interface between the control circuit and the power

switch itself. Its main purpose is to turn the device ON and OFF. Although this may seem

simple, a lot of constraints regarding costs, safety and performance need to be taken into

account [12] :

Price A complex design with additional features and thus more components will be

107

108 Appendix B. Design considerations

more costly while a low-cost solution is usually preferred

Responsiveness The component passes through the active region during switching. In

this zone, the power dissipation is very high. So it is important that the driver is able

to switch the device ON and OFF very rapidly to limit the switching losses. Therefore,

the power and even more the peak current of the drivers is a very important aspect.

This may seem odd since MOSFETs and IGBTs are essentially voltage controlled. But

at turn-ON, a current is needed to charge the gate capacitance such that the component

starts conducting.

Bipolar output Drivers with bipolar output supply the power switch with a positive

voltage to turn it on and with a negative voltage to turn it off. The use of such a driver

is usually preferred over a unipolar output (switches between a positive voltage and

GND) because it decreases the turn-OFF time of the device. Another advantage is that

the circuit is less sensitive to switching transients caused by other components. These

transients may lead to unwanted ON ↔ OFF oscillations that cause additional losses.

Blanking time A blanking time is usually needed to prevent shoot-through of the leg.

This may happen during the small time interval when one of the switches turns OFF

while the other one turns ON.

Emitter inductance There is always a small amount of emitter inductance present in

the circuit. At first, the device package contains some inductance. This is usually rather

limited and can be decreased when the manufacturer foresees two leads for the emitter.

One for the main power path, the other for the driving signal. The second cause of

emitter inductance are the PCB tracks between the driver and the component. They

should be kept as short as possible, which means that the driver needs to be placed as

close as possible to the switch.

Gate resistance This is the resistor that needs to be applied between the gate of the

IGBT or MOSFET and the driving circuit. A low value is preferable for fast response

and low power losses. However, if the gate resistance is too low, the EMI performance

usually deteriorates because of the high di/dt and dv/dt and possible ringing. An

indication of the required value is normally given in the data sheet. This value usually

needs to be tweaked for optimal performance since the gate resistor Rg together with

the gate-emitter capacitance CGE and the emitter inductance Le form an RLC circuit

that may start ringing when a voltage from the driver is applied. Rg should be chosen

B.1. Fundamentals of power electronics design 109

Rg Rg ton toff Eon Eoff

Turn-on peak current dv/dt di/dt

EMI noise

Table B.1: Influence of gate resistance on performance [7]

such that enough damping is present in the circuit. Table B.1 summarizes the most

important tendencies when the resistance is in- or decreased [7].

Electrical isolation The GND of the control circuit usually differs from the GND of the

driver. Each driver has a separate ground that needs to be connected with the emitter of

the IGBT since the applied driving signals need to be referred to this potential and not

to the common GND. This isolation is usually achieved by transformers, optocouplers

or fiber optics.

Over-current protection Over-currents may arise when the load is too high or when

a short circuit is present. The current can be measured using an external sensor but

usually a more elegant method is preferred. The collector-emitter voltage VCE is mea-

sured and compared with the nominal ON-state voltage. When the current increases,

also VCE will increase. If the voltage exceeds a certain, user-defined limit, the driver

stops working and gives an error. This method is usually referred to as desaturation

protection.

Under-voltage protection In power electronics, the MOSFETs or IGBTs are used in

switch mode. This means that the component is completely ON or completely OFF and

is done by applying a sufficient amount of voltage. If the voltage to switch the device

falls below a certain threshold, the component will be used in active mode. The losses

in active mode are much higher compared to switch mode. It is therefore recommended

to detect an under-voltage condition and consequently shut down the driver since the

low voltage may be a consequence of faulty conditions.


B.2 Component selection

The selection of the relevant components is discussed here together with their important

features. Both a regular Buck converter and a Buck converter with split DC bus will be

built using mostly the same components.

Main switches IGBTs with integrated diodes will be used as the main switches: Inter-

national Rectifier IRG4PH40UDPbF and also IRGP30B120KD-E. The relevant part of

the data sheet can be found in Appendix F. To make a comparison with better compo-

nents, also SiC transistors will be used: CREE C2M0080120D SiC MOSFETs (RDS,on

= 80 mΩ)

Auxiliary switches The auxiliary switches that have been selected are both regular

MOSFETs as SiC MOSFETs: CREE C2M0280120D (RDS,on = 280 mΩ)

Diodes The free-wheeling diodes of the Buck converter/ inverter are integrated in the

main switches. For the soft cell, Silicon Carbide Schottky diodes will be used since they

can be used for high frequencies, have very low switching losses and switch very fast:

CREE C4D02120A.

Inductances Several inductances will be tested ant their performance will be compared.

The main issue is here the linearity of the inductor over a broad current range and the

maximum heat dissipation capabilities. If the industrial available components are not

suitable, air coils can be used as an alternative. They have the advantage that they do

not saturate.

General purpose power supply The board will be supplied via an external 5V power

supply: Myrra 47200.

Driver power supplies The driving voltages of the IGBTs are +15/-8.7V. The driving

voltages of the SiC transistor are slightly different: +20/-5V They will be fed by Murata

MGJ2 isolated DC/DC converters.

Gate drivers For fast switching, a high quality driver is needed. Therefore, the Avago

ACPL-337J has been selected. It contains an integrated desaturation protection, active

Miller clamping and error status feedback.

B.3. PCB design 111

B.3 PCB design

The software that has been used for the design of the boards is Altium Designer 14.3.11.

Since I was personally not able to work with this software, a considerable amount of time

went to training via instruction videos and reading the provided tutorials of the software.

The design of a PCB consists of different steps. First, a schematic of the circuit must be

made. To do so, the different items that will be used must be available in the ’component

library’. This means that both a schematic symbol and a ’footprint’ need to exist. If they

are not available, which is usually the case, they must be custom made. If the schematic is

complete and all the components have been assigned the correct footprints, the schematic

can be transferred to the PCB lay-out. In PCB lay-out one must first define the board’s

dimensions. Then, the components can be placed on the board and the routing can be

done. This process has usually some internal feedback in it, which makes that it is ran

through several times for perfection.

Component selection has already been discussed in a previous section. However, a lot of

components/ICs still need some extra auxiliary parts to work properly (e.g. filter capac-

itors for the drivers). SMD components were chosen for this purpose. This way, a high

component density (components per unit are) and low parasitics are achieved. They can

be placed on both sides of the PCB and they are usually cheaper. Also the traces can be

made shorter, which again decreases the parasitic resistance and inductance. So different

advantages are present when SMD components are chosen. The only disadvantage is that

they also need to be soldered by hand, which needs some experience.

The PCBs have been fabricated in the workshop of EELAB. This leaded to some constraints

since no high-end, automated machines are used:

The board can only be single- or double-layered.

The minimum trace width is 0.3 mm.

The drilling is done manually.

The components must be soldered by hand.

For the eventual PCB lay-out and schematics, we refer to Appendix D.


B.4 PCB optimization

During the initial design stage, the guidelines of the data sheets of the components have

been followed. However it has been found, via experimental verification, that the proposed

solutions still needed some optimization.

For the driving circuit, an Avago ACPL-337J IC is used. The recommended application

circuit can be found in the data sheet and is shown in Fig. B.1 and Fig. B.2. The involved

circuit is used to protect the IGBT and must intervene when the collector current is too

high. This is sensed via the collector-emitter voltage VCE by reasoning that an over-current

will also lead to an increased voltage across the terminals of the device. The protection

must trip at a current of w 21 A. The circuit however intervened too quickly. Therefore, it

needed to be tuned such that it acts only above this current level. This was made possible

by using a combination of a Zenerdiode and two regular diodes, namely the combination

of BZX79C2V4, BYV26, 1N4148. With this configuration the protection triggers for a

current in the range of 21-23 A.

For the first tests, normal cables were used to transmit the signal from the DSP to the

driver. This however leaded to some disturbances because the signal was influenced by

the EMI of the power cables (high dv/dt and di/dt). This problem was solved by using

shielded cables.

Also the gate resistor needed to be determined. This can be done using the equations in

the driver data sheet [6] where it is also important to control if the power dissipation of

the driver is not too high. This calculation has been done via a Matlab script that can be

found in Appendix A.5. The result is Rg = 3.9 Ω. To verify this result, the driving voltage

is plotted in Fig. B.3. One can see that the behavior is as expected, without any ringing.

So the calculated Rg is valid.

B.5 Thermal design

The switching and conduction losses are dissipated inside the IGBT. This leads to a tem-

perature increase of the package. The component will be destroyed if a certain critical

B.5. Thermal design 113

Fig. B.1: Recommended driver application circuit [6]

Fig. B.2: Recommended application of the DESAT protection circuit [6]


×10-70 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vol

ts [V

]

-10

-5

0

5

10

15

20Turn-on

Time [s] ×10-70 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vol

ts [V

]

-15

-10

-5

0

5

10

15Turn-off

Fig. B.3: IGBT driving voltages (zoom)

temperature is reached. For most components this is Tmax = 150 C. To extend the ca-

pabilities of the switches, they are usually mounted on a heat sink using thermal grease.

This is done to maximize the heat transfer towards the heat sink. Another important

aspect is that the transistor needs to be isolated from the heat sink. This is achieved using

thermal insulators as shown in Fig. B.4. The reliability of the entire system depends on

an adequate thermal design.

The losses of the IGBTs can be calculated as described in Chapter 2. The Matlab script

that has been used for this purpose can be found in section A.2. Both the losses of a Buck

converter operating at 4 kW and an inverter with an output of 4 kW have been calculated.

This information together with the chosen heat sink leads to the temperature increase

of the device. The heat sink was chosen rather large such that the components would

not experience a thermal breakdown during the tests. The Matlab script can be adapted

easily to the appropriate input parameters when for example the input voltage or switching

frequency is altered.

B.6. Control circuitry 115

Fig. B.4: Thermal insulation tube

B.6 Control circuitry

The control signals that are supplied to the boards are generated via a Digital Signal

Processor (DSP) of Texas Instruments, namely the TMS320F28335, 32 bit digital signal

processor with a clock frequency of 150 MHz, in combination with the Peripheral Explorer

Board. Pictures of both are shown in Fig. B.5. The DSP was programmed via the program

’Code Composer Studio’, version 6.1.2 . These programs are written in the C language

and can be found under Appendix C.


Fig. B.5: The Digital Signal Processor

Appendix C

DSP code

This appendix contains the program, written in C, that was used to deliver the signal

to the gate drivers. It was uploaded via Code Composer Studio 6.1.2 towards the TI

TMS320F28335. The main purpose was to produce three square waves (PWM) with a

variable frequency and variable duty cycle. Also the timing needed to be easily changeable.

The first square wave is the main PWM signal to the converter while the other two are the

pulses for the auxiliary circuit. They need to be adjusted such that they start just before

the begin or the end of the main pulse. These two signals are then combined via a logic

OR gate (7432) and then fed to the driver of the auxiliary circuit.

1 //Created on: 24 mrt. 2016

2 //Author: simon

3 //Based on examples provided by Texas Instruments

4

5 #include "DSP2833x Device.h"

6

7 // external function prototypes

8 extern void InitSysCtrl(void);

9 extern void InitPieCtrl(void);

10 extern void InitPieVectTable(void);

11 extern void InitCpuTimers(void);

12 extern void ConfigCpuTimer(struct CPUTIMER VARS *, float, float);

13

14 // Prototype statements for functions found within this file.

15 void Gpio select(void);

117

118 Appendix C. DSP code

16 void Setup ePWM(void);

17 interrupt void cpu timer0 isr(void);

18

19 float duty 1 = 50.0;

20 float duty 2 = 10.0;

21 float duty 3 = 10.0;

22 float duty 4 = 10.0;

23

24 float set 1 = 0.0; //Pulse width of PWM 1A

25 float set 2 = 0.0; // Pulse width of PWM 2A

26 float set 3 = 0.0; //Phase shift of 2 relative to 1 75 =1us; 150 =2us; ...

225 =3us

27 float set 4 = 0.0; //Phase shift of 2 relative to 1 75 =1us; 150 =2us; ...

225 =3us

28 float set 5 = 0.0;

29 float set 6 = 1;

30

31 int set TBPRD = 3750; // 3750 = 20kHz, /2 for 40kHz, /2.5 for 50kHz

32

33 //###########################################################################

34 // main code

35 //###########################################################################

36 void main(void)

37 38 int counter=0; // binary counter for digital output

39

40 InitSysCtrl(); // Basic Core Init from DSP2833x SysCtrl.c

41

42 EALLOW;

43 SysCtrlRegs.WDCR= 0x00AF; // Re-enable the watchdog

44 EDIS; // 0x00AF to NOT disable the Watchdog, ...

Prescaler = 64

45

46 DINT; // Disable all interrupts

47

48 Gpio select(); // GPIO9, GPIO11, GPIO34 and GPIO49 as output

49 // to 4 LEDs at Peripheral Explorer)

50

51 Setup ePWM(); // init of ePWM1A

52

53 InitPieCtrl(); // basic setup of PIE table; from ...

DSP2833x PieCtrl.c

54

119

55 InitPieVectTable(); // default ISR's in PIE

56

57 EALLOW;

58 PieVectTable.TINT0 = &cpu timer0 isr;

59 EDIS;

60

61 InitCpuTimers(); // basic setup CPU Timer0, 1 and 2

62

63 ConfigCpuTimer(&CpuTimer0,150,100);

64

65 PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

66

67 IER |=1;68

69 EINT;

70 ERTM;

71

72 CpuTimer0Regs.TCR.bit.TSS = 0; // start timer0

73

74 while(1)

75 76 while(CpuTimer0.InterruptCount == 0);

77 CpuTimer0.InterruptCount = 0;

78

79 EALLOW;

80 SysCtrlRegs.WDKEY = 0x55; // service WD #1

81 EDIS;

82 counter++;

83

84 set 1 = duty 1 * set TBPRD *0.01; //Duty cycle is ...

converted to a value between 0 and TBPRD

85 set 2 = duty 2 * set TBPRD * 0.01;

86 //set 3 = duty 3 * set TBPRD * 0.01; //If a symmetrical ...

pulse is wanted

87 set 4 = duty 4 * set TBPRD * 0.01;

88 if (set 6 == 1) //set 5 and set 6 ...

are used to position the pulse at turn-off

89 set 5 = 3750 - set 1 + 5;90

91

92 EPwm1Regs.CMPA.half.CMPA = set 1;

93 EPwm2Regs.CMPB = set 2;

94 EPwm2Regs.TBPHS.half.TBPHS = set 3;


95 EPwm3Regs.CMPB = set 4;

96 EPwm3Regs.TBPHS.half.TBPHS = set 5;

97

98 99

100

101 void Gpio select(void)

102 103 EALLOW;

104 GpioCtrlRegs.GPAMUX1.all = 0; // GPIO15 ... GPIO0 = General ...

Puropse I/O

105 GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // ePWM1A active



108

109

110 GpioCtrlRegs.GPAMUX2.all = 0; // GPIO31 ... GPIO16 = General ...

Purpose I/O

111 GpioCtrlRegs.GPBMUX1.all = 0; // GPIO47 ... GPIO32 = General ...

Purpose I/O

112 GpioCtrlRegs.GPBMUX2.all = 0; // GPIO63 ... GPIO48 = General ...

Purpose I/O

113 GpioCtrlRegs.GPCMUX1.all = 0; // GPIO79 ... GPIO64 = General ...

Purpose I/O

114 GpioCtrlRegs.GPCMUX2.all = 0; // GPIO87 ... GPIO80 = General ...

Purpose I/O

115

116 GpioCtrlRegs.GPADIR.all = 0;

117 GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // peripheral explorer: LED ...

LD1 at GPIO9

118 GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // peripheral explorer: LED ...

LD2 at GPIO11

119


121 GpioDataRegs.GPASET.bit.GPIO17 = 1; // ePWM3A active

122

123 GpioCtrlRegs.GPBDIR.all = 0; // GPIO63-32 as inputs

124 GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // peripheral explorer: LED ...

LD3 at GPIO34

125 GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1; // peripheral explorer: LED LD4 ...

at GPIO49

126 GpioDataRegs.GPBSET.bit.GPIO49 = 1;

127

121

128

129 GpioCtrlRegs.GPCDIR.all = 0; // GPIO87-64 as inputs

130 EDIS;

131 132

133 void Setup ePWM(void)

134 135 EPwm1Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1

136 EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1; // HSPCLKDIV = 2

137 EPwm1Regs.TBCTL.bit.CTRMODE = 0; // up mode - DUs enkel omhoog ...

tellen!!!

138 EPwm1Regs.AQCTLA.all = 18; // ZRO = set, PRD = clear

139 //EPwm1Regs.AQCTLA.all = 96;

140 EPwm1Regs.TBPRD = set TBPRD; // 20KHz - PWM signal - Geen ...

1/2 nodig als we enkel omhoog counten!

141 EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; //Generate a signal if CTR=0, ...

needed for the phase shift

142

143 //EPwm1Regs.CMPA.half.CMPA = set;

144

145 EPwm2Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1


147 EPwm2Regs.TBCTL.bit.CTRMODE = 0; // up mode

148 EPwm2Regs.AQCTLA.all = 258; // ZRO = set, PRD = clear THIS ...

LINE IS MEANINGLESS!!! SHOULD BE 18 OR 06

149 EPwm2Regs.TBPRD = set TBPRD; // 20KHz - PWM signal

150

151 EPwm2Regs.TBCTL.bit.PHSEN = 1; // Set phase enable

152 EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; //Sync Out Select: SYNCIN = SYNCOUT

153 //EPwm2Regs.TBPHS.half.TBPHS = 100; //Phase shift of 2 relative to 1

154 //EPwm2Regs.CMPB = 500; //dutycycle

155

156 EPwm3Regs.TBCTL.bit.CLKDIV = 0; // CLKDIV = 1


158 EPwm3Regs.TBCTL.bit.CTRMODE = 0; // up mode

159 EPwm3Regs.AQCTLA.all = 258; // ZRO = set, PRD = clear

160 EPwm3Regs.TBPRD = set TBPRD; // 20KHz - PWM signal

161 EPwm3Regs.TBCTL.bit.SYNCOSEL = 0; //Sync Out Select: SYNCIN = SYNCOUT

162 EPwm3Regs.TBCTL.bit.PHSEN = 1;

163 EPwm3Regs.TBPHS.half.TBPHS = set 5; // set your phase shift ...

of the aux pulse

164

165


166

167 interrupt void cpu timer0 isr(void)

168 169 CpuTimer0.InterruptCount++;

170 EALLOW;

171 SysCtrlRegs.WDKEY = 0xAA; // service WD #2

172 EDIS;

173 PieCtrlRegs.PIEACK.all = PIEACK GROUP1;

174 175 //===========================================================================

176 // End of SourceCode.

177 //===========================================================================

Appendix D

PCB design

In this section, the different schematics and board lay-outs for the converter and auxiliary

circuits can be found. They are made with Altium Designer 14.3.11

D.1 Schematics

123

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 25-2-2016 Sheet ofFile: C:\Users\..\5V Power supply.SchDoc Drawn By:

1

2 3

4ACN

ACL -Vout

+VoutD27

ECE Series

12

P3

Header 2

C31100nF

C32100nF

C3010uF

R33

100

R34

100

+5V

GND_P

1

2

7

6

5

MGJ2

+Vin

-Vin-Vout

0V

+Vout

DCDC1

Murata MGJ2 Series

+15V_TOP_M

-5V_TOP_M

GND_TOP_MC34100nF

C35100nF

C33100nF

C36100nF

+5V

GND_P

L5

22uH

L6

22uH

1

2

7

6

5

MGJ2

+Vin

-Vin-Vout

0V

+Vout

DCDC2

Murata MGJ2 Series

C39100nF

+5V

GND_BOT_M

+15V_BOT_M

-5V_BOT_M

C37100nF

C40100nF

GND_P

10mH

L7

10mH

10mH

L8

10mH

C38100nF

1

2

7

6

5

+Vin

-Vin-Vout

0V

+VoutDCDC3

Murata MGJ2 Series

C42100nF

C41100nF

C44100nF

GND_TOP_A

+15V_TOP_A

-5V_TOP_A

+5V

GND_P

1

2

7

6

5

+Vin

-Vin-Vout

0V

+VoutDCDC4

Murata MGJ2 Series

C47100nF

+5V

GND_P

C45100nF

C48100nF

+15V_BOT_A

-5V_BOT_A

GND_BOT_A

C43100nF

C46100nF

10mH

L9

10mH

10mH

L10

10mH

10mH

L11

10mH

10mH

L12

10mH

AC1

AC2

12

P2

Header 2

12

P4

Header 2

12

P6

Header 2

12

P10

Header 2

12

P5

Header 2

12

P7

Header 2

12

P8

Header 2

12

P9

Header 2

12

P?

Header 2

12

P?

Header 2

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 25-2-2016 Sheet ofFile: C:\Users\..\Buck.SchDoc Drawn By:

Q1IGBT-N

Q2IGBT-N

R10.1

R90.1

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16ACPL-337J

Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC1

ACPL-337J

R6

5

R5 5

R14

5

R13 5

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16ACPL-337J

Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC2

ACPL-337J

+Vbus

-Vbus

D5 D Schottky

D10 D Schottky

C11uF

150R7

R8150

C21uF

C31uF

C61uF

Cblank1220pF

R2

1K

D1Diode

+15V_TOP_M

-5V_TOP_M

GND_TOP_M

GND_TOP_M

D3

D Zener

D4

D SchottkyR410K

R310K

C4330pFC5

330pF

GND_1

J1

Socket

J5

SocketGND_BOT_M

C81uF

C91uF

C101uF

-5V_BOT_M

+15V_BOT_M

Cblank2220pF

R10

1K

D9

D Schottky

D8

D Zener

D7

Diode

GND_BOT_MR1110K

R1210K

100pF

C11Cap

100pF

C12Cap

R15

150

R16

150

C7

1uF

GND_1

J3

Socket

J2

Socket

J4

Socket

1 23 45 67 89 1011 1213 1415 1617 1819 20

P1

Header 10X2

+5V

GND_1

FAIL

FAIL

M_D_TOP

GND_1GND_1

M_D_TOPA_D_TOP

A_D_BOTM_D_BOT

FAIL

M_D_BOT

FAIL

FAIL

GND_1+5V

1 2

3 4

G

R

D2

HSMF-C155

1 2

3 4

G

R

D6

HSMF-C155

-5V_TOP_M

-5V_BOT_M

-5V_BOT_M

-5V_TOP_M

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 25-2-2016 Sheet ofFile: C:\Users\..\Soft_cell.SchDoc Drawn By:

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC3

ACPL-337J

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC4

ACPL-337J

Q3MOSFET-N

Q4MOSFET-N

D15Diode

D23Diode

D19

Diode

D18

Diode

C152.2nF

C262.2nF

C22

16nF

C17

15nF

L1

30uH

L2

10uH

L3

10uH

L4

30uH

D16Diode

D20Diode

J6

Socket

J11

Socket

J9

Socket

J7

Socket

R2710K

R2810K

C28330pF

C29330pF

R31

150

R32

150

C23

1uF

R1810K

R1910K

C19330pF

C20330pF

R22

150

R24

150

C13

1uF

GND_P

+5VGND_P

+5VGND_P

R305

R295

D26 D Schottky

C241uF

C251uF

C271uF

+15V_BOT_A

Cblank4220pF

D25

D Schottky

D24

D Zener

GND_BOT_A

R23

0.1

R25

0.1

-5V_BOT_AGND_BOT_A

R26

1K

R215

R205

D17 D Schottky

C141uF

C161uF

C181uF

+15V_TOP_A

Cblank3220pF

D14

D Schottky

D13

D Zener

GND_TOP_A

R17

1K

-5V_TOP_A

D22

Diode

D12

Diode

A_D_TOP

A_D_BOT

FAIL

FAIL

FAIL

FAIL

GND_P

GND_TOP_A

1 2

3 4

G

R

D11

HSMF-C155

1 2

3 4

G

R

D21

HSMF-C155

-5V_TOP_A

-5V_BOT_A

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 28-4-2016 Sheet ofFile: C:\Users\..\Soft_cell_one.SchDoc Drawn By:

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC3

ACPL-337J

Q3MOSFET-N

C17

15nF

L1

30uH

L2

10uH

J9

Socket

J11

Socket

J10

Socket

R1810K

R1910K

C19330pF

C20330pF

R22

150

R24

150

C13

1uF

+5VGND_P

R23

0.1

R215

R205

D17 D Schottky

C141uF

C161uF

C181uF

+15V_TOP_A

Cblank3220pF

D14

D Schottky

D13

D Zener

GND_TOP_A

R17

1K

-5V_TOP_A

D12

Diode

A_D_TOP

FAIL

FAIL

GND_P

GND_TOP_A

1 2

3 4

G

R

D11

HSMF-C155

-5V_TOP_A

G3

P9

Mounting pad

P10

Mounting pad

P11

Mounting pad

P7

Mounting pad

P8

Mounting pad

D15Diode_SR

D16

Diode_SR

D18Diode_SR

J16

Socket

J17

Socket

J18

Socket

+DCbus

-DCbus

Midpoint

1234

P33

Header 4

FAIL+5VA_D_TOP

GND_P

J30

Socket

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 28-4-2016 Sheet ofFile: C:\Users\..\T_type_schema.SchDoc Drawn By:

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC1

ACPL-337J

R210K

R310K

C5330pF

C6330pF

R6

150

R7

150

C1

1uF

+5VGND_P

R55

R45

C21uF

C31uF

C41uF

+15V_A1

Cblank1220pF

D4

D Schottky

D3

D Zener

SOURCE_A1

R1

1K

-5V_A1

D2

Diode

Pulse_A1

FAIL

FAIL

GND_P

1 2

3 4

G

R

D1

HSMF-C155

-5V_A1

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16Vee1

Vin+

Vcc1

Vleddr

Uvlo

Fault

Anode

Cathode

Vee2

Vled

Desat

Ve

Vcc2

Vout

Vclamp

Vee2

IC2

ACPL-337J

R910K

R1010K

C11330pF

C12330pF

R13

150

R14

150

C7

1uF

+5VGND_P

R125

R115

C81uF

C91uF

C101uF

+15V_A2

Cblank2220pF

D10

D Schottky

D9

D Zener

SOURCE_A2

R8

1K

-5V_A2

D8

Diode

Pulse_A2

FAIL

FAIL

GND_P

1 2

3 4

G

R

D7

HSMF-C155

-5V_A2

Lr118uH

Lr218uH

Cr18nF

Cr28nF

J_Midpoint_SwitchesSocket

J_Midpoint_CapSocket

GATE_A1

GATE_A1

GATE_A2

GATE_A2

SOURCE_A2

DRAIN_A1

DRAIN_A2

DRAIN_A2

R150.1 J1

Socket

D11Diode

R17100K

C141nF

D5Diode

DRAIN_A1

SOURCE_A1C131nF

R16100K Q_A1

MOSFET-N

Q_A2MOSFET-N

P1

Mounting pad

P2

Mounting pad

P3

Mounting pad

P4

Mounting pad

1234

P5

Header 4GND_P

Pulse_A1Pulse_A2

FAIL

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 28-4-2016 Sheet ofFile: C:\Users\..\T_type_powersupplies.SchDoc Drawn By:

1

2

7

6

5

MGJ2

+Vin

-Vin-Vout

0V

+Vout

DCDC1

Murata MGJ2 Series

+15V_A1

-5V_A1

SOURCE_A1C31100nF

C32100nF

C30100nF

C33100nF

+5V

GND_P

L3

22uH

L4

22uH

1

2

7

6

5

MGJ2

+Vin

-Vin-Vout

0V

+Vout

DCDC2

Murata MGJ2 Series

C36100nF

+5V+15V_A2

-5V_A2

C34100nF

C37100nF

GND_P

L5

22uH

L6

22uH

C35100nF

12

P23

Header 2

12

P24

Header 2

SOURCE_A2

A1

A2

A3

A4

130 Appendix D. PCB design

D.2 Board lay-out

D.2. Board lay-out 131

Fig. D.1: PCB layout - Buck


Fig. D.2: PCB layout - ZVT1

D.2. Board lay-out 133

Fig. D.3: PCB layout - ZVT2


D.3 Pictures

D.3. Pictures 135

Fig. D.4: Buck converter

Fig. D.5: Midpoint clamped SSAC


Fig. D.6: Soft switching auxiliary circuit 2

Appendix E

Measurements

137

138 Appendix E. Measurements

The measurement data that was obtained during the experiments can be found in this

appendix.

δ Vin Iin Pin Vout Iout Pout η

[/] [V] [A] [W] [V] [A] [W] [%]

0, 10 300, 00 0, 11 33, 00 28, 98 1, 04 30, 14 91, 33

0, 15 300, 00 0, 24 72, 00 43, 60 1, 57 68, 45 95, 07

0, 20 300, 00 0, 43 129, 00 58, 40 2, 10 122, 64 95, 07

0, 25 300, 00 0, 66 198, 00 72, 70 2, 62 190, 47 96, 20

0, 30 300, 00 0, 96 288, 00 87, 40 3, 15 275, 31 95, 59

0, 35 300, 00 1, 30 390, 00 102, 10 3, 68 375, 73 96, 34

0, 40 300, 00 1, 70 510, 00 116, 80 4, 21 491, 73 96, 42

0, 45 300, 00 2, 15 645, 00 131, 50 4, 74 623, 31 96, 64

0, 50 300, 00 2, 64 792, 00 146, 00 5, 26 767, 96 96, 96

0, 55 300, 00 3, 20 960, 00 160, 70 5, 79 930, 45 96, 92

0, 60 300, 00 3, 80 1140, 00 175, 40 6, 32 1108, 53 97, 24

0, 65 300, 00 4, 47 1341, 00 190, 10 6, 85 1302, 19 97, 11

0, 70 300, 00 5, 19 1557, 00 205, 20 7, 40 1518, 48 97, 53

0, 75 300, 00 5, 96 1788, 00 220, 00 7, 94 1746, 80 97, 70

0, 80 300, 00 6, 79 2037, 00 234, 90 8, 47 1989, 60 97, 67

0, 85 300, 00 7, 68 2304, 00 249, 70 9, 02 2252, 29 97, 76

0, 90 300, 00 8, 62 2586, 00 264, 70 9, 55 2527, 89 97, 75

Table E.1: Hard switched Buck - Measurements at 10 kHz

139


[/] [V] [A] [W] [V] [A] [W] [%]

0, 10 300, 00 0, 12 36, 00 29, 10 1, 05 30, 56 84, 88

0, 15 300, 00 0, 25 75, 00 43, 80 1, 58 69, 20 92, 27

0, 20 300, 00 0, 43 129, 00 58, 10 2, 09 121, 43 94, 13

0, 25 300, 00 0, 67 201, 00 72, 60 2, 61 189, 49 94, 27

0, 30 300, 00 0, 96 288, 00 87, 30 3, 15 275, 00 95, 48

0, 35 300, 00 1, 31 393, 00 102, 20 3, 69 377, 12 95, 96

0, 40 300, 00 1, 71 513, 00 116, 90 4, 22 493, 32 96, 16

0, 45 300, 00 2, 16 648, 00 131, 50 4, 74 623, 31 96, 19

0, 50 300, 00 2, 66 798, 00 146, 30 5, 28 772, 46 96, 80

0, 55 300, 00 3, 22 966, 00 161, 20 5, 81 936, 57 96, 95

0, 60 300, 00 3, 84 1152, 00 175, 90 6, 35 1116, 97 96, 96

0, 65 300, 00 4, 51 1353, 00 190, 70 6, 88 1312, 02 96, 97

0, 70 300, 00 5, 23 1569, 00 205, 50 7, 42 1524, 81 97, 18

0, 75 300, 00 6, 02 1806, 00 220, 30 7, 96 1753, 59 97, 10

0, 80 300, 00 6, 86 2058, 00 235, 20 8, 50 1999, 20 97, 14

0, 85 300, 00 7, 76 2328, 00 250, 10 9, 04 2260, 90 97, 12

0, 90 300, 00 8, 74 2622, 00 265, 10 9, 58 2539, 66 96, 86




[/] [V] [A] [W] [V] [A] [W] [%]

0, 10 300, 20 0, 14 42, 03 29, 20 1, 20 35, 04 83, 37

0, 15 300, 20 0, 28 84, 06 42, 80 1, 70 72, 76 86, 56

0, 20 300, 20 0, 46 138, 09 57, 20 2, 19 125, 27 90, 71

0, 25 300, 20 0, 71 213, 14 71, 90 2, 72 195, 57 91, 75

0, 30 300, 20 1, 01 303, 20 86, 80 3, 26 282, 97 93, 33

0, 35 300, 20 1, 37 411, 27 101, 60 3, 81 387, 10 94, 12

0, 40 300, 20 1, 79 537, 36 116, 50 4, 37 509, 11 94, 74

0, 45 300, 20 2, 26 678, 45 131, 10 4, 92 645, 01 95, 07

0, 50 300, 20 2, 78 834, 56 145, 90 5, 48 799, 53 95, 80

0, 55 300, 20 3, 37 1011, 67 160, 70 6, 03 969, 02 95, 78

0, 60 300, 20 4, 02 1206, 80 175, 60 6, 59 1157, 20 95, 89

0, 65 300, 20 4, 74 1422, 95 190, 50 7, 15 1362, 08 95, 72


141

δmain δon Ton Vin,1 Iin,1 Vin,2 Iin,2 Pin Vout Iout Pout η

[%] [%] [s] [V] [A] [V] [A] [W] [V] [A] [W] [/]

10 1 3, 33E − 07 300, 1 0, 13 150, 1 0, 01 40, 51 31, 7 1, 14 36, 14 0, 89

20 1 3, 33E − 07 300, 1 0, 45 150, 1 0, 01 136, 55 60, 3 2, 17 130, 85 0, 96

30 1 3, 33E − 07 300, 1 0, 97 150, 1 0, 04 297, 10 89, 1 3, 21 286, 01 0, 96

40 1 4, 00E − 07 300, 1 1, 72 150, 1 0, 05 523, 68 118, 6 4, 28 507, 61 0, 97

50 1 4, 00E − 07 300, 1 2, 68 150, 1 0, 06 813, 27 148 5, 34 790, 32 0, 97

60 1 4, 27E − 07 300, 1 3, 86 150, 1 0, 07 1168, 89 177, 5 6, 41 1137, 78 0, 97

70 1 4, 53E − 07 300, 1 5, 26 150, 1 0, 08 1590, 53 207 7, 49 1550, 43 0, 97

80 1 4, 67E − 07 300, 1 6, 88 150, 1 0, 09 2078, 20 236, 5 8, 55 2022, 08 0, 97

90 1 5, 07E − 07 300, 1 8, 71 150, 1 0, 10 2628, 88 266, 1 9, 63 2562, 54 0, 97

Table E.4: Buck converter with MPC SSAC at turn-on - 20 kHz

δmain δoff Toff Vin,1 Iin,1 Vin,2 Iin,2 Pin Vout Iout Pout η

[%] [%] [s] [V] [A] [V] [A] [W] [V] [A] [W] [/]

10 0, 5 6, 67E − 08 300, 1 0, 13 150, 1 0, 01 40, 51 31, 1 1, 12 34, 83 0, 86

20 0, 5 6, 67E − 08 300, 1 0, 44 150, 1 0, 01 133, 55 59, 6 2, 15 128, 14 0, 96

30 0, 5 6, 67E − 08 300, 1 0, 98 150, 1 0, 01 295, 60 88, 8 3, 20 284, 16 0, 96

40 0, 5 6, 67E − 08 300, 1 1, 73 150, 1 0, 02 522, 18 118, 2 4, 26 503, 53 0, 96

50 0, 5 6, 67E − 08 300, 1 2, 69 150, 1 0, 02 810, 27 147, 7 5, 33 787, 24 0, 97

60 0, 5 6, 67E − 08 300, 1 3, 87 150, 1 0, 03 1165, 89 177, 2 6, 39 1132, 31 0, 97

70 0, 5 6, 67E − 08 300, 1 5, 27 150, 1 0, 03 1586, 03 206, 7 7, 46 1541, 98 0, 97

80 0, 5 6, 67E − 08 300, 1 6, 89 150, 1 0, 04 2073, 69 236, 3 8, 54 2018, 00 0, 97

90 0, 5 6, 67E − 08 300, 1 8, 72 150, 1 0, 04 2622, 88 265, 9 9, 61 2555, 30 0, 97

Table E.5: Buck converter with MPC SSAC at turn-off - 20 kHz


δmain

δon

Ton

δoff

Toff

Vin,1

Iin,1

Vin,2

Iin,2

Pin

Vout

Iout

Pout

η

[%]

[%]

[s][%

][s]

[V]

[A]

[V]

[A]

[W]

[V]

[A]

[W]

[/]

101

3,33E−

070,5

6,67E−

08300,1

0,12150,1

0,0239,01

321,15

36,800,94

201

3,33E−

070,5

6,67E−

08300,1

0,44150,1

0,03136,55

60,72,19

132,930,97

301

3,33E−

070,5

6,67E−

08300,1

0,97150,1

0,05298,60

89,53,23

289,090,97

401

3,33E−

070,5

6,67E−

08300,1

1,71150,1

0,06522,18

118,64,28

507,610,97

501

3,33E−

070,5

6,67E−

08300,1

2,67150,1

0,07811,77

147,95,34

789,790,97

601

4,00E−

070,5

6,67E−

08300,1

3,85150,1

0,091168,89

177,76,41

1139,060,97

701

4,00E−

070,5

6,67E−

08300,1

5,24150,1

0,111589,04

207,17,47

1547,040,97

801

4,27E−

070,5

6,67E−

08300,1

6,85150,1

0,122073,70

236,78,56

2026,150,98

901

4,67E−

070,5

6,67E−

08300,1

8,70150,1

0,142631,88

266,39,64

2567,130,98

Tab

leE

.6:B

uck

converter

with

MP

CSSA

Cat

turn

-onan

doff

-20

kH

z

143

δ main

δ on

Ton

δ off

Toff

Vin,1

I in,1

Vin,2

I in,2

Pin

Vout

I out

Pout

η

[%]

[%]

[s]

[%]

[s]

[V]

[A]

[V]

[A]

[W]

[V]

[A]

[W]

[/]

101

3,33E−

071

6,67E−

0830

0,1

0,15

150,

10,

0451,0

235,7

01,

2845,7

00,

90

201

3,33E−

071

6,67E−

0830

0,1

0,47

150,

10,

0715

1,55

63,4

02,

2814

4,55

0,95

301

3,33E−

071

6,67E−

0830

0,1

1,00

150,

10,

1031

5,11

91,8

03,

3030

2,94

0,96

401

4,00E−

071

6,67E−

0830

0,1

1,78

150,

10,

1355

3,69

121,

704,

3953

4,26

0,96

501

4,67E−

071

6,67E−

0830

0,1

2,76

150,

10,

1785

3,79

151,

205,

4682

5,55

0,97

601

4,67E−

071

6,67E−

0830

0,1

3,94

150,

10,

2012

12,4

118

0,40

6,52

1176,2

10,

97

701

4,67E−

071

6,67E−

0830

0,1

5,34

150,

10,

2416

38,5

620

9,60

7,58

1588,7

70,

97

801

4,67E−

071

6,67E−

0830

0,1

6,97

150,

10,

2721

32,2

223

9,00

8,65

2067,3

50,

97

901

4,67E−

071

6,67E−

0830

0,1

8,82

150,

10,

2926

90,4

126

8,60

9,73

2613,4

80,

97

Tab

leE

.7:

Buck

conve

rter

wit

hM

PC

SSA

Cat

turn

-on

and

off-

40kH

z


δ Vin,1 Iin,1 Vin,2 Iin,2 Pin VR IR PR Vout Iout Pout η

[%] [V] [A] [V] [A] [W] [V] [A] [W] [V] [A] [W] [/]

55 200 0, 58 200, 1 1, 09 334, 11 200, 1 1, 53 306, 15 20, 1 1, 05 21, 11 0, 75

60 200 1, 37 200, 1 1, 20 514, 12 200, 1 1, 93 386, 19 42, 5 2, 23 94, 78 0, 74

65 200 1, 98 200, 1 1, 02 600, 10 200, 1 1, 92 384, 19 58, 4 3, 02 176, 37 0, 82

70 200 2, 86 200, 1 0, 87 746, 09 200, 1 1, 97 394, 20 78, 9 4, 04 318, 76 0, 91

75 200 3, 86 200, 1 0, 81 934, 08 200, 1 2, 02 404, 20 96, 6 5, 08 490, 73 0, 93

80 200 4, 94 200, 1 0, 87 1162, 09 200, 1 2, 03 406, 20 116, 2 6, 12 711, 14 0, 94

85 200 6, 15 200, 1 1, 03 1436, 10 200, 1 2, 03 406, 20 135, 8 7, 17 973, 69 0, 95

90 200 7, 53 200, 1 1, 31 1768, 13 200, 1 2, 03 406, 20 156, 4 8, 27 1293, 43 0, 95

95 200 8, 97 200, 1 1, 70 2134, 17 200, 1 2, 03 406, 20 176, 1 9, 32 1641, 25 0, 95

Table E.8: Buck with split DC bus 400 V - 20 kHz - hard switched


[%] [V] [A] [V] [A] [W] [V] [A] [W] [V] [A] [W] [/]

55 200 0, 58 200, 1 1, 58 432, 15 200, 1 2, 02 404, 20 19, 9 1, 04 20, 69 0, 74

60 200 1, 23 200, 1 1, 25 496, 12 200, 1 2, 02 404, 20 39, 3 2, 01 78, 99 0, 85

65 200 2 200, 1 1 600, 10 200, 1 2, 02 404, 20 57, 9 3, 03 175, 43 0, 89

70 200 2, 87 200, 1 0, 86 746, 08 200, 1 2, 02 404, 20 77, 3 4, 06 313, 83 0, 91

75 200 3, 87 200, 1 0, 81 936, 08 200, 1 2, 02 404, 20 96, 9 5, 09 493, 22 0, 92

80 200 4, 96 200, 1 0, 87 1166, 08 200, 1 2, 02 404, 20 116, 5 6, 14 715, 31 0, 93

85 200 6, 18 200, 1 1, 04 1444, 10 200, 1 2, 02 404, 20 136, 2 7, 18 977, 91 0, 94

90 200 7, 5 200, 1 1, 32 1764, 13 200, 1 2, 02 404, 20 155, 5 8, 21 1276, 65 0, 93

95 200 8, 97 200, 1 1, 7 2134, 17 200, 1 2, 02 404, 20 175, 4 9, 24 1620, 69 0, 93


145

δ main

δ on

Ton

δ off

Toff

Vin,1

I in,1

Vin,2

I in,2

Pin

VR

I RPR

Vout

I out

Pout

η

[%]

[%]

[s]

[%]

[s]

[V]

[A]

[V]

[A]

[W]

[V]

[A]

[W]

[V]

[A]

[W]

[/]

551

2,67E−

071

6,67E−

0820

00,

6720

0,1

0,62

258,

0620

0,1

1,12

224,

1122,9

1,20

27,4

80,

81

601

2,67E−

071

6,67E−

0820

01,

3320

0,1

0,30

326,

0320

0,1

1,12

224,

1141,8

2,20

91,9

60,

90

651

3,33E−

071

6,67E−

0820

02,

1220

0,1

0,08

440,

0120

0,1

1,12

224,

1161,5

3,23

198,

650,

92

701

3,33E−

071

1,33E−

0720

03,

0020

0,1

0,87

774,

0920

0,1

2,03

406,

2080,7

4,26

343,

780,

93

751

4,00E−

071

6,67E−

0820

03,

9820

0,1

0,84

964,

0820

0,1

2,02

404,

2010

05,

2952

9,00

0,94

800,

84,

00E−

071

1,52E−

2120

05,

0620

0,1

0,92

1196,0

920

0,1

2,03

406,

2011

9,1

6,30

750,

330,

95

850,

84,

67E−

070,

71,

00E−

0720

06,

3020

0,1

1,11

1482,1

120

0,1

2,03

406,

2013

9,4

7,37

1027,3

80,

95

900,

84,

67E−

071

6,67E−

0820

07,

5820

0,1

1,39

1794,1

420

0,1

2,03

406,

2015

8,2

8,38

1325,7

20,

96

951

4,67E−

071

7,33E−

0820

08,

7220

0,1

1,70

2084,1

720

0,1

2,03

406,

2017

4,6

9,24

1613,3

00,

96

Tab

leE

.10:

Buck

wit

hsp

lit

DC

bus

400

V-

20kH

z-

MP

CSSA

C


δmain

δon

Ton

δoff

Toff

Vin,1

Iin,1

Vin,2

Iin,2

Pin

VR

IR

PR

Vout

Iout

Pout

η

[%]

[%]

[s][%

][s]

[V]

[A]

[V]

[A]

[W]

[V]

[A]

[W]

[V]

[A]

[W]

[/]

551,5

2,67E−

071,5

6,05E−

08200

0,72200,1

1,51446,15

200,12,02

404,2024,8

1,3032,24

0,77

601,5

3,33E−

071,5

6,13E−

08200

1,30200,1

1,26512,13

200,12,02

404,2044,7

2,1495,66

0,89

651,5

3,33E−

071,5

6,22E−

08200

2,00200,1

1,08616,11

200,12,02

404,2063,7

3,06194,92

0,92

701,5

3,33E−

071,5

1,02E−

07200

3,04200,1

0,88784,09

200,12,02

404,2082,5

4,33357,23

0,94

751,5

3,73E−

071,5

1,03E−

07200

4,04200,1

0,87982,09

200,12,02

404,20102,1

5,37548,28

0,95

801,5

3,73E−

071,5

6,33E−

08200

5,12200,1

0,961216,10

200,12,02

404,20120,8

6,37769,50

0,95

851,5

3,73E−

071,3

6,55E−

08200

6,31200,1

1,161494,12

200,12,02

404,20140,1

7,401036,74

0,95

901,5

4,40E−

071,3

6,63E−

08200

7,66200,1

1,471826,15

200,12,02

404,20159,9

8,461352,75

0,95

951,2

4,40E−

071

6,72E−

08200

9,09200,1

1,882194,19

200,12,02

404,20179,2

9,501702,40

0,95

Tab

leE

.11:B

uck

with

split

DC

bus

400V

-30

kH

z-

MP

CSSA

C

147


[%] [V] [A] [V] [A] [W] [V] [A] [W] [V] [A] [W] [/]

55 300 0, 88 300 1, 80 804, 0 300 2, 37 711, 0 41, 1 1, 47 60, 42 0, 65

60 300 1, 38 300 1, 57 885, 0 300 2, 37 711, 0 61, 4 2, 19 134, 47 0, 77

65 300 2, 19 300 1, 32 1053, 0 300 2, 37 711, 0 90, 6 3, 25 294, 45 0, 86

70 300 3, 12 300 1, 18 1290, 0 300 2, 37 711, 0 120 4, 31 517, 20 0, 89

75 300 4, 15 300 1, 15 1590, 0 300 2, 37 711, 0 149, 3 5, 37 801, 74 0, 91

80 300 5, 29 300 1, 23 1956, 0 300 2, 37 711, 0 178, 9 6, 44 1152, 12 0, 93

85 300 6, 55 300 1, 41 2388, 0 300 2, 37 711, 0 208, 3 7, 51 1564, 33 0, 93

90 300 7, 91 300 1, 70 2883, 0 300 2, 37 711, 0 237, 8 8, 58 2040, 32 0, 94

95 300 9, 23 300 2, 08 3393, 0 300 2, 37 711, 0 263, 6 9, 52 2509, 47 0, 94



[%] [V] [A] [V] [A] [W] [V] [A] [W] [V] [A] [W] [/]

55 300 0, 73 300 1, 88 783, 0 300 2, 35 705, 0 34, 1 1, 21 41, 3 0, 53

60 300 1, 44 300 1, 56 900, 0 300 2, 35 705, 0 62, 8 2, 24 140, 7 0, 72

65 300 2, 26 300 1, 33 1077, 0 300 2, 36 708, 0 91, 9 3, 28 301, 4 0, 82

70 300 3, 20 300 1, 21 1323, 0 300 2, 36 708, 0 121, 3 4, 34 526, 4 0, 86

75 300 4, 25 300 1, 20 1635, 0 300 2, 36 708, 0 150, 7 5, 41 815, 3 0, 88

80 300 5, 44 300 1, 31 2025, 0 300 2, 36 708, 0 180, 5 6, 49 1171, 4 0, 89



δmain

δon

Ton

δoff

Toff

Vin,1

Iin,1

Vin,2

Iin,2

Pin

VR

IR

PR

Vout

Iout

Pout

η

[%]

[%]

[s][%

][s]

[V]

[A]

[V]

[A]

[W]

[V]

[A]

[W]

[V]

[A]

[W]

[/]

551

2,67E−

071

6,67E−

08300

0,83300

1,80789,00

3002,35

705,0039,4

1,4356,34

0,67

601

2,67E−

071

6,67E−

08300

1,47300

1,51894,00

3002,35

705,0065,6

2,38156,13

0,83

651

3,33E−

071

6,67E−

08300

2,29300

1,291074,00

3002,35

705,0095,3

3,45328,79

0,89

701

3,33E−

071

1,33E−

07300

3,17300

1,181305,00

3002,36

708,00123,4

4,46550,36

0,92

751

4,00E−

071

6,67E−

08300

4,24300

1,171623,00

3002,36

708,00153,9

5,56855,68

0,94

800,8

4,00E−

071

1,52E−

21300

5,35300

1,261983,00

3002,36

708,00182,6

6,601205,16

0,95

850,8

4,00E−

070,8

6,67E−

08300

6,58300

1,462412,00

3002,36

708,00211,6

7,651618,74

0,95

900,8

4,67E−

070,8

6,67E−

08300

7,97300

1,782925,00

3002,36

708,00241,5

8,742110,71

0,95

951

4,67E−

071

7,33E−

08300

9,23300

2,143411,00

3002,37

711,00265

9,602544,00

0,94

Tab

leE

.14:B

uck

with

split

DC

bus

600V

-20

kH

z-

MP

CSSA

C

149

δ main

δ on

Ton

δ off

Toff

Vin,1

I in,1

Vin,2

I in,2

Pin

VR

I RPR

Vout

I out

Pout

η

[%]

[%]

[s]

[%]

[s]

[V]

[A]

[V]

[A]

[W]

[V]

[A]

[W]

[V]

[A]

[W]

[/]

551

2,67E−

071

6,85E−

0830

0,0

0,89

300

1,79

804,

030

02,

3570

5,0

41,3

1,51

62,3

60,

63

601

3,33E−

071

6,80E−

0830

0,0

1,61

300

1,49

930,

030

02,

3570

5,0

70,7

2,57

181,

700,

81

651

3,33E−

071

6,88E−

0830

0,0

2,41

300

1,30

1113,0

300

2,35

705,

099,2

3,59

356,

130,

87

701

3,73E−

071

6,83E−

0830

0,0

3,33

300

1,21

1362,0

300

2,35

705,

012

8,2

4,64

594,

850,

91

751

4,00E−

071

6,25E−

0830

0,0

4,34

300

1,22

1668,0

300

2,35

705,

015

6,5

5,66

885,

790,

92

801

4,00E−

071

6,87E−

0830

0,0

5,47

300

1,33

2040,0

300

2,35

705,

018

5,2

6,70

1240,8

40,

93

851

4,27E−

071

6,95E−

0830

0,0

6,74

300

1,55

2487,0

300

2,35

705,

021

4,9

7,77

1669,7

70,

94

901

4,27E−

071

6,50E−

0830

0,0

8,09

300

1,87

2988,0

300

2,35

705,

024

4,2

8,85

2161,1

70,

95

951

4,27E−

071

6,58E−

0830

0,0

9,21

300

2,25

3438,0

300

2,35

705,

026

4,4

9,58

2532,9

50,

93

Tab

leE

.15:

Buck

wit

hsp

lit

DC

bus

600

V-

30kH

z-

MP

CSSA

C



[%] [V] [A] [V] [A] [W] [V] [A] [W] [V] [A] [W] [/]

55 300 0, 84 300 1, 74 774, 0 300 2, 34 702, 0 40, 8 1, 47 60, 0 0, 83

60 300 1, 29 300 1, 53 846, 0 300 2, 34 702, 0 59, 2 2, 13 126, 1 0, 88

65 300 2, 10 300 1, 26 1008, 0 300 2, 34 702, 0 88, 7 3, 20 283, 8 0, 93

70 300 3, 01 300 1, 10 1233, 0 300 2, 34 702, 0 118, 2 4, 27 504, 7 0, 95

75 300 4, 02 300 1, 05 1521, 0 300 2, 34 702, 0 147, 7 5, 34 788, 7 0, 96

80 300 5, 16 300 1, 11 1881, 0 300 2, 34 702, 0 177, 5 6, 42 1139, 6 0, 97

85 300 6, 40 300 1, 27 2301, 0 300 2, 33 699, 0 207, 3 7, 49 1552, 7 0, 97

90 300 7, 77 300 1, 54 2793, 0 300 2, 33 699, 0 237, 2 8, 59 2037, 5 0, 97

95 300 9, 20 300 1, 93 3339, 0 300 2, 33 699, 0 265, 3 9, 64 2557, 5 0, 97

Table E.16: Buck with split DC bus 600 V - 20 kHz - Silicon Carbide


[%] [V] [A] [V] [A] [W] [V] [A] [W] [V] [A] [W] [/]

55 300 0, 65 300 1, 87 756 300 2, 34 702 32, 0 1, 17 37, 4 0, 69

60 300 1, 34 300 1, 52 858 300 2, 34 702 60, 9 2, 20 134, 0 0, 86

65 300 2, 15 300 1, 26 1023 300 2, 34 702 90, 2 3, 25 293, 2 0, 91

70 300 3, 06 300 1, 12 1254 300 2, 34 702 119, 7 4, 31 515, 9 0, 93

75 300 4, 09 300 1, 06 1545 300 2, 34 702 149, 4 5, 38 803, 8 0, 95

80 300 5, 23 300 1, 13 1908 300 2, 33 699 179, 0 6, 45 1154, 6 0, 95

85 300 6, 48 300 1, 30 2334 300 2, 33 699 208, 7 7, 54 1573, 6 0, 96

90 300 7, 85 300 1, 57 2826 300 2, 32 696 238, 5 8, 64 2060, 6 0, 97

Table E.17: Buck with split DC bus 600 V - 40 kHz - Silicon Carbide

Appendix F

Data sheets

In this appendix, the most relevant parts of the data sheets are published. Not all the

used components are discussed. Two IGBTs and a SiC Power MOSFET are included since

their characteristics are important in the framework of this thesis.

151

Features

E

G

n-channel

C

=

!"#$%&' ( )* ($%&'+ ,-.,/ ++(*+ )$*'+"012

* )* ($%&'*(),-.,/ $%&'345(*6))

7/+89:;;1

TO-247AC

!

" # $%& # ' ( ) #* (+, ) - . / " +, "( $ 0" +, "( $ 0 1$2 3 4 $5

4 $67 -8*0-*8*0 97 9

+:60-+- * ;7<8*=< 9

>

5θ 2 . ??? ??? *@@

5θ 2 ( ??? ??? *@ A>5θ 4676 7 ??? *! ???

5θ 2' ;6 B$ ??? ??? !> >C ??? 08*9 ??? 8D9

www.irf.com 1

<+

2 www.irf.com

E .C89 F #0 - 'E . C89 F - ! 4)*#

E .C89 F G !! 1(B F !0 F

5 F - F '6# 177(B F G@ 65Ω ) F ! -0 B HH 14C& F *# F % %B*

1774C& F *G- F 2 4)*G66# 4C& F -*@- !*0

1(B F ! F 64)*6# 5 F - F '6#

177(B F ! F 65Ω ) F F B HH

4C& F @*! F 2 % %B*& F - F I + 7 $

$$ F # F 1$$ F F $) - 4)*@

5% 7$ F # F J*+ID (5% 5%B F 0- G 4)*

F 0 0 !#*' ("5% 5%B F !* #* ' 4)*

F 0* E (5% 5%BC F ! -# 4)*

F -- ## 0A'AK A ("57)75%B F -- F 'AK 4)*

( F # F @

! "#$

F F 6K'

ΔΔ $77*7 F *!- F A 6* ' 4 F *!- -* '

F *G@ F !' 4)*6F *!@ F '6

.C C -* F 0* 6K'ΔAΔ $77*7C C F F A 6K'

) 0 ! F 4 6' L. F F K' 6

F F 66 ()($ F *0 -*- #*' 4)*-

F *! -* #*'6 . & F F / ' /

% ! "#$

INSULATED GATE BIPOLAR TRANSISTOR WITHULTRAFAST SOFT RECOVERY DIODE

Features

Benefits

Absolute Maximum Ratings

Thermal Resistance

Parameter Min. Typ. Max. UnitsRθJC Junction-to-Case - IGBT ––– ––– 0.42RθJC Junction-to-Case - Diode ––– ––– 0.83 °C/WRθCS Case-to-Sink, flat, greased surface ––– 0.24 –––RθJA Junction-to-Ambient, typical socket mount ––– ––– 40Wt Weight ––– 6 (0.21) ––– g (oz)ZθJC Transient Thermal Impedance Junction-to-Case (Fig.24)

E

G

C

IRGP30B120KD-EMotor Control Co-Pack IGBT

TO-247AD

N-channel

www.irf.com 1

Parameter Max. UnitsVCES Collector-to-Emitter Breakdown Voltage 1200 VIC @ TC = 25°C Continuous Collector Current (Fig.1) 60IC @ TC = 100°C Continuous Collector Current (Fig.1) 30ICM Pulsed Collector Current (Fig.3, Fig. CT.5) 120ILM Clamped Inductive Load Current(Fig.4, Fig. CT.2) 120 AIF @ TC = 100°C Diode Continuous Forward Current 30IFM Diode Maximum Forward Current 120VGE Gate-to-Emitter Voltage ± 20 VPD @ TC = 25°C Maximum Power Dissipation (Fig.2) 300PD @ TC = 100°C Maximum Power Dissipation (Fig.2) 120TJ Operating Junction and -55 to + 150TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds 300, (0.063 in. (1.6mm) from case)°C

Mounting Torque, 6-32 or M3 screw. 10 lbf•in (1.1N•m)

• Low VCE(on) Non Punch Through (NPT) Technology • Low Diode VF (1.76V Typical @ 25A & 25°C) • 10 μs Short Circuit Capability • Square RBSOA • Ultrasoft Diode Recovery Characteristics • Positive VCE(on) Temperature Coefficient • Extended Lead TO-247AD Package

• Benchmark Efficiency for Motor Control Applications • Rugged Transient Performance • Low EMI • Significantly Less Snubber Required • Excellent Current Sharing in Parallel Operation • Longer leads for Easier Mounting

VCES = 1200V

VCE(on) typ. = 2.28V

VGE = 15V, IC = 25A, 25°C

IRGP30B120KD-E

2 www.irf.com

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)Parameter Min. Typ. Max. Units Conditions Fig.

V(BR)CES Collector-to-Emitter Breakdown Voltage 1200 V VGE = 0V,Ic =250 μA

ΔV(BR)CES / ΔTj Temperature Coeff. of Breakdown Voltage +1.2 V/°C VGE = 0V, Ic = 1 mA ( 25 -125 oC )

2.28 2.48 IC = 25A, VGE = 15V 5, 6

Collector-to-Emitter Saturation 2.46 2.66 IC = 30A, VGE = 15V 7, 9

VCE(on) Voltage 3.43 4.00 V IC = 60A, VGE = 15V 10

2.74 3.10 IC = 25A, VGE = 15V, TJ = 125°C 11

2.98 3.35 IC = 30A, VGE = 15V, TJ = 125°C

VGE(th) Gate Threshold Voltage 4.0 5.0 6.0 V VCE = VGE, IC = 250 μA 9,10,11,12

ΔVGE(th) / ΔTj Temperature Coeff. of Threshold Voltage - 1.2 mV/oC VCE = VGE, IC = 1 mA ( 25 -125 oC )

gfe Forward Transconductance 14.8 16.9 19.0 S VCE = 50V, IC = 25A, PW=80μs

250 VGE = 0V,VCE = 1200V

ICES Zero Gate Voltage Collector Current 325 675 μA VGE = 0v, VCE = 1200V, TJ =125°C

2000 VGE = 0v, VCE = 1200V, TJ =150°C

1.76 2.06 IC = 25A

VFM Diode Forward Voltage Drop 1.86 2.17 V IC = 30A 8

1.87 2.18 IC = 25A, TJ = 125°C

2.01 2.40 IC = 30A, TJ = 125°C

IGES Gate-to-Emitter Leakage Current ±100 nA VGE = ±20V

Switching Characteristics @ TJ = 25°C (unless otherwise specified)Parameter Min. Typ. Max. Units Conditions Fig.

Qg Total Gate charge (turn-on) 169 254 IC = 25A 23

Qge Gate - Emitter Charge (turn-on) 19 29 nC VCC =600V CT 1

Qgc Gate - Collector Charge (turn-on) 82 123 VGE = 15V

Eon Turn-On Switching Loss 1066 1250 IC = 25A, VCC = 600V CT 4

Eoff Turn-Off Switching Loss 1493 1800 μJ VGE = 15V, Rg = 5Ω, L=200μH WF1

Etot Total Switching Loss 2559 3050 TJ = 25oC, Energy losses include tail and diode reverse recovery

WF2

Eon Turn-on Switching Loss 1660 1856 Ic =25A, VCC=600V 13, 15

Eoff Turn-off Switching Loss 2118 2580 μJ VGE = 15V, Rg = 5Ω, L=200μH CT 4

Etot Total Switching Loss 3778 4436 TJ = 125oC, Energy losses include tail and diode reverse recovery

WF1 & 2

td(on) Turn - on delay time 50 65 Ic =25A, VCC=600V 14, 16

tr Rise time 25 35 ns VGE = 15V, Rg = 5Ω, L=200μH CT 4

td(off) Turn - off delay time 210 230 TJ = 125oC, WF1

tf Fall time 60 75 WF2

Cies Input Capacitance 2200 VGE = 0V

Coes Output Capacitance 210 pF VCC = 30V 22

Cres Reverse Transfer Capacitance 85 f = 1.0 MHz

TJ =150oC, Ic = 120A 4

RBSOA Reverse bias safe operating area FULL SQUARE VCC = 1000V, VP = 1200V CT 2

Rg = 5Ω, VGE = +15V to 0 V

TJ = 150oC CT 3

SCSOA Short Circuit Safe Operating Area 10 ---- ---- μs VCC = 900V,VP = 1200V WF4

Rg = 5Ω, VGE = +15V to 0 V

Erec Reverse recovery energy of the diode 1820 2400 μJ TJ = 125oC 17,18,19

trr Diode Reverse recovery time 300 ns VCC = 600V, Ic = 25A 20, 21

Irr Peak Reverse Recovery Current 34 38 A VGE = 15V, Rg = 5Ω, L=200μH CT 4, WF3

Le Internal Emitter Inductance 13 nH Measured 5 mm from the package.

1 C2M0080120D Rev. A

C2M0080120DSilicon Carbide Power MOSFET Z-FET

TM MOSFET

N-Channel Enhancement Mode Features

• High Speed Switching with Low Capacitances• High Blocking Voltage with Low RDS(on)• Easy to Parallel and Simple to Drive• Avalanche Ruggedness• Resistant to Latch-Up• Halogen Free, RoHS Compliant

Benefits

• HigherSystemEfficiency• Reduced Cooling Requirements• Increased System Switching Frequency

Applications

• Solar Inverters • High Voltage DC/DC Converters• Motor Drives• Switch Mode Power Supplies• UPS

Package

TO-247-3

Part Number Package

C2M0080120D TO-247-3

VDS 1200 V

ID @ 25˚C 31.6 A

RDS(on) 80 mΩ

Maximum Ratings (TC=25˚Cunlessotherwisespecified)

Symbol Parameter Value Unit Test Conditions Note

IDS (DC) Continuous Drain Current31.6

AVGS@20 V, TC =25˚C Fig. 16

20 VGS@20 V, TC =100˚C

IDS (pulse) Pulsed Drain Current 80 APulse width tP = 50 μs

duty limited by Tjmax, TC =25˚C

VGS Gate Source Voltage -10/+25 V

PtotPower Dissipation 208 W TC=25˚C Fig. 15

TJ , TstgOperating Junction and Storage Temperature -55 to

+150 ˚C

TLSolder Temperature 260 ˚C 1.6mm (0.063”) from case for 10s

Md Mounting Torque 18.8

Nmlbf-in M3 or 6-32 screw

2 C2M0080120D Rev. A

Electrical Characteristics (TC=25˚Cunlessotherwisespecified)

Symbol Parameter Min. Typ. Max. Unit Test Conditions Note

V(BR)DSS Drain-Source Breakdown Voltage 1200 V VGS = 0 V, ID=100μA

VGS(th)Gate Threshold Voltage

1.7 2.2V

VDS = 10V, ID = 1 mA

Fig. 83.2 VDS = 10V, ID = 10 mA

1.2 1.7V

VDS = 10V, ID = 1 mA, TJ = 150ºC

TBD VDS = 10V, ID = 10 mA, TJ = 150ºC

IDSS Zero Gate Voltage Drain Current1 100

μAVDS = 1200 V, VGS = 0 V

10 250 VDS = 1200 V, VGS = 0 V TJ = 150ºC

IGSS Gate-Source Leakage Current 0.25 μA VGS = 20 V, VDS = 0 V

RDS(on) Drain-Source On-State Resistance80 98

mΩVGS = 20 V, ID = 20 A

Fig. 6150 208 VGS = 20 V, ID = 20A, TJ = 150ºC

gfs Transconductance9.8

SVDS= 20 V, IDS= 20 A

Fig. 48.5 VDS= 20 V, IDS= 20 A, TJ = 150ºC

Ciss Input Capacitance 950

pFVGS = 0 V

VDS = 1000 V

f = 1 MHz

VAC = 25 mV

Fig. 13, 14

Coss Output Capacitance 80

Crss Reverse Transfer Capacitance 6.5

Eoss Coss Stored Energy 40 μJ Fig. 12

td(on)v Turn-On Delay Time 12.0

ns

VDD = 800 V, VGS = 0/20 V

ID = 20 A

RG(ext)=0Ω,RL=40Ω

Timing relative to VDS

Fig. 20tfv Fall Time 18.4

td(off)v Turn-Off Delay Time 23.2

trv Rise Time 13.6

RG Internal Gate Resistance 4.6 Ω f = 1 MHz, VAC = 25 mV

Built-in SiC Body Diode Characteristics

Symbol Parameter Typ. Max. Unit Test Conditions Note

VSD Diode Forward Voltage3.3

VVGS = -5 V, IF=10 A, TJ = 25 ºC

3.1 VGS = -2 V, IF=10 A, TJ = 25 ºC

trr Reverse Recovery Time 40 ns VGS = -5 V, IF=20 A, TJ = 25 ºCVR = 800 V, diF/dt= 350A/μs

Qrr Reverse Recovery Charge 165 nC

Irrm Peak Reverse Recovery Current 6.4 A

Thermal Characteristics


RθJC Thermal Resistance from Junction to Case 0.60 0.65

K/W Fig. 17RθCS Case to Sink, w/ Thermal Compound TBD

RθJA Thermal Resistance From Junction to Ambient 40

Gate Charge Characteristics


Qgs Gate to Source Charge 10.8

nCVDS = 800 V, VGS = 0/20 VID =20 APer JEDEC24 pg 27

Fig. 28Qgd Gate to Drain Charge 18.0

Qg Gate Charge Total 49.2

158 Appendix F. Data sheets

Bibliography

[1] G. Hua, C. Leu, Y. Jiang, and F. Lee, “Novel zero-voltage-transition pwm converters,”

Power Electronics, IEEE Transactions on, vol. 9, pp. 213–219, Mar 1994.

[2] C.-M. Wang, “Novel zero-voltage-transition pwm dc-dc converters,” Industrial Elec-

tronics, IEEE Transactions on, vol. 53, no. 1, pp. 254–262, 2006.

[3] C. M. De Oliveira Stein, H. A. Grundling, H. Pinheiro, J. R. Pinheiro, and H. L. Hey,

“Zero-current and zero-voltage soft-transition commutation cell for pwm inverters,”

Power Electronics, IEEE Transactions on, vol. 19, no. 2, pp. 396–403, 2004.

[4] M. Krogemann, The Parallel Resonant DC Link Inverter-A Soft Switching Inverter

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[7] M. Hermwille, IGBT Driver Calculation. SEMIKRON, 2007.

[8] D. Bozalakov, T. Vandoorn, B. Meersman, G. Papagiannis, A. Chrysochos, and

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Power Delivery, vol. PP, no. 99, pp. 1–1, 2016.

[9] D. Bozalakov, T. Vandoorn, B. Meersman, C. Demoulias, and L. Vandevelde, “Voltage

dip mitigation capabilities of three-phase damping control strategy,” Electric Power

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[10] D. Bozalakov, T. Vandoorn, B. Meersman, and L. Vandevelde, “Overview of increasing

the penetration of renewable energy sources in the distribution grid by developing

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[11] International Rectifier, IGBT Characteristics, 2012.

[12] N. Mohan and T. M. Undeland, Power electronics: converters, applications, and de-

sign. John Wiley, 2003.

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[13] L. Lasne, Electronique de puissance. Dunod, 2003.

[14] J. Pollefliet, Vermogenselektronica. Academia Press, 2003.

[15] P. Haaf and J. Harper, Understanding diode reverse recovery and its effect on switching

losses. FairchildSemiconductor Europe, 2007.

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switching performance. Vishay Siliconix, 2004.

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croelectronics, 1999.

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tion. Springer, 2014.

[20] C. Basso, “Get rid of the miller effect with zero voltage switching,” November 2004.

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app/answers/detail/a_id/215. Accessed: 2015-10-24.

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betrekking tot de verbetering van de netkwaliteit. PhD thesis, University of Ghent,

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